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author | Daniel Baumann <daniel@debian.org> | 2024-10-18 20:33:49 +0200 |
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committer | Daniel Baumann <daniel@debian.org> | 2024-12-12 23:57:56 +0100 |
commit | e68b9d00a6e05b3a941f63ffb696f91e554ac5ec (patch) | |
tree | 97775d6c13b0f416af55314eb6a89ef792474615 /options/gitignore/SynopsysVCS | |
parent | Initial commit. (diff) | |
download | forgejo-e68b9d00a6e05b3a941f63ffb696f91e554ac5ec.tar.xz forgejo-e68b9d00a6e05b3a941f63ffb696f91e554ac5ec.zip |
Adding upstream version 9.0.3.
Signed-off-by: Daniel Baumann <daniel@debian.org>
Diffstat (limited to '')
-rw-r--r-- | options/gitignore/SynopsysVCS | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/options/gitignore/SynopsysVCS b/options/gitignore/SynopsysVCS new file mode 100644 index 0000000..ad751f6 --- /dev/null +++ b/options/gitignore/SynopsysVCS @@ -0,0 +1,36 @@ +# Waveform formats +*.vcd +*.vpd +*.evcd +*.fsdb + +# Default name of the simulation executable. A different name can be +# specified with this switch (the associated daidir database name is +# also taken from here): -o <path>/<filename> +simv + +# Generated for Verilog and VHDL top configs +simv.daidir/ +simv.db.dir/ + +# Infrastructure necessary to co-simulate SystemC models with +# Verilog/VHDL models. An alternate directory may be specified with this +# switch: -Mdir=<directory_path> +csrc/ + +# Log file - the following switch allows to specify the file that will be +# used to write all messages from simulation: -l <filename> +*.log + +# Coverage results (generated with urg) and database location. The +# following switch can also be used: urg -dir <coverage_directory>.vdb +simv.vdb/ +urgReport/ + +# DVE and UCLI related files. +DVEfiles/ +ucli.key + +# When the design is elaborated for DirectC, the following file is created +# with declarations for C/C++ functions. +vc_hdrs.h |