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author | Macpaul Lin <macpaul.lin@mediatek.com> | 2020-02-21 10:52:20 +0100 |
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committer | Stephen Boyd <sboyd@kernel.org> | 2020-05-29 06:22:47 +0200 |
commit | 0502f26c6441d82cf7299678198b644f3838e871 (patch) | |
tree | f1a61ce8fbd823aee7ac4bf83eda9b3f87b0c3b7 | |
parent | dt-bindings: clock: mediatek: document clk bindings mipi0a for Mediatek MT676... (diff) | |
download | linux-0502f26c6441d82cf7299678198b644f3838e871.tar.xz linux-0502f26c6441d82cf7299678198b644f3838e871.zip |
dt-bindings: clock: mediatek: document clk bindings vcodecsys for Mediatek MT6765 SoC
This patch adds the binding documentation for vcodecsys.
Signed-off-by: Mars Cheng <mars.cheng@mediatek.com>
Signed-off-by: Owen Chen <owen.chen@mediatek.com>
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Link: https://lore.kernel.org/r/1582278742-1626-4-git-send-email-macpaul.lin@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-rw-r--r-- | Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt new file mode 100644 index 000000000000..c877bcc1a5c5 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,vcodecsys.txt @@ -0,0 +1,27 @@ +Mediatek vcodecsys controller +============================ + +The Mediatek vcodecsys controller provides various clocks to the system. + +Required Properties: + +- compatible: Should be one of: + - "mediatek,mt6765-vcodecsys", "syscon" +- #clock-cells: Must be 1 + +The vcodecsys controller uses the common clk binding from +Documentation/devicetree/bindings/clock/clock-bindings.txt +The available clocks are defined in dt-bindings/clock/mt*-clk.h. + +The vcodecsys controller also uses the common power domain from +Documentation/devicetree/bindings/soc/mediatek/scpsys.txt +The available power doamins are defined in dt-bindings/power/mt*-power.h. + +Example: + +venc_gcon: clock-controller@17000000 { + compatible = "mediatek,mt6765-vcodecsys", "syscon"; + reg = <0 0x17000000 0 0x10000>; + power-domains = <&scpsys MT6765_POWER_DOMAIN_VCODEC>; + #clock-cells = <1>; +}; |