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| author | Conor Dooley <conor.dooley@microchip.com> | 2024-10-11 16:00:43 +0200 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2025-01-22 00:35:13 +0100 |
| commit | 04aa999eb96fdc8d3cf2b2d98363d6372befaef2 (patch) | |
| tree | 62a79b5535327b227db281503bdc751a620eb711 /Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | |
| parent | PCI: microchip: Set inbound address translation for coherent or non-coherent ... (diff) | |
| download | linux-04aa999eb96fdc8d3cf2b2d98363d6372befaef2.tar.xz linux-04aa999eb96fdc8d3cf2b2d98363d6372befaef2.zip | |
dt-bindings: PCI: microchip,pcie-host: Allow dma-noncoherent
PolarFire SoC may be configured in a way that requires non-coherent DMA
handling. On RISC-V, buses are coherent by default & the dma-noncoherent
property is required to denote buses or devices that are non-coherent.
Link: https://lore.kernel.org/r/20241011140043.1250030-4-daire.mcnamara@microchip.com
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Rob Herring <robh@kernel.org>
Diffstat (limited to '')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 2e1547569702..103574d18dbc 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -50,6 +50,8 @@ properties: items: pattern: '^fic[0-3]$' + dma-coherent: true + ranges: minItems: 1 maxItems: 3 |