diff options
| author | Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> | 2023-01-13 11:33:45 +0100 |
|---|---|---|
| committer | Wim Van Sebroeck <wim@linux-watchdog.org> | 2023-02-18 15:11:38 +0100 |
| commit | 733318534849044089de8c818a2fb1c67fa39bd1 (patch) | |
| tree | 68bf4056b9ad5763c19f1a158a7d8425db36c07d /Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | |
| parent | dt-bindings: watchdog: qcom-wdt: allow interrupts (diff) | |
| download | linux-733318534849044089de8c818a2fb1c67fa39bd1.tar.xz linux-733318534849044089de8c818a2fb1c67fa39bd1.zip | |
dt-bindings: watchdog: qcom-wdt: merge MSM timer
Merge Qualcomm MSM timer bindings into watchdog, because the timer
compatibles are already included here and the hardware is quite similar.
While converting the MSM timer bindings, adjust clock-frequency
property to take only one frequency, instead of two, because:
1. DT schema does not allow to frequencies,
2. The Linux timer driver reads only first frequency.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20221212163532.142533-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Diffstat (limited to '')
| -rw-r--r-- | Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index b7fc57f4800e..837ce9112071 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -10,6 +10,9 @@ maintainers: - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> properties: + $nodename: + pattern: "^(watchdog|timer)@[0-9a-f]+$" + compatible: oneOf: - items: @@ -48,6 +51,20 @@ properties: clocks: maxItems: 1 + clock-names: + items: + - const: sleep + + clock-frequency: + description: + The frequency of the general purpose timer in Hz. + + cpu-offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Per-CPU offset used when the timer is accessed without the CPU remapping + facilities. The offset is cpu-offset + (0x10000 * cpu-nr). + interrupts: minItems: 1 maxItems: 5 @@ -67,12 +84,27 @@ allOf: const: qcom,kpss-wdt then: properties: + clock-frequency: false + cpu-offset: false interrupts: minItems: 1 items: - description: Bark - description: Bite + else: + properties: + interrupts: + minItems: 3 + items: + - description: Debug + - description: First general purpose timer + - description: Second general purpose timer + - description: First watchdog + - description: Second watchdog + required: + - clock-frequency + unevaluatedProperties: false examples: @@ -86,3 +118,20 @@ examples: interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; timeout-sec = <10>; }; + + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + watchdog@200a000 { + compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer"; + interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>, + <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>; + reg = <0x0200a000 0x100>; + clock-frequency = <25000000>; + clocks = <&sleep_clk>; + clock-names = "sleep"; + cpu-offset = <0x80000>; + }; |