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author | Daniel Kurtz <djkurtz@chromium.org> | 2018-07-02 23:19:55 +0200 |
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committer | Mark Brown <broonie@kernel.org> | 2018-07-03 17:15:32 +0200 |
commit | df61f9f76609456efbc60d495b3235baf7d07691 (patch) | |
tree | dec4720c54ac5b3a2470d6656a7f3863f57063a3 /Documentation | |
parent | ASoC: AMD: Reset bytescount when starting transaction (diff) | |
download | linux-df61f9f76609456efbc60d495b3235baf7d07691.tar.xz linux-df61f9f76609456efbc60d495b3235baf7d07691.zip |
ASoC: AMD: Simplify trigger handler
Now that the I2S channel names are fixed, and DMA data flow order is
consistent (ch1 then ch2), we can simplify channel start order:
start the upstream channel and then the downstream channel for both
playback and capture cases.
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'Documentation')
0 files changed, 0 insertions, 0 deletions