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author | Dietmar Eggemann <dietmar.eggemann@arm.com> | 2017-08-30 16:41:20 +0200 |
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committer | Simon Horman <horms+renesas@verge.net.au> | 2017-10-12 12:13:19 +0200 |
commit | 5bdc81259bb0efd5bd71820ef15757b70beae751 (patch) | |
tree | a74abfd6dbb1528e707a3b7fd9c3c5506c13e4c6 /arch/arm/boot/dts/r8a7745.dtsi | |
parent | ARM: dts: iwg20d-q7-dbcm-ca: Add device trees for camera DB (diff) | |
download | linux-5bdc81259bb0efd5bd71820ef15757b70beae751.tar.xz linux-5bdc81259bb0efd5bd71820ef15757b70beae751.zip |
ARM: dts: r8a7790: add cpu capacity-dmips-mhz information
The following 'capacity-dmips-mhz' dt property values are used:
Cortex-A15: 1024, Cortex-A7: 539
They have been derived form the cpu_efficiency values:
Cortex-A15: 3891, Cortex-A7: 2048
by scaling them so that the Cortex-A15s (big cores) use 1024.
The cpu_efficiency values were originally derived from the "Big.LITTLE
Processing with ARM Cortex™-A15 & Cortex-A7" white paper
(http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x
(3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the
Dhrystone benchmark.
The following platform is affected once cpu-invariant accounting
support is re-connected to the task scheduler:
r8a7790-lager
Signed-off-by: Dietmar Eggemann <dietmar.eggemann@arm.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7745.dtsi')
0 files changed, 0 insertions, 0 deletions