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| author | Zhenyu Ye <yezhenyu2@huawei.com> | 2020-07-15 09:19:43 +0200 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2020-07-15 16:57:30 +0200 |
| commit | b620ba54547cd0f98e35c1be102eec2cc25fda5d (patch) | |
| tree | 5057a6279d2dd70d506c1297dcc279a9e651ce65 /arch/arm64/include/asm/cpucaps.h | |
| parent | arm64: tlb: don't set the ttl value in flush_tlb_page_nosync (diff) | |
| download | linux-b620ba54547cd0f98e35c1be102eec2cc25fda5d.tar.xz linux-b620ba54547cd0f98e35c1be102eec2cc25fda5d.zip | |
arm64: tlb: Detect the ARMv8.4 TLBI RANGE feature
ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
range of input addresses. This patch detect this feature.
Signed-off-by: Zhenyu Ye <yezhenyu2@huawei.com>
Link: https://lore.kernel.org/r/20200715071945.897-2-yezhenyu2@huawei.com
[catalin.marinas@arm.com: some renaming for consistency]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/cpucaps.h')
| -rw-r--r-- | arch/arm64/include/asm/cpucaps.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h index d44ba903d11d..07b643a70710 100644 --- a/arch/arm64/include/asm/cpucaps.h +++ b/arch/arm64/include/asm/cpucaps.h @@ -63,7 +63,8 @@ #define ARM64_HAS_32BIT_EL1 53 #define ARM64_BTI 54 #define ARM64_HAS_ARMv8_4_TTL 55 +#define ARM64_HAS_TLB_RANGE 56 -#define ARM64_NCAPS 56 +#define ARM64_NCAPS 57 #endif /* __ASM_CPUCAPS_H */ |