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author | Vincenzo Frascino <vincenzo.frascino@arm.com> | 2021-03-15 14:20:17 +0100 |
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committer | Catalin Marinas <catalin.marinas@arm.com> | 2021-04-11 11:56:40 +0200 |
commit | 65812c6921cc849d86811147038dd246fa0ea18c (patch) | |
tree | 8c841e65798297cf32b10f835df7d477334d05a7 /arch/arm64/include/asm/mte.h | |
parent | arm64: mte: Conditionally compile mte_enable_kernel_*() (diff) | |
download | linux-65812c6921cc849d86811147038dd246fa0ea18c.tar.xz linux-65812c6921cc849d86811147038dd246fa0ea18c.zip |
arm64: mte: Enable async tag check fault
MTE provides a mode that asynchronously updates the TFSR_EL1 register
when a tag check exception is detected.
To take advantage of this mode the kernel has to verify the status of
the register at:
1. Context switching
2. Return to user/EL0 (Not required in entry from EL0 since the kernel
did not run)
3. Kernel entry from EL1
4. Kernel exit to EL1
If the register is non-zero a trace is reported.
Add the required features for EL1 detection and reporting.
Note: ITFSB bit is set in the SCTLR_EL1 register hence it guaranties that
the indirect writes to TFSR_EL1 are synchronized at exception entry to
EL1. On the context switch path the synchronization is guarantied by the
dsb() in __switch_to().
The dsb(nsh) in mte_check_tfsr_exit() is provisional pending
confirmation by the architects.
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Andrey Konovalov <andreyknvl@google.com>
Tested-by: Andrey Konovalov <andreyknvl@google.com>
Signed-off-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Link: https://lore.kernel.org/r/20210315132019.33202-8-vincenzo.frascino@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'arch/arm64/include/asm/mte.h')
-rw-r--r-- | arch/arm64/include/asm/mte.h | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm64/include/asm/mte.h b/arch/arm64/include/asm/mte.h index 8603c6636a7d..9a929620ca5d 100644 --- a/arch/arm64/include/asm/mte.h +++ b/arch/arm64/include/asm/mte.h @@ -98,11 +98,40 @@ static inline bool system_uses_mte_async_mode(void) { return static_branch_unlikely(&mte_async_mode); } + +void mte_check_tfsr_el1(void); + +static inline void mte_check_tfsr_entry(void) +{ + mte_check_tfsr_el1(); +} + +static inline void mte_check_tfsr_exit(void) +{ + /* + * The asynchronous faults are sync'ed automatically with + * TFSR_EL1 on kernel entry but for exit an explicit dsb() + * is required. + */ + dsb(nsh); + isb(); + + mte_check_tfsr_el1(); +} #else static inline bool system_uses_mte_async_mode(void) { return false; } +static inline void mte_check_tfsr_el1(void) +{ +} +static inline void mte_check_tfsr_entry(void) +{ +} +static inline void mte_check_tfsr_exit(void) +{ +} #endif /* CONFIG_KASAN_HW_TAGS */ #endif /* __ASSEMBLY__ */ |