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authorHans-Christian Noren Egtvedt <egtvedt@samfundet.no>2017-02-26 12:56:39 +0100
committerHans-Christian Noren Egtvedt <egtvedt@samfundet.no>2017-05-01 09:27:15 +0200
commit26202873bb51fafdaa51be3e8de7aab9beb49f70 (patch)
treec3ba9451f8fa93e6bd6347318375a7348ecb522f /arch/avr32/mach-at32ap
parentLinux 4.11 (diff)
downloadlinux-26202873bb51fafdaa51be3e8de7aab9beb49f70.tar.xz
linux-26202873bb51fafdaa51be3e8de7aab9beb49f70.zip
avr32: remove support for AVR32 architecture
This patch drops support for AVR32 architecture from the Linux kernel. The AVR32 architecture is not keeping up with the development of the kernel, and since it shares so much of the drivers with Atmel ARM SoC, it is starting to hinder these drivers to develop swiftly. Also, all AVR32 AP7 SoC processors are end of lifed from Atmel (now Microchip). Finally, the GCC toolchain is stuck at version 4.2.x, and has not received any patches since the last release from Atmel; 4.2.4-atmel.1.1.3.avr32linux.1. When building kernel v4.10, this toolchain is no longer able to properly link the network stack. Haavard and I have came to the conclusion that we feel keeping AVR32 on life support offers more obstacles for Atmel ARMs, than it gives joy to AVR32 users. I also suspect there are very few AVR32 users left today, if anybody at all. Signed-off-by: Hans-Christian Noren Egtvedt <egtvedt@samfundet.no> Signed-off-by: HÃ¥vard Skinnemoen <hskinnemoen@gmail.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Diffstat (limited to 'arch/avr32/mach-at32ap')
-rw-r--r--arch/avr32/mach-at32ap/Kconfig31
-rw-r--r--arch/avr32/mach-at32ap/Makefile8
-rw-r--r--arch/avr32/mach-at32ap/at32ap700x.c2368
-rw-r--r--arch/avr32/mach-at32ap/clock.c334
-rw-r--r--arch/avr32/mach-at32ap/clock.h35
-rw-r--r--arch/avr32/mach-at32ap/extint.c271
-rw-r--r--arch/avr32/mach-at32ap/hmatrix.c88
-rw-r--r--arch/avr32/mach-at32ap/hsmc.c282
-rw-r--r--arch/avr32/mach-at32ap/hsmc.h127
-rw-r--r--arch/avr32/mach-at32ap/include/mach/at32ap700x.h245
-rw-r--r--arch/avr32/mach-at32ap/include/mach/board.h115
-rw-r--r--arch/avr32/mach-at32ap/include/mach/chip.h19
-rw-r--r--arch/avr32/mach-at32ap/include/mach/cpu.h23
-rw-r--r--arch/avr32/mach-at32ap/include/mach/gpio.h45
-rw-r--r--arch/avr32/mach-at32ap/include/mach/hmatrix.h55
-rw-r--r--arch/avr32/mach-at32ap/include/mach/init.h18
-rw-r--r--arch/avr32/mach-at32ap/include/mach/io.h38
-rw-r--r--arch/avr32/mach-at32ap/include/mach/irq.h14
-rw-r--r--arch/avr32/mach-at32ap/include/mach/pm.h27
-rw-r--r--arch/avr32/mach-at32ap/include/mach/portmux.h30
-rw-r--r--arch/avr32/mach-at32ap/include/mach/smc.h113
-rw-r--r--arch/avr32/mach-at32ap/include/mach/sram.h30
-rw-r--r--arch/avr32/mach-at32ap/intc.c200
-rw-r--r--arch/avr32/mach-at32ap/intc.h329
-rw-r--r--arch/avr32/mach-at32ap/pdc.c47
-rw-r--r--arch/avr32/mach-at32ap/pio.c470
-rw-r--r--arch/avr32/mach-at32ap/pio.h180
-rw-r--r--arch/avr32/mach-at32ap/pm-at32ap700x.S167
-rw-r--r--arch/avr32/mach-at32ap/pm.c243
-rw-r--r--arch/avr32/mach-at32ap/pm.h112
-rw-r--r--arch/avr32/mach-at32ap/sdramc.h76
31 files changed, 0 insertions, 6140 deletions
diff --git a/arch/avr32/mach-at32ap/Kconfig b/arch/avr32/mach-at32ap/Kconfig
deleted file mode 100644
index a7bbcc82058e..000000000000
--- a/arch/avr32/mach-at32ap/Kconfig
+++ /dev/null
@@ -1,31 +0,0 @@
-if PLATFORM_AT32AP
-
-menu "Atmel AVR32 AP options"
-
-choice
- prompt "AT32AP700x static memory bus width"
- depends on CPU_AT32AP700X
- default AP700X_16_BIT_SMC
- help
- Define the width of the AP7000 external static memory interface.
- This is used to determine how to mangle the address and/or data
- when doing little-endian port access.
-
- The current code can only support a single external memory bus
- width for all chip selects, excluding the flash (which is using
- raw access and is thus not affected by any of this.)
-
-config AP700X_32_BIT_SMC
- bool "32 bit"
-
-config AP700X_16_BIT_SMC
- bool "16 bit"
-
-config AP700X_8_BIT_SMC
- bool "8 bit"
-
-endchoice
-
-endmenu
-
-endif # PLATFORM_AT32AP
diff --git a/arch/avr32/mach-at32ap/Makefile b/arch/avr32/mach-at32ap/Makefile
deleted file mode 100644
index fc09ec4bc725..000000000000
--- a/arch/avr32/mach-at32ap/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-obj-y += pdc.o clock.o intc.o extint.o pio.o hsmc.o
-obj-y += hmatrix.o
-obj-$(CONFIG_CPU_AT32AP700X) += at32ap700x.o pm-at32ap700x.o
-obj-$(CONFIG_PM) += pm.o
-
-ifeq ($(CONFIG_PM_DEBUG),y)
-CFLAGS_pm.o += -DDEBUG
-endif
diff --git a/arch/avr32/mach-at32ap/at32ap700x.c b/arch/avr32/mach-at32ap/at32ap700x.c
deleted file mode 100644
index 00d6dcc1d9b6..000000000000
--- a/arch/avr32/mach-at32ap/at32ap700x.c
+++ /dev/null
@@ -1,2368 +0,0 @@
-/*
- * Copyright (C) 2005-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/clk.h>
-#include <linux/delay.h>
-#include <linux/platform_data/dma-dw.h>
-#include <linux/fb.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-#include <linux/slab.h>
-#include <linux/gpio.h>
-#include <linux/spi/spi.h>
-#include <linux/usb/atmel_usba_udc.h>
-
-#include <linux/atmel-mci.h>
-
-#include <asm/io.h>
-#include <asm/irq.h>
-
-#include <mach/at32ap700x.h>
-#include <mach/board.h>
-#include <mach/hmatrix.h>
-#include <mach/portmux.h>
-#include <mach/sram.h>
-
-#include <sound/atmel-abdac.h>
-#include <sound/atmel-ac97c.h>
-
-#include <video/atmel_lcdc.h>
-
-#include "clock.h"
-#include "pio.h"
-#include "pm.h"
-
-
-#define PBMEM(base) \
- { \
- .start = base, \
- .end = base + 0x3ff, \
- .flags = IORESOURCE_MEM, \
- }
-#define IRQ(num) \
- { \
- .start = num, \
- .end = num, \
- .flags = IORESOURCE_IRQ, \
- }
-#define NAMED_IRQ(num, _name) \
- { \
- .start = num, \
- .end = num, \
- .name = _name, \
- .flags = IORESOURCE_IRQ, \
- }
-
-/* REVISIT these assume *every* device supports DMA, but several
- * don't ... tc, smc, pio, rtc, watchdog, pwm, ps2, and more.
- */
-#define DEFINE_DEV(_name, _id) \
-static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
-static struct platform_device _name##_id##_device = { \
- .name = #_name, \
- .id = _id, \
- .dev = { \
- .dma_mask = &_name##_id##_dma_mask, \
- .coherent_dma_mask = DMA_BIT_MASK(32), \
- }, \
- .resource = _name##_id##_resource, \
- .num_resources = ARRAY_SIZE(_name##_id##_resource), \
-}
-#define DEFINE_DEV_DATA(_name, _id) \
-static u64 _name##_id##_dma_mask = DMA_BIT_MASK(32); \
-static struct platform_device _name##_id##_device = { \
- .name = #_name, \
- .id = _id, \
- .dev = { \
- .dma_mask = &_name##_id##_dma_mask, \
- .platform_data = &_name##_id##_data, \
- .coherent_dma_mask = DMA_BIT_MASK(32), \
- }, \
- .resource = _name##_id##_resource, \
- .num_resources = ARRAY_SIZE(_name##_id##_resource), \
-}
-
-#define select_peripheral(port, pin_mask, periph, flags) \
- at32_select_periph(GPIO_##port##_BASE, pin_mask, \
- GPIO_##periph, flags)
-
-#define DEV_CLK(_name, devname, bus, _index) \
-static struct clk devname##_##_name = { \
- .name = #_name, \
- .dev = &devname##_device.dev, \
- .parent = &bus##_clk, \
- .mode = bus##_clk_mode, \
- .get_rate = bus##_clk_get_rate, \
- .index = _index, \
-}
-
-static DEFINE_SPINLOCK(pm_lock);
-
-static struct clk osc0;
-static struct clk osc1;
-
-static unsigned long osc_get_rate(struct clk *clk)
-{
- return at32_board_osc_rates[clk->index];
-}
-
-static unsigned long pll_get_rate(struct clk *clk, unsigned long control)
-{
- unsigned long div, mul, rate;
-
- div = PM_BFEXT(PLLDIV, control) + 1;
- mul = PM_BFEXT(PLLMUL, control) + 1;
-
- rate = clk->parent->get_rate(clk->parent);
- rate = (rate + div / 2) / div;
- rate *= mul;
-
- return rate;
-}
-
-static long pll_set_rate(struct clk *clk, unsigned long rate,
- u32 *pll_ctrl)
-{
- unsigned long mul;
- unsigned long mul_best_fit = 0;
- unsigned long div;
- unsigned long div_min;
- unsigned long div_max;
- unsigned long div_best_fit = 0;
- unsigned long base;
- unsigned long pll_in;
- unsigned long actual = 0;
- unsigned long rate_error;
- unsigned long rate_error_prev = ~0UL;
- u32 ctrl;
-
- /* Rate must be between 80 MHz and 200 Mhz. */
- if (rate < 80000000UL || rate > 200000000UL)
- return -EINVAL;
-
- ctrl = PM_BF(PLLOPT, 4);
- base = clk->parent->get_rate(clk->parent);
-
- /* PLL input frequency must be between 6 MHz and 32 MHz. */
- div_min = DIV_ROUND_UP(base, 32000000UL);
- div_max = base / 6000000UL;
-
- if (div_max < div_min)
- return -EINVAL;
-
- for (div = div_min; div <= div_max; div++) {
- pll_in = (base + div / 2) / div;
- mul = (rate + pll_in / 2) / pll_in;
-
- if (mul == 0)
- continue;
-
- actual = pll_in * mul;
- rate_error = abs(actual - rate);
-
- if (rate_error < rate_error_prev) {
- mul_best_fit = mul;
- div_best_fit = div;
- rate_error_prev = rate_error;
- }
-
- if (rate_error == 0)
- break;
- }
-
- if (div_best_fit == 0)
- return -EINVAL;
-
- ctrl |= PM_BF(PLLMUL, mul_best_fit - 1);
- ctrl |= PM_BF(PLLDIV, div_best_fit - 1);
- ctrl |= PM_BF(PLLCOUNT, 16);
-
- if (clk->parent == &osc1)
- ctrl |= PM_BIT(PLLOSC);
-
- *pll_ctrl = ctrl;
-
- return actual;
-}
-
-static unsigned long pll0_get_rate(struct clk *clk)
-{
- u32 control;
-
- control = pm_readl(PLL0);
-
- return pll_get_rate(clk, control);
-}
-
-static void pll1_mode(struct clk *clk, int enabled)
-{
- unsigned long timeout;
- u32 status;
- u32 ctrl;
-
- ctrl = pm_readl(PLL1);
-
- if (enabled) {
- if (!PM_BFEXT(PLLMUL, ctrl) && !PM_BFEXT(PLLDIV, ctrl)) {
- pr_debug("clk %s: failed to enable, rate not set\n",
- clk->name);
- return;
- }
-
- ctrl |= PM_BIT(PLLEN);
- pm_writel(PLL1, ctrl);
-
- /* Wait for PLL lock. */
- for (timeout = 10000; timeout; timeout--) {
- status = pm_readl(ISR);
- if (status & PM_BIT(LOCK1))
- break;
- udelay(10);
- }
-
- if (!(status & PM_BIT(LOCK1)))
- printk(KERN_ERR "clk %s: timeout waiting for lock\n",
- clk->name);
- } else {
- ctrl &= ~PM_BIT(PLLEN);
- pm_writel(PLL1, ctrl);
- }
-}
-
-static unsigned long pll1_get_rate(struct clk *clk)
-{
- u32 control;
-
- control = pm_readl(PLL1);
-
- return pll_get_rate(clk, control);
-}
-
-static long pll1_set_rate(struct clk *clk, unsigned long rate, int apply)
-{
- u32 ctrl = 0;
- unsigned long actual_rate;
-
- actual_rate = pll_set_rate(clk, rate, &ctrl);
-
- if (apply) {
- if (actual_rate != rate)
- return -EINVAL;
- if (clk->users > 0)
- return -EBUSY;
- pr_debug(KERN_INFO "clk %s: new rate %lu (actual rate %lu)\n",
- clk->name, rate, actual_rate);
- pm_writel(PLL1, ctrl);
- }
-
- return actual_rate;
-}
-
-static int pll1_set_parent(struct clk *clk, struct clk *parent)
-{
- u32 ctrl;
-
- if (clk->users > 0)
- return -EBUSY;
-
- ctrl = pm_readl(PLL1);
- WARN_ON(ctrl & PM_BIT(PLLEN));
-
- if (parent == &osc0)
- ctrl &= ~PM_BIT(PLLOSC);
- else if (parent == &osc1)
- ctrl |= PM_BIT(PLLOSC);
- else
- return -EINVAL;
-
- pm_writel(PLL1, ctrl);
- clk->parent = parent;
-
- return 0;
-}
-
-/*
- * The AT32AP7000 has five primary clock sources: One 32kHz
- * oscillator, two crystal oscillators and two PLLs.
- */
-static struct clk osc32k = {
- .name = "osc32k",
- .get_rate = osc_get_rate,
- .users = 1,
- .index = 0,
-};
-static struct clk osc0 = {
- .name = "osc0",
- .get_rate = osc_get_rate,
- .users = 1,
- .index = 1,
-};
-static struct clk osc1 = {
- .name = "osc1",
- .get_rate = osc_get_rate,
- .index = 2,
-};
-static struct clk pll0 = {
- .name = "pll0",
- .get_rate = pll0_get_rate,
- .parent = &osc0,
-};
-static struct clk pll1 = {
- .name = "pll1",
- .mode = pll1_mode,
- .get_rate = pll1_get_rate,
- .set_rate = pll1_set_rate,
- .set_parent = pll1_set_parent,
- .parent = &osc0,
-};
-
-/*
- * The main clock can be either osc0 or pll0. The boot loader may
- * have chosen one for us, so we don't really know which one until we
- * have a look at the SM.
- */
-static struct clk *main_clock;
-
-/*
- * Synchronous clocks are generated from the main clock. The clocks
- * must satisfy the constraint
- * fCPU >= fHSB >= fPB
- * i.e. each clock must not be faster than its parent.
- */
-static unsigned long bus_clk_get_rate(struct clk *clk, unsigned int shift)
-{
- return main_clock->get_rate(main_clock) >> shift;
-};
-
-static void cpu_clk_mode(struct clk *clk, int enabled)
-{
- unsigned long flags;
- u32 mask;
-
- spin_lock_irqsave(&pm_lock, flags);
- mask = pm_readl(CPU_MASK);
- if (enabled)
- mask |= 1 << clk->index;
- else
- mask &= ~(1 << clk->index);
- pm_writel(CPU_MASK, mask);
- spin_unlock_irqrestore(&pm_lock, flags);
-}
-
-static unsigned long cpu_clk_get_rate(struct clk *clk)
-{
- unsigned long cksel, shift = 0;
-
- cksel = pm_readl(CKSEL);
- if (cksel & PM_BIT(CPUDIV))
- shift = PM_BFEXT(CPUSEL, cksel) + 1;
-
- return bus_clk_get_rate(clk, shift);
-}
-
-static long cpu_clk_set_rate(struct clk *clk, unsigned long rate, int apply)
-{
- u32 control;
- unsigned long parent_rate, child_div, actual_rate, div;
-
- parent_rate = clk->parent->get_rate(clk->parent);
- control = pm_readl(CKSEL);
-
- if (control & PM_BIT(HSBDIV))
- child_div = 1 << (PM_BFEXT(HSBSEL, control) + 1);
- else
- child_div = 1;
-
- if (rate > 3 * (parent_rate / 4) || child_div == 1) {
- actual_rate = parent_rate;
- control &= ~PM_BIT(CPUDIV);
- } else {
- unsigned int cpusel;
- div = (parent_rate + rate / 2) / rate;
- if (div > child_div)
- div = child_div;
- cpusel = (div > 1) ? (fls(div) - 2) : 0;
- control = PM_BIT(CPUDIV) | PM_BFINS(CPUSEL, cpusel, control);
- actual_rate = parent_rate / (1 << (cpusel + 1));
- }
-
- pr_debug("clk %s: new rate %lu (actual rate %lu)\n",
- clk->name, rate, actual_rate);
-
- if (apply)
- pm_writel(CKSEL, control);
-
- return actual_rate;
-}
-
-static void hsb_clk_mode(struct clk *clk, int enabled)
-{
- unsigned long flags;
- u32 mask;
-
- spin_lock_irqsave(&pm_lock, flags);
- mask = pm_readl(HSB_MASK);
- if (enabled)
- mask |= 1 << clk->index;
- else
- mask &= ~(1 << clk->index);
- pm_writel(HSB_MASK, mask);
- spin_unlock_irqrestore(&pm_lock, flags);
-}
-
-static unsigned long hsb_clk_get_rate(struct clk *clk)
-{
- unsigned long cksel, shift = 0;
-
- cksel = pm_readl(CKSEL);
- if (cksel & PM_BIT(HSBDIV))
- shift = PM_BFEXT(HSBSEL, cksel) + 1;
-
- return bus_clk_get_rate(clk, shift);
-}
-
-void pba_clk_mode(struct clk *clk, int enabled)
-{
- unsigned long flags;
- u32 mask;
-
- spin_lock_irqsave(&pm_lock, flags);
- mask = pm_readl(PBA_MASK);
- if (enabled)
- mask |= 1 << clk->index;
- else
- mask &= ~(1 << clk->index);
- pm_writel(PBA_MASK, mask);
- spin_unlock_irqrestore(&pm_lock, flags);
-}
-
-unsigned long pba_clk_get_rate(struct clk *clk)
-{
- unsigned long cksel, shift = 0;
-
- cksel = pm_readl(CKSEL);
- if (cksel & PM_BIT(PBADIV))
- shift = PM_BFEXT(PBASEL, cksel) + 1;
-
- return bus_clk_get_rate(clk, shift);
-}
-
-static void pbb_clk_mode(struct clk *clk, int enabled)
-{
- unsigned long flags;
- u32 mask;
-
- spin_lock_irqsave(&pm_lock, flags);
- mask = pm_readl(PBB_MASK);
- if (enabled)
- mask |= 1 << clk->index;
- else
- mask &= ~(1 << clk->index);
- pm_writel(PBB_MASK, mask);
- spin_unlock_irqrestore(&pm_lock, flags);
-}
-
-static unsigned long pbb_clk_get_rate(struct clk *clk)
-{
- unsigned long cksel, shift = 0;
-
- cksel = pm_readl(CKSEL);
- if (cksel & PM_BIT(PBBDIV))
- shift = PM_BFEXT(PBBSEL, cksel) + 1;
-
- return bus_clk_get_rate(clk, shift);
-}
-
-static struct clk cpu_clk = {
- .name = "cpu",
- .get_rate = cpu_clk_get_rate,
- .set_rate = cpu_clk_set_rate,
- .users = 1,
-};
-static struct clk hsb_clk = {
- .name = "hsb",
- .parent = &cpu_clk,
- .get_rate = hsb_clk_get_rate,
-};
-static struct clk pba_clk = {
- .name = "pba",
- .parent = &hsb_clk,
- .mode = hsb_clk_mode,
- .get_rate = pba_clk_get_rate,
- .index = 1,
-};
-static struct clk pbb_clk = {
- .name = "pbb",
- .parent = &hsb_clk,
- .mode = hsb_clk_mode,
- .get_rate = pbb_clk_get_rate,
- .users = 1,
- .index = 2,
-};
-
-/* --------------------------------------------------------------------
- * Generic Clock operations
- * -------------------------------------------------------------------- */
-
-static void genclk_mode(struct clk *clk, int enabled)
-{
- u32 control;
-
- control = pm_readl(GCCTRL(clk->index));
- if (enabled)
- control |= PM_BIT(CEN);
- else
- control &= ~PM_BIT(CEN);
- pm_writel(GCCTRL(clk->index), control);
-}
-
-static unsigned long genclk_get_rate(struct clk *clk)
-{
- u32 control;
- unsigned long div = 1;
-
- control = pm_readl(GCCTRL(clk->index));
- if (control & PM_BIT(DIVEN))
- div = 2 * (PM_BFEXT(DIV, control) + 1);
-
- return clk->parent->get_rate(clk->parent) / div;
-}
-
-static long genclk_set_rate(struct clk *clk, unsigned long rate, int apply)
-{
- u32 control;
- unsigned long parent_rate, actual_rate, div;
-
- parent_rate = clk->parent->get_rate(clk->parent);
- control = pm_readl(GCCTRL(clk->index));
-
- if (rate > 3 * parent_rate / 4) {
- actual_rate = parent_rate;
- control &= ~PM_BIT(DIVEN);
- } else {
- div = (parent_rate + rate) / (2 * rate) - 1;
- control = PM_BFINS(DIV, div, control) | PM_BIT(DIVEN);
- actual_rate = parent_rate / (2 * (div + 1));
- }
-
- dev_dbg(clk->dev, "clk %s: new rate %lu (actual rate %lu)\n",
- clk->name, rate, actual_rate);
-
- if (apply)
- pm_writel(GCCTRL(clk->index), control);
-
- return actual_rate;
-}
-
-int genclk_set_parent(struct clk *clk, struct clk *parent)
-{
- u32 control;
-
- dev_dbg(clk->dev, "clk %s: new parent %s (was %s)\n",
- clk->name, parent->name, clk->parent->name);
-
- control = pm_readl(GCCTRL(clk->index));
-
- if (parent == &osc1 || parent == &pll1)
- control |= PM_BIT(OSCSEL);
- else if (parent == &osc0 || parent == &pll0)
- control &= ~PM_BIT(OSCSEL);
- else
- return -EINVAL;
-
- if (parent == &pll0 || parent == &pll1)
- control |= PM_BIT(PLLSEL);
- else
- control &= ~PM_BIT(PLLSEL);
-
- pm_writel(GCCTRL(clk->index), control);
- clk->parent = parent;
-
- return 0;
-}
-
-static void __init genclk_init_parent(struct clk *clk)
-{
- u32 control;
- struct clk *parent;
-
- BUG_ON(clk->index > 7);
-
- control = pm_readl(GCCTRL(clk->index));
- if (control & PM_BIT(OSCSEL))
- parent = (control & PM_BIT(PLLSEL)) ? &pll1 : &osc1;
- else
- parent = (control & PM_BIT(PLLSEL)) ? &pll0 : &osc0;
-
- clk->parent = parent;
-}
-
-static struct resource dw_dmac0_resource[] = {
- PBMEM(0xff200000),
- IRQ(2),
-};
-DEFINE_DEV(dw_dmac, 0);
-DEV_CLK(hclk, dw_dmac0, hsb, 10);
-
-/* --------------------------------------------------------------------
- * System peripherals
- * -------------------------------------------------------------------- */
-static struct resource at32_pm0_resource[] = {
- {
- .start = 0xfff00000,
- .end = 0xfff0007f,
- .flags = IORESOURCE_MEM,
- },
- IRQ(20),
-};
-
-static struct resource at32ap700x_rtc0_resource[] = {
- {
- .start = 0xfff00080,
- .end = 0xfff000af,
- .flags = IORESOURCE_MEM,
- },
- IRQ(21),
-};
-
-static struct resource at32_wdt0_resource[] = {
- {
- .start = 0xfff000b0,
- .end = 0xfff000cf,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct resource at32_eic0_resource[] = {
- {
- .start = 0xfff00100,
- .end = 0xfff0013f,
- .flags = IORESOURCE_MEM,
- },
- IRQ(19),
-};
-
-DEFINE_DEV(at32_pm, 0);
-DEFINE_DEV(at32ap700x_rtc, 0);
-DEFINE_DEV(at32_wdt, 0);
-DEFINE_DEV(at32_eic, 0);
-
-/*
- * Peripheral clock for PM, RTC, WDT and EIC. PM will ensure that this
- * is always running.
- */
-static struct clk at32_pm_pclk = {
- .name = "pclk",
- .dev = &at32_pm0_device.dev,
- .parent = &pbb_clk,
- .mode = pbb_clk_mode,
- .get_rate = pbb_clk_get_rate,
- .users = 1,
- .index = 0,
-};
-
-static struct resource intc0_resource[] = {
- PBMEM(0xfff00400),
-};
-struct platform_device at32_intc0_device = {
- .name = "intc",
- .id = 0,
- .resource = intc0_resource,
- .num_resources = ARRAY_SIZE(intc0_resource),
-};
-DEV_CLK(pclk, at32_intc0, pbb, 1);
-
-static struct clk ebi_clk = {
- .name = "ebi",
- .parent = &hsb_clk,
- .mode = hsb_clk_mode,
- .get_rate = hsb_clk_get_rate,
- .users = 1,
-};
-static struct clk hramc_clk = {
- .name = "hramc",
- .parent = &hsb_clk,
- .mode = hsb_clk_mode,
- .get_rate = hsb_clk_get_rate,
- .users = 1,
- .index = 3,
-};
-static struct clk sdramc_clk = {
- .name = "sdramc_clk",
- .parent = &pbb_clk,
- .mode = pbb_clk_mode,
- .get_rate = pbb_clk_get_rate,
- .users = 1,
- .index = 14,
-};
-
-static struct resource smc0_resource[] = {
- PBMEM(0xfff03400),
-};
-DEFINE_DEV(smc, 0);
-DEV_CLK(pclk, smc0, pbb, 13);
-DEV_CLK(mck, smc0, hsb, 0);
-
-static struct platform_device pdc_device = {
- .name = "pdc",
- .id = 0,
-};
-DEV_CLK(hclk, pdc, hsb, 4);
-DEV_CLK(pclk, pdc, pba, 16);
-
-static struct clk pico_clk = {
- .name = "pico",
- .parent = &cpu_clk,
- .mode = cpu_clk_mode,
- .get_rate = cpu_clk_get_rate,
- .users = 1,
-};
-
-/* --------------------------------------------------------------------
- * HMATRIX
- * -------------------------------------------------------------------- */
-
-struct clk at32_hmatrix_clk = {
- .name = "hmatrix_clk",
- .parent = &pbb_clk,
- .mode = pbb_clk_mode,
- .get_rate = pbb_clk_get_rate,
- .index = 2,
- .users = 1,
-};
-
-/*
- * Set bits in the HMATRIX Special Function Register (SFR) used by the
- * External Bus Interface (EBI). This can be used to enable special
- * features like CompactFlash support, NAND Flash support, etc. on
- * certain chipselects.
- */
-static inline void set_ebi_sfr_bits(u32 mask)
-{
- hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, mask);
-}
-
-/* --------------------------------------------------------------------
- * Timer/Counter (TC)
- * -------------------------------------------------------------------- */
-
-static struct resource at32_tcb0_resource[] = {
- PBMEM(0xfff00c00),
- IRQ(22),
-};
-static struct platform_device at32_tcb0_device = {
- .name = "atmel_tcb",
- .id = 0,
- .resource = at32_tcb0_resource,
- .num_resources = ARRAY_SIZE(at32_tcb0_resource),
-};
-DEV_CLK(t0_clk, at32_tcb0, pbb, 3);
-
-static struct resource at32_tcb1_resource[] = {
- PBMEM(0xfff01000),
- IRQ(23),
-};
-static struct platform_device at32_tcb1_device = {
- .name = "atmel_tcb",
- .id = 1,
- .resource = at32_tcb1_resource,
- .num_resources = ARRAY_SIZE(at32_tcb1_resource),
-};
-DEV_CLK(t0_clk, at32_tcb1, pbb, 4);
-
-/* --------------------------------------------------------------------
- * PIO
- * -------------------------------------------------------------------- */
-
-static struct resource pio0_resource[] = {
- PBMEM(0xffe02800),
- IRQ(13),
-};
-DEFINE_DEV(pio, 0);
-DEV_CLK(mck, pio0, pba, 10);
-
-static struct resource pio1_resource[] = {
- PBMEM(0xffe02c00),
- IRQ(14),
-};
-DEFINE_DEV(pio, 1);
-DEV_CLK(mck, pio1, pba, 11);
-
-static struct resource pio2_resource[] = {
- PBMEM(0xffe03000),
- IRQ(15),
-};
-DEFINE_DEV(pio, 2);
-DEV_CLK(mck, pio2, pba, 12);
-
-static struct resource pio3_resource[] = {
- PBMEM(0xffe03400),
- IRQ(16),
-};
-DEFINE_DEV(pio, 3);
-DEV_CLK(mck, pio3, pba, 13);
-
-static struct resource pio4_resource[] = {
- PBMEM(0xffe03800),
- IRQ(17),
-};
-DEFINE_DEV(pio, 4);
-DEV_CLK(mck, pio4, pba, 14);
-
-static int __init system_device_init(void)
-{
- platform_device_register(&at32_pm0_device);
- platform_device_register(&at32_intc0_device);
- platform_device_register(&at32ap700x_rtc0_device);
- platform_device_register(&at32_wdt0_device);
- platform_device_register(&at32_eic0_device);
- platform_device_register(&smc0_device);
- platform_device_register(&pdc_device);
- platform_device_register(&dw_dmac0_device);
-
- platform_device_register(&at32_tcb0_device);
- platform_device_register(&at32_tcb1_device);
-
- platform_device_register(&pio0_device);
- platform_device_register(&pio1_device);
- platform_device_register(&pio2_device);
- platform_device_register(&pio3_device);
- platform_device_register(&pio4_device);
-
- return 0;
-}
-core_initcall(system_device_init);
-
-/* --------------------------------------------------------------------
- * PSIF
- * -------------------------------------------------------------------- */
-static struct resource atmel_psif0_resource[] __initdata = {
- {
- .start = 0xffe03c00,
- .end = 0xffe03cff,
- .flags = IORESOURCE_MEM,
- },
- IRQ(18),
-};
-static struct clk atmel_psif0_pclk = {
- .name = "pclk",
- .parent = &pba_clk,
- .mode = pba_clk_mode,
- .get_rate = pba_clk_get_rate,
- .index = 15,
-};
-
-static struct resource atmel_psif1_resource[] __initdata = {
- {
- .start = 0xffe03d00,
- .end = 0xffe03dff,
- .flags = IORESOURCE_MEM,
- },
- IRQ(18),
-};
-static struct clk atmel_psif1_pclk = {
- .name = "pclk",
- .parent = &pba_clk,
- .mode = pba_clk_mode,
- .get_rate = pba_clk_get_rate,
- .index = 15,
-};
-
-struct platform_device *__init at32_add_device_psif(unsigned int id)
-{
- struct platform_device *pdev;
- u32 pin_mask;
-
- if (!(id == 0 || id == 1))
- return NULL;
-
- pdev = platform_device_alloc("atmel_psif", id);
- if (!pdev)
- return NULL;
-
- switch (id) {
- case 0:
- pin_mask = (1 << 8) | (1 << 9); /* CLOCK & DATA */
-
- if (platform_device_add_resources(pdev, atmel_psif0_resource,
- ARRAY_SIZE(atmel_psif0_resource)))
- goto err_add_resources;
- atmel_psif0_pclk.dev = &pdev->dev;
- select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
- break;
- case 1:
- pin_mask = (1 << 11) | (1 << 12); /* CLOCK & DATA */
-
- if (platform_device_add_resources(pdev, atmel_psif1_resource,
- ARRAY_SIZE(atmel_psif1_resource)))
- goto err_add_resources;
- atmel_psif1_pclk.dev = &pdev->dev;
- select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
- break;
- default:
- return NULL;
- }
-
- platform_device_add(pdev);
- return pdev;
-
-err_add_resources:
- platform_device_put(pdev);
- return NULL;
-}
-
-/* --------------------------------------------------------------------
- * USART
- * -------------------------------------------------------------------- */
-
-static struct atmel_uart_data atmel_usart0_data = {
- .use_dma_tx = 1,
- .use_dma_rx = 1,
-};
-static struct resource atmel_usart0_resource[] = {
- PBMEM(0xffe00c00),
- IRQ(6),
-};
-DEFINE_DEV_DATA(atmel_usart, 0);
-DEV_CLK(usart, atmel_usart0, pba, 3);
-
-static struct atmel_uart_data atmel_usart1_data = {
- .use_dma_tx = 1,
- .use_dma_rx = 1,
-};
-static struct resource atmel_usart1_resource[] = {
- PBMEM(0xffe01000),
- IRQ(7),
-};
-DEFINE_DEV_DATA(atmel_usart, 1);
-DEV_CLK(usart, atmel_usart1, pba, 4);
-
-static struct atmel_uart_data atmel_usart2_data = {
- .use_dma_tx = 1,
- .use_dma_rx = 1,
-};
-static struct resource atmel_usart2_resource[] = {
- PBMEM(0xffe01400),
- IRQ(8),
-};
-DEFINE_DEV_DATA(atmel_usart, 2);
-DEV_CLK(usart, atmel_usart2, pba, 5);
-
-static struct atmel_uart_data atmel_usart3_data = {
- .use_dma_tx = 1,
- .use_dma_rx = 1,
-};
-static struct resource atmel_usart3_resource[] = {
- PBMEM(0xffe01800),
- IRQ(9),
-};
-DEFINE_DEV_DATA(atmel_usart, 3);
-DEV_CLK(usart, atmel_usart3, pba, 6);
-
-static inline void configure_usart0_pins(int flags)
-{
- u32 pin_mask = (1 << 8) | (1 << 9); /* RXD & TXD */
- if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 6);
- if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 7);
- if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 10);
-
- select_peripheral(PIOA, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
-}
-
-static inline void configure_usart1_pins(int flags)
-{
- u32 pin_mask = (1 << 17) | (1 << 18); /* RXD & TXD */
- if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 19);
- if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 20);
- if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 16);
-
- select_peripheral(PIOA, pin_mask, PERIPH_A, AT32_GPIOF_PULLUP);
-}
-
-static inline void configure_usart2_pins(int flags)
-{
- u32 pin_mask = (1 << 26) | (1 << 27); /* RXD & TXD */
- if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 30);
- if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 29);
- if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 28);
-
- select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
-}
-
-static inline void configure_usart3_pins(int flags)
-{
- u32 pin_mask = (1 << 18) | (1 << 17); /* RXD & TXD */
- if (flags & ATMEL_USART_RTS) pin_mask |= (1 << 16);
- if (flags & ATMEL_USART_CTS) pin_mask |= (1 << 15);
- if (flags & ATMEL_USART_CLK) pin_mask |= (1 << 19);
-
- select_peripheral(PIOB, pin_mask, PERIPH_B, AT32_GPIOF_PULLUP);
-}
-
-static struct platform_device *__initdata at32_usarts[4];
-
-void __init at32_map_usart(unsigned int hw_id, unsigned int line, int flags)
-{
- struct platform_device *pdev;
- struct atmel_uart_data *pdata;
-
- switch (hw_id) {
- case 0:
- pdev = &atmel_usart0_device;
- configure_usart0_pins(flags);
- break;
- case 1:
- pdev = &atmel_usart1_device;
- configure_usart1_pins(flags);
- break;
- case 2:
- pdev = &atmel_usart2_device;
- configure_usart2_pins(flags);
- break;
- case 3:
- pdev = &atmel_usart3_device;
- configure_usart3_pins(flags);
- break;
- default:
- return;
- }
-
- if (PXSEG(pdev->resource[0].start) == P4SEG) {
- /* Addresses in the P4 segment are permanently mapped 1:1 */
- struct atmel_uart_data *data = pdev->dev.platform_data;
- data->regs = (void __iomem *)pdev->resource[0].start;
- }
-
- pdev->id = line;
- pdata = pdev->dev.platform_data;
- pdata->num = line;
- at32_usarts[line] = pdev;
-}
-
-struct platform_device *__init at32_add_device_usart(unsigned int id)
-{
- platform_device_register(at32_usarts[id]);
- return at32_usarts[id];
-}
-
-void __init at32_setup_serial_console(unsigned int usart_id)
-{
-#ifdef CONFIG_SERIAL_ATMEL
- atmel_default_console_device = at32_usarts[usart_id];
-#endif
-}
-
-/* --------------------------------------------------------------------
- * Ethernet
- * -------------------------------------------------------------------- */
-
-#ifdef CONFIG_CPU_AT32AP7000
-static struct macb_platform_data macb0_data;
-static struct resource macb0_resource[] = {
- PBMEM(0xfff01800),
- IRQ(25),
-};
-DEFINE_DEV_DATA(macb, 0);
-DEV_CLK(hclk, macb0, hsb, 8);
-DEV_CLK(pclk, macb0, pbb, 6);
-
-static struct macb_platform_data macb1_data;
-static struct resource macb1_resource[] = {
- PBMEM(0xfff01c00),
- IRQ(26),
-};
-DEFINE_DEV_DATA(macb, 1);
-DEV_CLK(hclk, macb1, hsb, 9);
-DEV_CLK(pclk, macb1, pbb, 7);
-
-struct platform_device *__init
-at32_add_device_eth(unsigned int id, struct macb_platform_data *data)
-{
- struct platform_device *pdev;
- u32 pin_mask;
-
- switch (id) {
- case 0:
- pdev = &macb0_device;
-
- pin_mask = (1 << 3); /* TXD0 */
- pin_mask |= (1 << 4); /* TXD1 */
- pin_mask |= (1 << 7); /* TXEN */
- pin_mask |= (1 << 8); /* TXCK */
- pin_mask |= (1 << 9); /* RXD0 */
- pin_mask |= (1 << 10); /* RXD1 */
- pin_mask |= (1 << 13); /* RXER */
- pin_mask |= (1 << 15); /* RXDV */
- pin_mask |= (1 << 16); /* MDC */
- pin_mask |= (1 << 17); /* MDIO */
-
- if (!data->is_rmii) {
- pin_mask |= (1 << 0); /* COL */
- pin_mask |= (1 << 1); /* CRS */
- pin_mask |= (1 << 2); /* TXER */
- pin_mask |= (1 << 5); /* TXD2 */
- pin_mask |= (1 << 6); /* TXD3 */
- pin_mask |= (1 << 11); /* RXD2 */
- pin_mask |= (1 << 12); /* RXD3 */
- pin_mask |= (1 << 14); /* RXCK */
-#ifndef CONFIG_BOARD_MIMC200
- pin_mask |= (1 << 18); /* SPD */
-#endif
- }
-
- select_peripheral(PIOC, pin_mask, PERIPH_A, 0);
-
- break;
-
- case 1:
- pdev = &macb1_device;
-
- pin_mask = (1 << 13); /* TXD0 */
- pin_mask |= (1 << 14); /* TXD1 */
- pin_mask |= (1 << 11); /* TXEN */
- pin_mask |= (1 << 12); /* TXCK */
- pin_mask |= (1 << 10); /* RXD0 */
- pin_mask |= (1 << 6); /* RXD1 */
- pin_mask |= (1 << 5); /* RXER */
- pin_mask |= (1 << 4); /* RXDV */
- pin_mask |= (1 << 3); /* MDC */
- pin_mask |= (1 << 2); /* MDIO */
-
-#ifndef CONFIG_BOARD_MIMC200
- if (!data->is_rmii)
- pin_mask |= (1 << 15); /* SPD */
-#endif
-
- select_peripheral(PIOD, pin_mask, PERIPH_B, 0);
-
- if (!data->is_rmii) {
- pin_mask = (1 << 19); /* COL */
- pin_mask |= (1 << 23); /* CRS */
- pin_mask |= (1 << 26); /* TXER */
- pin_mask |= (1 << 27); /* TXD2 */
- pin_mask |= (1 << 28); /* TXD3 */
- pin_mask |= (1 << 29); /* RXD2 */
- pin_mask |= (1 << 30); /* RXD3 */
- pin_mask |= (1 << 24); /* RXCK */
-
- select_peripheral(PIOC, pin_mask, PERIPH_B, 0);
- }
- break;
-
- default:
- return NULL;
- }
-
- memcpy(pdev->dev.platform_data, data, sizeof(struct macb_platform_data));
- platform_device_register(pdev);
-
- return pdev;
-}
-#endif
-
-/* --------------------------------------------------------------------
- * SPI
- * -------------------------------------------------------------------- */
-static struct resource atmel_spi0_resource[] = {
- PBMEM(0xffe00000),
- IRQ(3),
-};
-DEFINE_DEV(atmel_spi, 0);
-DEV_CLK(spi_clk, atmel_spi0, pba, 0);
-
-static struct resource atmel_spi1_resource[] = {
- PBMEM(0xffe00400),
- IRQ(4),
-};
-DEFINE_DEV(atmel_spi, 1);
-DEV_CLK(spi_clk, atmel_spi1, pba, 1);
-
-void __init
-at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n)
-{
- /*
- * Manage the chipselects as GPIOs, normally using the same pins
- * the SPI controller expects; but boards can use other pins.
- */
- static u8 __initdata spi_pins[][4] = {
- { GPIO_PIN_PA(3), GPIO_PIN_PA(4),
- GPIO_PIN_PA(5), GPIO_PIN_PA(20) },
- { GPIO_PIN_PB(2), GPIO_PIN_PB(3),
- GPIO_PIN_PB(4), GPIO_PIN_PA(27) },
- };
- unsigned int pin, mode;
-
- /* There are only 2 SPI controllers */
- if (bus_num > 1)
- return;
-
- for (; n; n--, b++) {
- b->bus_num = bus_num;
- if (b->chip_select >= 4)
- continue;
- pin = (unsigned)b->controller_data;
- if (!pin) {
- pin = spi_pins[bus_num][b->chip_select];
- b->controller_data = (void *)pin;
- }
- mode = AT32_GPIOF_OUTPUT;
- if (!(b->mode & SPI_CS_HIGH))
- mode |= AT32_GPIOF_HIGH;
- at32_select_gpio(pin, mode);
- }
-}
-
-struct platform_device *__init
-at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n)
-{
- struct platform_device *pdev;
- u32 pin_mask;
-
- switch (id) {
- case 0:
- pdev = &atmel_spi0_device;
- pin_mask = (1 << 1) | (1 << 2); /* MOSI & SCK */
-
- /* pullup MISO so a level is always defined */
- select_peripheral(PIOA, (1 << 0), PERIPH_A, AT32_GPIOF_PULLUP);
- select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
-
- at32_spi_setup_slaves(0, b, n);
- break;
-
- case 1:
- pdev = &atmel_spi1_device;
- pin_mask = (1 << 1) | (1 << 5); /* MOSI */
-
- /* pullup MISO so a level is always defined */
- select_peripheral(PIOB, (1 << 0), PERIPH_B, AT32_GPIOF_PULLUP);
- select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
-
- at32_spi_setup_slaves(1, b, n);
- break;
-
- default:
- return NULL;
- }
-
- spi_register_board_info(b, n);
- platform_device_register(pdev);
- return pdev;
-}
-
-/* --------------------------------------------------------------------
- * TWI
- * -------------------------------------------------------------------- */
-static struct resource atmel_twi0_resource[] __initdata = {
- PBMEM(0xffe00800),
- IRQ(5),
-};
-static struct clk atmel_twi0_pclk = {
- .name = "twi_pclk",
- .parent = &pba_clk,
- .mode = pba_clk_mode,
- .get_rate = pba_clk_get_rate,
- .index = 2,
-};
-
-struct platform_device *__init at32_add_device_twi(unsigned int id,
- struct i2c_board_info *b,
- unsigned int n)
-{
- struct platform_device *pdev;
- u32 pin_mask;
-
- if (id != 0)
- return NULL;
-
- pdev = platform_device_alloc("atmel_twi", id);
- if (!pdev)
- return NULL;
-
- if (platform_device_add_resources(pdev, atmel_twi0_resource,
- ARRAY_SIZE(atmel_twi0_resource)))
- goto err_add_resources;
-
- pin_mask = (1 << 6) | (1 << 7); /* SDA & SDL */
-
- select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
-
- atmel_twi0_pclk.dev = &pdev->dev;
-
- if (b)
- i2c_register_board_info(id, b, n);
-
- platform_device_add(pdev);
- return pdev;
-
-err_add_resources:
- platform_device_put(pdev);
- return NULL;
-}
-
-/* --------------------------------------------------------------------
- * MMC
- * -------------------------------------------------------------------- */
-static struct resource atmel_mci0_resource[] __initdata = {
- PBMEM(0xfff02400),
- IRQ(28),
-};
-static struct clk atmel_mci0_pclk = {
- .name = "mci_clk",
- .parent = &pbb_clk,
- .mode = pbb_clk_mode,
- .get_rate = pbb_clk_get_rate,
- .index = 9,
-};
-
-static bool at32_mci_dma_filter(struct dma_chan *chan, void *pdata)
-{
- struct dw_dma_slave *sl = pdata;
-
- if (!sl)
- return false;
-
- if (sl->dma_dev == chan->device->dev) {
- chan->private = sl;
- return true;
- }
-
- return false;
-}
-
-struct platform_device *__init
-at32_add_device_mci(unsigned int id, struct mci_platform_data *data)
-{
- struct platform_device *pdev;
- struct dw_dma_slave *slave;
- u32 pioa_mask;
- u32 piob_mask;
-
- if (id != 0 || !data)
- return NULL;
-
- /* Must have at least one usable slot */
- if (!data->slot[0].bus_width && !data->slot[1].bus_width)
- return NULL;
-
- pdev = platform_device_alloc("atmel_mci", id);
- if (!pdev)
- goto fail;
-
- if (platform_device_add_resources(pdev, atmel_mci0_resource,
- ARRAY_SIZE(atmel_mci0_resource)))
- goto fail;
-
- slave = kzalloc(sizeof(*slave), GFP_KERNEL);
- if (!slave)
- goto fail;
-
- slave->dma_dev = &dw_dmac0_device.dev;
- slave->src_id = 0;
- slave->dst_id = 1;
- slave->m_master = 1;
- slave->p_master = 0;
-
- data->dma_slave = slave;
- data->dma_filter = at32_mci_dma_filter;
-
- if (platform_device_add_data(pdev, data,
- sizeof(struct mci_platform_data)))
- goto fail_free;
-
- /* CLK line is common to both slots */
- pioa_mask = 1 << 10;
-
- switch (data->slot[0].bus_width) {
- case 4:
- pioa_mask |= 1 << 13; /* DATA1 */
- pioa_mask |= 1 << 14; /* DATA2 */
- pioa_mask |= 1 << 15; /* DATA3 */
- /* fall through */
- case 1:
- pioa_mask |= 1 << 11; /* CMD */
- pioa_mask |= 1 << 12; /* DATA0 */
-
- if (gpio_is_valid(data->slot[0].detect_pin))
- at32_select_gpio(data->slot[0].detect_pin, 0);
- if (gpio_is_valid(data->slot[0].wp_pin))
- at32_select_gpio(data->slot[0].wp_pin, 0);
- break;
- case 0:
- /* Slot is unused */
- break;
- default:
- goto fail_free;
- }
-
- select_peripheral(PIOA, pioa_mask, PERIPH_A, 0);
- piob_mask = 0;
-
- switch (data->slot[1].bus_width) {
- case 4:
- piob_mask |= 1 << 8; /* DATA1 */
- piob_mask |= 1 << 9; /* DATA2 */
- piob_mask |= 1 << 10; /* DATA3 */
- /* fall through */
- case 1:
- piob_mask |= 1 << 6; /* CMD */
- piob_mask |= 1 << 7; /* DATA0 */
- select_peripheral(PIOB, piob_mask, PERIPH_B, 0);
-
- if (gpio_is_valid(data->slot[1].detect_pin))
- at32_select_gpio(data->slot[1].detect_pin, 0);
- if (gpio_is_valid(data->slot[1].wp_pin))
- at32_select_gpio(data->slot[1].wp_pin, 0);
- break;
- case 0:
- /* Slot is unused */
- break;
- default:
- if (!data->slot[0].bus_width)
- goto fail_free;
-
- data->slot[1].bus_width = 0;
- break;
- }
-
- atmel_mci0_pclk.dev = &pdev->dev;
-
- platform_device_add(pdev);
- return pdev;
-
-fail_free:
- kfree(slave);
-fail:
- data->dma_slave = NULL;
- platform_device_put(pdev);
- return NULL;
-}
-
-/* --------------------------------------------------------------------
- * LCDC
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
-static struct atmel_lcdfb_pdata atmel_lcdfb0_data;
-static struct resource atmel_lcdfb0_resource[] = {
- {
- .start = 0xff000000,
- .end = 0xff000fff,
- .flags = IORESOURCE_MEM,
- },
- IRQ(1),
- {
- /* Placeholder for pre-allocated fb memory */
- .start = 0x00000000,
- .end = 0x00000000,
- .flags = 0,
- },
-};
-DEFINE_DEV_DATA(atmel_lcdfb, 0);
-DEV_CLK(hclk, atmel_lcdfb0, hsb, 7);
-static struct clk atmel_lcdfb0_pixclk = {
- .name = "lcdc_clk",
- .dev = &atmel_lcdfb0_device.dev,
- .mode = genclk_mode,
- .get_rate = genclk_get_rate,
- .set_rate = genclk_set_rate,
- .set_parent = genclk_set_parent,
- .index = 7,
-};
-
-struct platform_device *__init
-at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_pdata *data,
- unsigned long fbmem_start, unsigned long fbmem_len,
- u64 pin_mask)
-{
- struct platform_device *pdev;
- struct atmel_lcdfb_pdata *info;
- struct fb_monspecs *monspecs;
- struct fb_videomode *modedb;
- unsigned int modedb_size;
- u32 portc_mask, portd_mask, porte_mask;
-
- /*
- * Do a deep copy of the fb data, monspecs and modedb. Make
- * sure all allocations are done before setting up the
- * portmux.
- */
- monspecs = kmemdup(data->default_monspecs,
- sizeof(struct fb_monspecs), GFP_KERNEL);
- if (!monspecs)
- return NULL;
-
- modedb_size = sizeof(struct fb_videomode) * monspecs->modedb_len;
- modedb = kmemdup(monspecs->modedb, modedb_size, GFP_KERNEL);
- if (!modedb)
- goto err_dup_modedb;
- monspecs->modedb = modedb;
-
- switch (id) {
- case 0:
- pdev = &atmel_lcdfb0_device;
-
- if (pin_mask == 0ULL)
- /* Default to "full" lcdc control signals and 24bit */
- pin_mask = ATMEL_LCDC_PRI_24BIT | ATMEL_LCDC_PRI_CONTROL;
-
- /* LCDC on port C */
- portc_mask = pin_mask & 0xfff80000;
- select_peripheral(PIOC, portc_mask, PERIPH_A, 0);
-
- /* LCDC on port D */
- portd_mask = pin_mask & 0x0003ffff;
- select_peripheral(PIOD, portd_mask, PERIPH_A, 0);
-
- /* LCDC on port E */
- porte_mask = (pin_mask >> 32) & 0x0007ffff;
- select_peripheral(PIOE, porte_mask, PERIPH_B, 0);
-
- clk_set_parent(&atmel_lcdfb0_pixclk, &pll0);
- clk_set_rate(&atmel_lcdfb0_pixclk, clk_get_rate(&pll0));
- break;
-
- default:
- goto err_invalid_id;
- }
-
- if (fbmem_len) {
- pdev->resource[2].start = fbmem_start;
- pdev->resource[2].end = fbmem_start + fbmem_len - 1;
- pdev->resource[2].flags = IORESOURCE_MEM;
- }
-
- info = pdev->dev.platform_data;
- memcpy(info, data, sizeof(struct atmel_lcdfb_pdata));
- info->default_monspecs = monspecs;
-
- pdev->name = "at32ap-lcdfb";
-
- platform_device_register(pdev);
- return pdev;
-
-err_invalid_id:
- kfree(modedb);
-err_dup_modedb:
- kfree(monspecs);
- return NULL;
-}
-#endif
-
-/* --------------------------------------------------------------------
- * PWM
- * -------------------------------------------------------------------- */
-static struct resource atmel_pwm0_resource[] __initdata = {
- PBMEM(0xfff01400),
- IRQ(24),
-};
-static struct clk atmel_pwm0_mck = {
- .name = "at91sam9rl-pwm",
- .parent = &pbb_clk,
- .mode = pbb_clk_mode,
- .get_rate = pbb_clk_get_rate,
- .index = 5,
-};
-
-struct platform_device *__init at32_add_device_pwm(u32 mask)
-{
- struct platform_device *pdev;
- u32 pin_mask;
-
- if (!mask)
- return NULL;
-
- pdev = platform_device_alloc("at91sam9rl-pwm", 0);
- if (!pdev)
- return NULL;
-
- if (platform_device_add_resources(pdev, atmel_pwm0_resource,
- ARRAY_SIZE(atmel_pwm0_resource)))
- goto out_free_pdev;
-
- pin_mask = 0;
- if (mask & (1 << 0))
- pin_mask |= (1 << 28);
- if (mask & (1 << 1))
- pin_mask |= (1 << 29);
- if (pin_mask > 0)
- select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
-
- pin_mask = 0;
- if (mask & (1 << 2))
- pin_mask |= (1 << 21);
- if (mask & (1 << 3))
- pin_mask |= (1 << 22);
- if (pin_mask > 0)
- select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
-
- atmel_pwm0_mck.dev = &pdev->dev;
-
- platform_device_add(pdev);
-
- return pdev;
-
-out_free_pdev:
- platform_device_put(pdev);
- return NULL;
-}
-
-/* --------------------------------------------------------------------
- * SSC
- * -------------------------------------------------------------------- */
-static struct resource ssc0_resource[] = {
- PBMEM(0xffe01c00),
- IRQ(10),
-};
-DEFINE_DEV(ssc, 0);
-DEV_CLK(pclk, ssc0, pba, 7);
-
-static struct resource ssc1_resource[] = {
- PBMEM(0xffe02000),
- IRQ(11),
-};
-DEFINE_DEV(ssc, 1);
-DEV_CLK(pclk, ssc1, pba, 8);
-
-static struct resource ssc2_resource[] = {
- PBMEM(0xffe02400),
- IRQ(12),
-};
-DEFINE_DEV(ssc, 2);
-DEV_CLK(pclk, ssc2, pba, 9);
-
-struct platform_device *__init
-at32_add_device_ssc(unsigned int id, unsigned int flags)
-{
- struct platform_device *pdev;
- u32 pin_mask = 0;
-
- switch (id) {
- case 0:
- pdev = &ssc0_device;
- if (flags & ATMEL_SSC_RF)
- pin_mask |= (1 << 21); /* RF */
- if (flags & ATMEL_SSC_RK)
- pin_mask |= (1 << 22); /* RK */
- if (flags & ATMEL_SSC_TK)
- pin_mask |= (1 << 23); /* TK */
- if (flags & ATMEL_SSC_TF)
- pin_mask |= (1 << 24); /* TF */
- if (flags & ATMEL_SSC_TD)
- pin_mask |= (1 << 25); /* TD */
- if (flags & ATMEL_SSC_RD)
- pin_mask |= (1 << 26); /* RD */
-
- if (pin_mask > 0)
- select_peripheral(PIOA, pin_mask, PERIPH_A, 0);
-
- break;
- case 1:
- pdev = &ssc1_device;
- if (flags & ATMEL_SSC_RF)
- pin_mask |= (1 << 0); /* RF */
- if (flags & ATMEL_SSC_RK)
- pin_mask |= (1 << 1); /* RK */
- if (flags & ATMEL_SSC_TK)
- pin_mask |= (1 << 2); /* TK */
- if (flags & ATMEL_SSC_TF)
- pin_mask |= (1 << 3); /* TF */
- if (flags & ATMEL_SSC_TD)
- pin_mask |= (1 << 4); /* TD */
- if (flags & ATMEL_SSC_RD)
- pin_mask |= (1 << 5); /* RD */
-
- if (pin_mask > 0)
- select_peripheral(PIOA, pin_mask, PERIPH_B, 0);
-
- break;
- case 2:
- pdev = &ssc2_device;
- if (flags & ATMEL_SSC_TD)
- pin_mask |= (1 << 13); /* TD */
- if (flags & ATMEL_SSC_RD)
- pin_mask |= (1 << 14); /* RD */
- if (flags & ATMEL_SSC_TK)
- pin_mask |= (1 << 15); /* TK */
- if (flags & ATMEL_SSC_TF)
- pin_mask |= (1 << 16); /* TF */
- if (flags & ATMEL_SSC_RF)
- pin_mask |= (1 << 17); /* RF */
- if (flags & ATMEL_SSC_RK)
- pin_mask |= (1 << 18); /* RK */
-
- if (pin_mask > 0)
- select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
-
- break;
- default:
- return NULL;
- }
-
- platform_device_register(pdev);
- return pdev;
-}
-
-/* --------------------------------------------------------------------
- * USB Device Controller
- * -------------------------------------------------------------------- */
-static struct resource usba0_resource[] __initdata = {
- {
- .start = 0xff300000,
- .end = 0xff3fffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0xfff03000,
- .end = 0xfff033ff,
- .flags = IORESOURCE_MEM,
- },
- IRQ(31),
-};
-static struct clk usba0_pclk = {
- .name = "pclk",
- .parent = &pbb_clk,
- .mode = pbb_clk_mode,
- .get_rate = pbb_clk_get_rate,
- .index = 12,
-};
-static struct clk usba0_hclk = {
- .name = "hclk",
- .parent = &hsb_clk,
- .mode = hsb_clk_mode,
- .get_rate = hsb_clk_get_rate,
- .index = 6,
-};
-
-#define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
- [idx] = { \
- .name = nam, \
- .index = idx, \
- .fifo_size = maxpkt, \
- .nr_banks = maxbk, \
- .can_dma = dma, \
- .can_isoc = isoc, \
- }
-
-static struct usba_ep_data at32_usba_ep[] __initdata = {
- EP("ep0", 0, 64, 1, 0, 0),
- EP("ep1", 1, 512, 2, 1, 1),
- EP("ep2", 2, 512, 2, 1, 1),
- EP("ep3-int", 3, 64, 3, 1, 0),
- EP("ep4-int", 4, 64, 3, 1, 0),
- EP("ep5", 5, 1024, 3, 1, 1),
- EP("ep6", 6, 1024, 3, 1, 1),
-};
-
-#undef EP
-
-struct platform_device *__init
-at32_add_device_usba(unsigned int id, struct usba_platform_data *data)
-{
- /*
- * pdata doesn't have room for any endpoints, so we need to
- * append room for the ones we need right after it.
- */
- struct {
- struct usba_platform_data pdata;
- struct usba_ep_data ep[7];
- } usba_data;
- struct platform_device *pdev;
-
- if (id != 0)
- return NULL;
-
- pdev = platform_device_alloc("atmel_usba_udc", 0);
- if (!pdev)
- return NULL;
-
- if (platform_device_add_resources(pdev, usba0_resource,
- ARRAY_SIZE(usba0_resource)))
- goto out_free_pdev;
-
- if (data) {
- usba_data.pdata.vbus_pin = data->vbus_pin;
- usba_data.pdata.vbus_pin_inverted = data->vbus_pin_inverted;
- } else {
- usba_data.pdata.vbus_pin = -EINVAL;
- usba_data.pdata.vbus_pin_inverted = -EINVAL;
- }
-
- data = &usba_data.pdata;
- data->num_ep = ARRAY_SIZE(at32_usba_ep);
- memcpy(data->ep, at32_usba_ep, sizeof(at32_usba_ep));
-
- if (platform_device_add_data(pdev, data, sizeof(usba_data)))
- goto out_free_pdev;
-
- if (gpio_is_valid(data->vbus_pin))
- at32_select_gpio(data->vbus_pin, 0);
-
- usba0_pclk.dev = &pdev->dev;
- usba0_hclk.dev = &pdev->dev;
-
- platform_device_add(pdev);
-
- return pdev;
-
-out_free_pdev:
- platform_device_put(pdev);
- return NULL;
-}
-
-/* --------------------------------------------------------------------
- * IDE / CompactFlash
- * -------------------------------------------------------------------- */
-#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7001)
-static struct resource at32_smc_cs4_resource[] __initdata = {
- {
- .start = 0x04000000,
- .end = 0x07ffffff,
- .flags = IORESOURCE_MEM,
- },
- IRQ(~0UL), /* Magic IRQ will be overridden */
-};
-static struct resource at32_smc_cs5_resource[] __initdata = {
- {
- .start = 0x20000000,
- .end = 0x23ffffff,
- .flags = IORESOURCE_MEM,
- },
- IRQ(~0UL), /* Magic IRQ will be overridden */
-};
-
-static int __init at32_init_ide_or_cf(struct platform_device *pdev,
- unsigned int cs, unsigned int extint)
-{
- static unsigned int extint_pin_map[4] __initdata = {
- (1 << 25),
- (1 << 26),
- (1 << 27),
- (1 << 28),
- };
- static bool common_pins_initialized __initdata = false;
- unsigned int extint_pin;
- int ret;
- u32 pin_mask;
-
- if (extint >= ARRAY_SIZE(extint_pin_map))
- return -EINVAL;
- extint_pin = extint_pin_map[extint];
-
- switch (cs) {
- case 4:
- ret = platform_device_add_resources(pdev,
- at32_smc_cs4_resource,
- ARRAY_SIZE(at32_smc_cs4_resource));
- if (ret)
- return ret;
-
- /* NCS4 -> OE_N */
- select_peripheral(PIOE, (1 << 21), PERIPH_A, 0);
- hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF0_ENABLE);
- break;
- case 5:
- ret = platform_device_add_resources(pdev,
- at32_smc_cs5_resource,
- ARRAY_SIZE(at32_smc_cs5_resource));
- if (ret)
- return ret;
-
- /* NCS5 -> OE_N */
- select_peripheral(PIOE, (1 << 22), PERIPH_A, 0);
- hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_CF1_ENABLE);
- break;
- default:
- return -EINVAL;
- }
-
- if (!common_pins_initialized) {
- pin_mask = (1 << 19); /* CFCE1 -> CS0_N */
- pin_mask |= (1 << 20); /* CFCE2 -> CS1_N */
- pin_mask |= (1 << 23); /* CFRNW -> DIR */
- pin_mask |= (1 << 24); /* NWAIT <- IORDY */
-
- select_peripheral(PIOE, pin_mask, PERIPH_A, 0);
-
- common_pins_initialized = true;
- }
-
- select_peripheral(PIOB, extint_pin, PERIPH_A, AT32_GPIOF_DEGLITCH);
-
- pdev->resource[1].start = EIM_IRQ_BASE + extint;
- pdev->resource[1].end = pdev->resource[1].start;
-
- return 0;
-}
-
-struct platform_device *__init
-at32_add_device_ide(unsigned int id, unsigned int extint,
- struct ide_platform_data *data)
-{
- struct platform_device *pdev;
-
- pdev = platform_device_alloc("at32_ide", id);
- if (!pdev)
- goto fail;
-
- if (platform_device_add_data(pdev, data,
- sizeof(struct ide_platform_data)))
- goto fail;
-
- if (at32_init_ide_or_cf(pdev, data->cs, extint))
- goto fail;
-
- platform_device_add(pdev);
- return pdev;
-
-fail:
- platform_device_put(pdev);
- return NULL;
-}
-
-struct platform_device *__init
-at32_add_device_cf(unsigned int id, unsigned int extint,
- struct cf_platform_data *data)
-{
- struct platform_device *pdev;
-
- pdev = platform_device_alloc("at32_cf", id);
- if (!pdev)
- goto fail;
-
- if (platform_device_add_data(pdev, data,
- sizeof(struct cf_platform_data)))
- goto fail;
-
- if (at32_init_ide_or_cf(pdev, data->cs, extint))
- goto fail;
-
- if (gpio_is_valid(data->detect_pin))
- at32_select_gpio(data->detect_pin, AT32_GPIOF_DEGLITCH);
- if (gpio_is_valid(data->reset_pin))
- at32_select_gpio(data->reset_pin, 0);
- if (gpio_is_valid(data->vcc_pin))
- at32_select_gpio(data->vcc_pin, 0);
- /* READY is used as extint, so we can't select it as gpio */
-
- platform_device_add(pdev);
- return pdev;
-
-fail:
- platform_device_put(pdev);
- return NULL;
-}
-#endif
-
-/* --------------------------------------------------------------------
- * NAND Flash / SmartMedia
- * -------------------------------------------------------------------- */
-static struct resource smc_cs3_resource[] __initdata = {
- {
- .start = 0x0c000000,
- .end = 0x0fffffff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = 0xfff03c00,
- .end = 0xfff03fff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device *__init
-at32_add_device_nand(unsigned int id, struct atmel_nand_data *data)
-{
- struct platform_device *pdev;
-
- if (id != 0 || !data)
- return NULL;
-
- pdev = platform_device_alloc("atmel_nand", id);
- if (!pdev)
- goto fail;
-
- if (platform_device_add_resources(pdev, smc_cs3_resource,
- ARRAY_SIZE(smc_cs3_resource)))
- goto fail;
-
- /* For at32ap7000, we use the reset workaround for nand driver */
- data->need_reset_workaround = true;
-
- if (platform_device_add_data(pdev, data,
- sizeof(struct atmel_nand_data)))
- goto fail;
-
- hmatrix_sfr_set_bits(HMATRIX_SLAVE_EBI, HMATRIX_EBI_NAND_ENABLE);
- if (data->enable_pin)
- at32_select_gpio(data->enable_pin,
- AT32_GPIOF_OUTPUT | AT32_GPIOF_HIGH);
- if (data->rdy_pin)
- at32_select_gpio(data->rdy_pin, 0);
- if (data->det_pin)
- at32_select_gpio(data->det_pin, 0);
-
- platform_device_add(pdev);
- return pdev;
-
-fail:
- platform_device_put(pdev);
- return NULL;
-}
-
-/* --------------------------------------------------------------------
- * AC97C
- * -------------------------------------------------------------------- */
-static struct resource atmel_ac97c0_resource[] __initdata = {
- PBMEM(0xfff02800),
- IRQ(29),
-};
-static struct clk atmel_ac97c0_pclk = {
- .name = "pclk",
- .parent = &pbb_clk,
- .mode = pbb_clk_mode,
- .get_rate = pbb_clk_get_rate,
- .index = 10,
-};
-
-struct platform_device *__init
-at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
- unsigned int flags)
-{
- struct platform_device *pdev;
- struct dw_dma_slave *rx_dws;
- struct dw_dma_slave *tx_dws;
- struct ac97c_platform_data _data;
- u32 pin_mask;
-
- if (id != 0)
- return NULL;
-
- pdev = platform_device_alloc("atmel_ac97c", id);
- if (!pdev)
- return NULL;
-
- if (platform_device_add_resources(pdev, atmel_ac97c0_resource,
- ARRAY_SIZE(atmel_ac97c0_resource)))
- goto out_free_resources;
-
- if (!data) {
- data = &_data;
- memset(data, 0, sizeof(struct ac97c_platform_data));
- data->reset_pin = -ENODEV;
- }
-
- rx_dws = &data->rx_dws;
- tx_dws = &data->tx_dws;
-
- /* Check if DMA slave interface for capture should be configured. */
- if (flags & AC97C_CAPTURE) {
- rx_dws->dma_dev = &dw_dmac0_device.dev;
- rx_dws->src_id = 3;
- rx_dws->m_master = 0;
- rx_dws->p_master = 1;
- }
-
- /* Check if DMA slave interface for playback should be configured. */
- if (flags & AC97C_PLAYBACK) {
- tx_dws->dma_dev = &dw_dmac0_device.dev;
- tx_dws->dst_id = 4;
- tx_dws->m_master = 0;
- tx_dws->p_master = 1;
- }
-
- if (platform_device_add_data(pdev, data,
- sizeof(struct ac97c_platform_data)))
- goto out_free_resources;
-
- /* SDO | SYNC | SCLK | SDI */
- pin_mask = (1 << 20) | (1 << 21) | (1 << 22) | (1 << 23);
-
- select_peripheral(PIOB, pin_mask, PERIPH_B, 0);
-
- if (gpio_is_valid(data->reset_pin))
- at32_select_gpio(data->reset_pin, AT32_GPIOF_OUTPUT
- | AT32_GPIOF_HIGH);
-
- atmel_ac97c0_pclk.dev = &pdev->dev;
-
- platform_device_add(pdev);
- return pdev;
-
-out_free_resources:
- platform_device_put(pdev);
- return NULL;
-}
-
-/* --------------------------------------------------------------------
- * ABDAC
- * -------------------------------------------------------------------- */
-static struct resource abdac0_resource[] __initdata = {
- PBMEM(0xfff02000),
- IRQ(27),
-};
-static struct clk abdac0_pclk = {
- .name = "pclk",
- .parent = &pbb_clk,
- .mode = pbb_clk_mode,
- .get_rate = pbb_clk_get_rate,
- .index = 8,
-};
-static struct clk abdac0_sample_clk = {
- .name = "sample_clk",
- .mode = genclk_mode,
- .get_rate = genclk_get_rate,
- .set_rate = genclk_set_rate,
- .set_parent = genclk_set_parent,
- .index = 6,
-};
-
-struct platform_device *__init
-at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data)
-{
- struct platform_device *pdev;
- struct dw_dma_slave *dws;
- u32 pin_mask;
-
- if (id != 0 || !data)
- return NULL;
-
- pdev = platform_device_alloc("atmel_abdac", id);
- if (!pdev)
- return NULL;
-
- if (platform_device_add_resources(pdev, abdac0_resource,
- ARRAY_SIZE(abdac0_resource)))
- goto out_free_resources;
-
- dws = &data->dws;
-
- dws->dma_dev = &dw_dmac0_device.dev;
- dws->dst_id = 2;
- dws->m_master = 0;
- dws->p_master = 1;
-
- if (platform_device_add_data(pdev, data,
- sizeof(struct atmel_abdac_pdata)))
- goto out_free_resources;
-
- pin_mask = (1 << 20) | (1 << 22); /* DATA1 & DATAN1 */
- pin_mask |= (1 << 21) | (1 << 23); /* DATA0 & DATAN0 */
-
- select_peripheral(PIOB, pin_mask, PERIPH_A, 0);
-
- abdac0_pclk.dev = &pdev->dev;
- abdac0_sample_clk.dev = &pdev->dev;
-
- platform_device_add(pdev);
- return pdev;
-
-out_free_resources:
- platform_device_put(pdev);
- return NULL;
-}
-
-/* --------------------------------------------------------------------
- * GCLK
- * -------------------------------------------------------------------- */
-static struct clk gclk0 = {
- .name = "gclk0",
- .mode = genclk_mode,
- .get_rate = genclk_get_rate,
- .set_rate = genclk_set_rate,
- .set_parent = genclk_set_parent,
- .index = 0,
-};
-static struct clk gclk1 = {
- .name = "gclk1",
- .mode = genclk_mode,
- .get_rate = genclk_get_rate,
- .set_rate = genclk_set_rate,
- .set_parent = genclk_set_parent,
- .index = 1,
-};
-static struct clk gclk2 = {
- .name = "gclk2",
- .mode = genclk_mode,
- .get_rate = genclk_get_rate,
- .set_rate = genclk_set_rate,
- .set_parent = genclk_set_parent,
- .index = 2,
-};
-static struct clk gclk3 = {
- .name = "gclk3",
- .mode = genclk_mode,
- .get_rate = genclk_get_rate,
- .set_rate = genclk_set_rate,
- .set_parent = genclk_set_parent,
- .index = 3,
-};
-static struct clk gclk4 = {
- .name = "gclk4",
- .mode = genclk_mode,
- .get_rate = genclk_get_rate,
- .set_rate = genclk_set_rate,
- .set_parent = genclk_set_parent,
- .index = 4,
-};
-
-static __initdata struct clk *init_clocks[] = {
- &osc32k,
- &osc0,
- &osc1,
- &pll0,
- &pll1,
- &cpu_clk,
- &hsb_clk,
- &pba_clk,
- &pbb_clk,
- &at32_pm_pclk,
- &at32_intc0_pclk,
- &at32_hmatrix_clk,
- &ebi_clk,
- &hramc_clk,
- &sdramc_clk,
- &smc0_pclk,
- &smc0_mck,
- &pdc_hclk,
- &pdc_pclk,
- &dw_dmac0_hclk,
- &pico_clk,
- &pio0_mck,
- &pio1_mck,
- &pio2_mck,
- &pio3_mck,
- &pio4_mck,
- &at32_tcb0_t0_clk,
- &at32_tcb1_t0_clk,
- &atmel_psif0_pclk,
- &atmel_psif1_pclk,
- &atmel_usart0_usart,
- &atmel_usart1_usart,
- &atmel_usart2_usart,
- &atmel_usart3_usart,
- &atmel_pwm0_mck,
-#if defined(CONFIG_CPU_AT32AP7000)
- &macb0_hclk,
- &macb0_pclk,
- &macb1_hclk,
- &macb1_pclk,
-#endif
- &atmel_spi0_spi_clk,
- &atmel_spi1_spi_clk,
- &atmel_twi0_pclk,
- &atmel_mci0_pclk,
-#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
- &atmel_lcdfb0_hclk,
- &atmel_lcdfb0_pixclk,
-#endif
- &ssc0_pclk,
- &ssc1_pclk,
- &ssc2_pclk,
- &usba0_hclk,
- &usba0_pclk,
- &atmel_ac97c0_pclk,
- &abdac0_pclk,
- &abdac0_sample_clk,
- &gclk0,
- &gclk1,
- &gclk2,
- &gclk3,
- &gclk4,
-};
-
-void __init setup_platform(void)
-{
- u32 cpu_mask = 0, hsb_mask = 0, pba_mask = 0, pbb_mask = 0;
- int i;
-
- if (pm_readl(MCCTRL) & PM_BIT(PLLSEL)) {
- main_clock = &pll0;
- cpu_clk.parent = &pll0;
- } else {
- main_clock = &osc0;
- cpu_clk.parent = &osc0;
- }
-
- if (pm_readl(PLL0) & PM_BIT(PLLOSC))
- pll0.parent = &osc1;
- if (pm_readl(PLL1) & PM_BIT(PLLOSC))
- pll1.parent = &osc1;
-
- genclk_init_parent(&gclk0);
- genclk_init_parent(&gclk1);
- genclk_init_parent(&gclk2);
- genclk_init_parent(&gclk3);
- genclk_init_parent(&gclk4);
-#if defined(CONFIG_CPU_AT32AP7000) || defined(CONFIG_CPU_AT32AP7002)
- genclk_init_parent(&atmel_lcdfb0_pixclk);
-#endif
- genclk_init_parent(&abdac0_sample_clk);
-
- /*
- * Build initial dynamic clock list by registering all clocks
- * from the array.
- * At the same time, turn on all clocks that have at least one
- * user already, and turn off everything else. We only do this
- * for module clocks, and even though it isn't particularly
- * pretty to check the address of the mode function, it should
- * do the trick...
- */
- for (i = 0; i < ARRAY_SIZE(init_clocks); i++) {
- struct clk *clk = init_clocks[i];
-
- /* first, register clock */
- at32_clk_register(clk);
-
- if (clk->users == 0)
- continue;
-
- if (clk->mode == &cpu_clk_mode)
- cpu_mask |= 1 << clk->index;
- else if (clk->mode == &hsb_clk_mode)
- hsb_mask |= 1 << clk->index;
- else if (clk->mode == &pba_clk_mode)
- pba_mask |= 1 << clk->index;
- else if (clk->mode == &pbb_clk_mode)
- pbb_mask |= 1 << clk->index;
- }
-
- pm_writel(CPU_MASK, cpu_mask);
- pm_writel(HSB_MASK, hsb_mask);
- pm_writel(PBA_MASK, pba_mask);
- pm_writel(PBB_MASK, pbb_mask);
-
- /* Initialize the port muxes */
- at32_init_pio(&pio0_device);
- at32_init_pio(&pio1_device);
- at32_init_pio(&pio2_device);
- at32_init_pio(&pio3_device);
- at32_init_pio(&pio4_device);
-}
-
-struct gen_pool *sram_pool;
-
-static int __init sram_init(void)
-{
- struct gen_pool *pool;
-
- /* 1KiB granularity */
- pool = gen_pool_create(10, -1);
- if (!pool)
- goto fail;
-
- if (gen_pool_add(pool, 0x24000000, 0x8000, -1))
- goto err_pool_add;
-
- sram_pool = pool;
- return 0;
-
-err_pool_add:
- gen_pool_destroy(pool);
-fail:
- pr_err("Failed to create SRAM pool\n");
- return -ENOMEM;
-}
-core_initcall(sram_init);
diff --git a/arch/avr32/mach-at32ap/clock.c b/arch/avr32/mach-at32ap/clock.c
deleted file mode 100644
index fdf1caecb7b9..000000000000
--- a/arch/avr32/mach-at32ap/clock.c
+++ /dev/null
@@ -1,334 +0,0 @@
-/*
- * Clock management for AT32AP CPUs
- *
- * Copyright (C) 2006 Atmel Corporation
- *
- * Based on arch/arm/mach-at91/clock.c
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/export.h>
-#include <linux/device.h>
-#include <linux/string.h>
-#include <linux/list.h>
-
-#include <mach/chip.h>
-
-#include "clock.h"
-
-/* at32 clock list */
-static LIST_HEAD(at32_clock_list);
-
-static DEFINE_SPINLOCK(clk_lock);
-static DEFINE_SPINLOCK(clk_list_lock);
-
-void at32_clk_register(struct clk *clk)
-{
- spin_lock(&clk_list_lock);
- /* add the new item to the end of the list */
- list_add_tail(&clk->list, &at32_clock_list);
- spin_unlock(&clk_list_lock);
-}
-
-static struct clk *__clk_get(struct device *dev, const char *id)
-{
- struct clk *clk;
-
- list_for_each_entry(clk, &at32_clock_list, list) {
- if (clk->dev == dev && strcmp(id, clk->name) == 0) {
- return clk;
- }
- }
-
- return ERR_PTR(-ENOENT);
-}
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
- struct clk *clk;
-
- spin_lock(&clk_list_lock);
- clk = __clk_get(dev, id);
- spin_unlock(&clk_list_lock);
-
- return clk;
-}
-
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
- /* clocks are static for now, we can't free them */
-}
-EXPORT_SYMBOL(clk_put);
-
-static void __clk_enable(struct clk *clk)
-{
- if (clk->parent)
- __clk_enable(clk->parent);
- if (clk->users++ == 0 && clk->mode)
- clk->mode(clk, 1);
-}
-
-int clk_enable(struct clk *clk)
-{
- unsigned long flags;
-
- if (!clk)
- return 0;
-
- spin_lock_irqsave(&clk_lock, flags);
- __clk_enable(clk);
- spin_unlock_irqrestore(&clk_lock, flags);
-
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void __clk_disable(struct clk *clk)
-{
- if (clk->users == 0) {
- printk(KERN_ERR "%s: mismatched disable\n", clk->name);
- WARN_ON(1);
- return;
- }
-
- if (--clk->users == 0 && clk->mode)
- clk->mode(clk, 0);
- if (clk->parent)
- __clk_disable(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
- unsigned long flags;
-
- if (IS_ERR_OR_NULL(clk))
- return;
-
- spin_lock_irqsave(&clk_lock, flags);
- __clk_disable(clk);
- spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- unsigned long flags;
- unsigned long rate;
-
- if (!clk)
- return 0;
-
- spin_lock_irqsave(&clk_lock, flags);
- rate = clk->get_rate(clk);
- spin_unlock_irqrestore(&clk_lock, flags);
-
- return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags, actual_rate;
-
- if (!clk)
- return 0;
-
- if (!clk->set_rate)
- return -ENOSYS;
-
- spin_lock_irqsave(&clk_lock, flags);
- actual_rate = clk->set_rate(clk, rate, 0);
- spin_unlock_irqrestore(&clk_lock, flags);
-
- return actual_rate;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- unsigned long flags;
- long ret;
-
- if (!clk)
- return 0;
-
- if (!clk->set_rate)
- return -ENOSYS;
-
- spin_lock_irqsave(&clk_lock, flags);
- ret = clk->set_rate(clk, rate, 1);
- spin_unlock_irqrestore(&clk_lock, flags);
-
- return (ret < 0) ? ret : 0;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- unsigned long flags;
- int ret;
-
- if (!clk)
- return 0;
-
- if (!clk->set_parent)
- return -ENOSYS;
-
- spin_lock_irqsave(&clk_lock, flags);
- ret = clk->set_parent(clk, parent);
- spin_unlock_irqrestore(&clk_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
- return !clk ? NULL : clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-
-
-#ifdef CONFIG_DEBUG_FS
-
-/* /sys/kernel/debug/at32ap_clk */
-
-#include <linux/io.h>
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-#include "pm.h"
-
-
-#define NEST_DELTA 2
-#define NEST_MAX 6
-
-struct clkinf {
- struct seq_file *s;
- unsigned nest;
-};
-
-static void
-dump_clock(struct clk *parent, struct clkinf *r)
-{
- unsigned nest = r->nest;
- char buf[16 + NEST_MAX];
- struct clk *clk;
- unsigned i;
-
- /* skip clocks coupled to devices that aren't registered */
- if (parent->dev && !dev_name(parent->dev) && !parent->users)
- return;
-
- /* <nest spaces> name <pad to end> */
- memset(buf, ' ', sizeof(buf) - 1);
- buf[sizeof(buf) - 1] = 0;
- i = strlen(parent->name);
- memcpy(buf + nest, parent->name,
- min(i, (unsigned)(sizeof(buf) - 1 - nest)));
-
- seq_printf(r->s, "%s%c users=%2d %-3s %9ld Hz",
- buf, parent->set_parent ? '*' : ' ',
- parent->users,
- parent->users ? "on" : "off", /* NOTE: not-paranoid!! */
- clk_get_rate(parent));
- if (parent->dev)
- seq_printf(r->s, ", for %s", dev_name(parent->dev));
- seq_putc(r->s, '\n');
-
- /* cost of this scan is small, but not linear... */
- r->nest = nest + NEST_DELTA;
-
- list_for_each_entry(clk, &at32_clock_list, list) {
- if (clk->parent == parent)
- dump_clock(clk, r);
- }
- r->nest = nest;
-}
-
-static int clk_show(struct seq_file *s, void *unused)
-{
- struct clkinf r;
- int i;
- struct clk *clk;
-
- /* show all the power manager registers */
- seq_printf(s,
- "MCCTRL = %8x\n"
- "CKSEL = %8x\n"
- "CPUMASK = %8x\n"
- "HSBMASK = %8x\n"
- "PBAMASK = %8x\n"
- "PBBMASK = %8x\n"
- "PLL0 = %8x\n"
- "PLL1 = %8x\n"
- "IMR = %8x\n",
- pm_readl(MCCTRL),
- pm_readl(CKSEL),
- pm_readl(CPU_MASK),
- pm_readl(HSB_MASK),
- pm_readl(PBA_MASK),
- pm_readl(PBB_MASK),
- pm_readl(PLL0),
- pm_readl(PLL1),
- pm_readl(IMR));
- for (i = 0; i < 8; i++) {
- if (i == 5)
- continue;
- seq_printf(s, "GCCTRL%d = %8x\n", i, pm_readl(GCCTRL(i)));
- }
-
- seq_putc(s, '\n');
- r.s = s;
- r.nest = 0;
- /* protected from changes on the list while dumping */
- spin_lock(&clk_list_lock);
-
- /* show clock tree as derived from the three oscillators */
- clk = __clk_get(NULL, "osc32k");
- dump_clock(clk, &r);
- clk_put(clk);
-
- clk = __clk_get(NULL, "osc0");
- dump_clock(clk, &r);
- clk_put(clk);
-
- clk = __clk_get(NULL, "osc1");
- dump_clock(clk, &r);
- clk_put(clk);
-
- spin_unlock(&clk_list_lock);
-
- return 0;
-}
-
-static int clk_open(struct inode *inode, struct file *file)
-{
- return single_open(file, clk_show, NULL);
-}
-
-static const struct file_operations clk_operations = {
- .open = clk_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init clk_debugfs_init(void)
-{
- (void) debugfs_create_file("at32ap_clk", S_IFREG | S_IRUGO,
- NULL, NULL, &clk_operations);
-
- return 0;
-}
-postcore_initcall(clk_debugfs_init);
-
-#endif
diff --git a/arch/avr32/mach-at32ap/clock.h b/arch/avr32/mach-at32ap/clock.h
deleted file mode 100644
index 4c7ebbdc6dfa..000000000000
--- a/arch/avr32/mach-at32ap/clock.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Clock management for AT32AP CPUs
- *
- * Copyright (C) 2006 Atmel Corporation
- *
- * Based on arch/arm/mach-at91/clock.c
- * Copyright (C) 2005 David Brownell
- * Copyright (C) 2005 Ivan Kokshaysky
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/clk.h>
-#include <linux/list.h>
-
-
-void at32_clk_register(struct clk *clk);
-
-struct clk {
- struct list_head list; /* linking element */
- const char *name; /* Clock name/function */
- struct device *dev; /* Device the clock is used by */
- struct clk *parent; /* Parent clock, if any */
- void (*mode)(struct clk *clk, int enabled);
- unsigned long (*get_rate)(struct clk *clk);
- long (*set_rate)(struct clk *clk, unsigned long rate,
- int apply);
- int (*set_parent)(struct clk *clk, struct clk *parent);
- u16 users; /* Enabled if non-zero */
- u16 index; /* Sibling index */
-};
-
-unsigned long pba_clk_get_rate(struct clk *clk);
-void pba_clk_mode(struct clk *clk, int enabled);
diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c
deleted file mode 100644
index 96cabad68489..000000000000
--- a/arch/avr32/mach-at32ap/extint.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * External interrupt handling for AT32AP CPUs
- *
- * Copyright (C) 2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/errno.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/random.h>
-#include <linux/slab.h>
-
-#include <asm/io.h>
-
-/* EIC register offsets */
-#define EIC_IER 0x0000
-#define EIC_IDR 0x0004
-#define EIC_IMR 0x0008
-#define EIC_ISR 0x000c
-#define EIC_ICR 0x0010
-#define EIC_MODE 0x0014
-#define EIC_EDGE 0x0018
-#define EIC_LEVEL 0x001c
-#define EIC_NMIC 0x0024
-
-/* Bitfields in NMIC */
-#define EIC_NMIC_ENABLE (1 << 0)
-
-/* Bit manipulation macros */
-#define EIC_BIT(name) \
- (1 << EIC_##name##_OFFSET)
-#define EIC_BF(name,value) \
- (((value) & ((1 << EIC_##name##_SIZE) - 1)) \
- << EIC_##name##_OFFSET)
-#define EIC_BFEXT(name,value) \
- (((value) >> EIC_##name##_OFFSET) \
- & ((1 << EIC_##name##_SIZE) - 1))
-#define EIC_BFINS(name,value,old) \
- (((old) & ~(((1 << EIC_##name##_SIZE) - 1) \
- << EIC_##name##_OFFSET)) \
- | EIC_BF(name,value))
-
-/* Register access macros */
-#define eic_readl(port,reg) \
- __raw_readl((port)->regs + EIC_##reg)
-#define eic_writel(port,reg,value) \
- __raw_writel((value), (port)->regs + EIC_##reg)
-
-struct eic {
- void __iomem *regs;
- struct irq_chip *chip;
- unsigned int first_irq;
-};
-
-static struct eic *nmi_eic;
-static bool nmi_enabled;
-
-static void eic_ack_irq(struct irq_data *d)
-{
- struct eic *eic = irq_data_get_irq_chip_data(d);
- eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
-}
-
-static void eic_mask_irq(struct irq_data *d)
-{
- struct eic *eic = irq_data_get_irq_chip_data(d);
- eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
-}
-
-static void eic_mask_ack_irq(struct irq_data *d)
-{
- struct eic *eic = irq_data_get_irq_chip_data(d);
- eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
- eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
-}
-
-static void eic_unmask_irq(struct irq_data *d)
-{
- struct eic *eic = irq_data_get_irq_chip_data(d);
- eic_writel(eic, IER, 1 << (d->irq - eic->first_irq));
-}
-
-static int eic_set_irq_type(struct irq_data *d, unsigned int flow_type)
-{
- struct eic *eic = irq_data_get_irq_chip_data(d);
- unsigned int irq = d->irq;
- unsigned int i = irq - eic->first_irq;
- u32 mode, edge, level;
-
- flow_type &= IRQ_TYPE_SENSE_MASK;
- if (flow_type == IRQ_TYPE_NONE)
- flow_type = IRQ_TYPE_LEVEL_LOW;
-
- mode = eic_readl(eic, MODE);
- edge = eic_readl(eic, EDGE);
- level = eic_readl(eic, LEVEL);
-
- switch (flow_type) {
- case IRQ_TYPE_LEVEL_LOW:
- mode |= 1 << i;
- level &= ~(1 << i);
- break;
- case IRQ_TYPE_LEVEL_HIGH:
- mode |= 1 << i;
- level |= 1 << i;
- break;
- case IRQ_TYPE_EDGE_RISING:
- mode &= ~(1 << i);
- edge |= 1 << i;
- break;
- case IRQ_TYPE_EDGE_FALLING:
- mode &= ~(1 << i);
- edge &= ~(1 << i);
- break;
- default:
- return -EINVAL;
- }
-
- eic_writel(eic, MODE, mode);
- eic_writel(eic, EDGE, edge);
- eic_writel(eic, LEVEL, level);
-
- irqd_set_trigger_type(d, flow_type);
- if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
- irq_set_handler_locked(d, handle_level_irq);
- else
- irq_set_handler_locked(d, handle_edge_irq);
-
- return IRQ_SET_MASK_OK_NOCOPY;
-}
-
-static struct irq_chip eic_chip = {
- .name = "eic",
- .irq_ack = eic_ack_irq,
- .irq_mask = eic_mask_irq,
- .irq_mask_ack = eic_mask_ack_irq,
- .irq_unmask = eic_unmask_irq,
- .irq_set_type = eic_set_irq_type,
-};
-
-static void demux_eic_irq(struct irq_desc *desc)
-{
- struct eic *eic = irq_desc_get_handler_data(desc);
- unsigned long status, pending;
- unsigned int i;
-
- status = eic_readl(eic, ISR);
- pending = status & eic_readl(eic, IMR);
-
- while (pending) {
- i = fls(pending) - 1;
- pending &= ~(1 << i);
-
- generic_handle_irq(i + eic->first_irq);
- }
-}
-
-int nmi_enable(void)
-{
- nmi_enabled = true;
-
- if (nmi_eic)
- eic_writel(nmi_eic, NMIC, EIC_NMIC_ENABLE);
-
- return 0;
-}
-
-void nmi_disable(void)
-{
- if (nmi_eic)
- eic_writel(nmi_eic, NMIC, 0);
-
- nmi_enabled = false;
-}
-
-static int __init eic_probe(struct platform_device *pdev)
-{
- struct eic *eic;
- struct resource *regs;
- unsigned int i;
- unsigned int nr_of_irqs;
- unsigned int int_irq;
- int ret;
- u32 pattern;
-
- regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- int_irq = platform_get_irq(pdev, 0);
- if (!regs || (int)int_irq <= 0) {
- dev_dbg(&pdev->dev, "missing regs and/or irq resource\n");
- return -ENXIO;
- }
-
- ret = -ENOMEM;
- eic = kzalloc(sizeof(struct eic), GFP_KERNEL);
- if (!eic) {
- dev_dbg(&pdev->dev, "no memory for eic structure\n");
- goto err_kzalloc;
- }
-
- eic->first_irq = EIM_IRQ_BASE + 32 * pdev->id;
- eic->regs = ioremap(regs->start, resource_size(regs));
- if (!eic->regs) {
- dev_dbg(&pdev->dev, "failed to map regs\n");
- goto err_ioremap;
- }
-
- /*
- * Find out how many interrupt lines that are actually
- * implemented in hardware.
- */
- eic_writel(eic, IDR, ~0UL);
- eic_writel(eic, MODE, ~0UL);
- pattern = eic_readl(eic, MODE);
- nr_of_irqs = fls(pattern);
-
- /* Trigger on low level unless overridden by driver */
- eic_writel(eic, EDGE, 0UL);
- eic_writel(eic, LEVEL, 0UL);
-
- eic->chip = &eic_chip;
-
- for (i = 0; i < nr_of_irqs; i++) {
- irq_set_chip_and_handler(eic->first_irq + i, &eic_chip,
- handle_level_irq);
- irq_set_chip_data(eic->first_irq + i, eic);
- }
-
- irq_set_chained_handler_and_data(int_irq, demux_eic_irq, eic);
-
- if (pdev->id == 0) {
- nmi_eic = eic;
- if (nmi_enabled)
- /*
- * Someone tried to enable NMI before we were
- * ready. Do it now.
- */
- nmi_enable();
- }
-
- dev_info(&pdev->dev,
- "External Interrupt Controller at 0x%p, IRQ %u\n",
- eic->regs, int_irq);
- dev_info(&pdev->dev,
- "Handling %u external IRQs, starting with IRQ %u\n",
- nr_of_irqs, eic->first_irq);
-
- return 0;
-
-err_ioremap:
- kfree(eic);
-err_kzalloc:
- return ret;
-}
-
-static struct platform_driver eic_driver = {
- .driver = {
- .name = "at32_eic",
- },
-};
-
-static int __init eic_init(void)
-{
- return platform_driver_probe(&eic_driver, eic_probe);
-}
-arch_initcall(eic_init);
diff --git a/arch/avr32/mach-at32ap/hmatrix.c b/arch/avr32/mach-at32ap/hmatrix.c
deleted file mode 100644
index 48f5ede77468..000000000000
--- a/arch/avr32/mach-at32ap/hmatrix.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * High-Speed Bus Matrix helper functions
- *
- * Copyright (C) 2008 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/clk.h>
-#include <linux/io.h>
-
-#include <mach/chip.h>
-#include <mach/hmatrix.h>
-
-static inline void __hmatrix_write_reg(unsigned long offset, u32 value)
-{
- __raw_writel(value, (void __iomem __force *)(HMATRIX_BASE + offset));
-}
-
-static inline u32 __hmatrix_read_reg(unsigned long offset)
-{
- return __raw_readl((void __iomem __force *)(HMATRIX_BASE + offset));
-}
-
-/**
- * hmatrix_write_reg - write HMATRIX configuration register
- * @offset: register offset
- * @value: value to be written to the register at @offset
- */
-void hmatrix_write_reg(unsigned long offset, u32 value)
-{
- clk_enable(&at32_hmatrix_clk);
- __hmatrix_write_reg(offset, value);
- __hmatrix_read_reg(offset);
- clk_disable(&at32_hmatrix_clk);
-}
-
-/**
- * hmatrix_read_reg - read HMATRIX configuration register
- * @offset: register offset
- *
- * Returns the value of the register at @offset.
- */
-u32 hmatrix_read_reg(unsigned long offset)
-{
- u32 value;
-
- clk_enable(&at32_hmatrix_clk);
- value = __hmatrix_read_reg(offset);
- clk_disable(&at32_hmatrix_clk);
-
- return value;
-}
-
-/**
- * hmatrix_sfr_set_bits - set bits in a slave's Special Function Register
- * @slave_id: operate on the SFR belonging to this slave
- * @mask: mask of bits to be set in the SFR
- */
-void hmatrix_sfr_set_bits(unsigned int slave_id, u32 mask)
-{
- u32 value;
-
- clk_enable(&at32_hmatrix_clk);
- value = __hmatrix_read_reg(HMATRIX_SFR(slave_id));
- value |= mask;
- __hmatrix_write_reg(HMATRIX_SFR(slave_id), value);
- __hmatrix_read_reg(HMATRIX_SFR(slave_id));
- clk_disable(&at32_hmatrix_clk);
-}
-
-/**
- * hmatrix_sfr_set_bits - clear bits in a slave's Special Function Register
- * @slave_id: operate on the SFR belonging to this slave
- * @mask: mask of bits to be cleared in the SFR
- */
-void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask)
-{
- u32 value;
-
- clk_enable(&at32_hmatrix_clk);
- value = __hmatrix_read_reg(HMATRIX_SFR(slave_id));
- value &= ~mask;
- __hmatrix_write_reg(HMATRIX_SFR(slave_id), value);
- __hmatrix_read_reg(HMATRIX_SFR(slave_id));
- clk_disable(&at32_hmatrix_clk);
-}
diff --git a/arch/avr32/mach-at32ap/hsmc.c b/arch/avr32/mach-at32ap/hsmc.c
deleted file mode 100644
index f66245e6e63e..000000000000
--- a/arch/avr32/mach-at32ap/hsmc.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Static Memory Controller for AT32 chips
- *
- * Copyright (C) 2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include <asm/io.h>
-#include <mach/smc.h>
-
-#include "hsmc.h"
-
-#define NR_CHIP_SELECTS 6
-
-struct hsmc {
- void __iomem *regs;
- struct clk *pclk;
- struct clk *mck;
-};
-
-static struct hsmc *hsmc;
-
-void smc_set_timing(struct smc_config *config,
- const struct smc_timing *timing)
-{
- int recover;
- int cycle;
-
- unsigned long mul;
-
- /* Reset all SMC timings */
- config->ncs_read_setup = 0;
- config->nrd_setup = 0;
- config->ncs_write_setup = 0;
- config->nwe_setup = 0;
- config->ncs_read_pulse = 0;
- config->nrd_pulse = 0;
- config->ncs_write_pulse = 0;
- config->nwe_pulse = 0;
- config->read_cycle = 0;
- config->write_cycle = 0;
-
- /*
- * cycles = x / T = x * f
- * = ((x * 1000000000) * ((f * 65536) / 1000000000)) / 65536
- * = ((x * 1000000000) * (((f / 10000) * 65536) / 100000)) / 65536
- */
- mul = (clk_get_rate(hsmc->mck) / 10000) << 16;
- mul /= 100000;
-
-#define ns2cyc(x) ((((x) * mul) + 65535) >> 16)
-
- if (timing->ncs_read_setup > 0)
- config->ncs_read_setup = ns2cyc(timing->ncs_read_setup);
-
- if (timing->nrd_setup > 0)
- config->nrd_setup = ns2cyc(timing->nrd_setup);
-
- if (timing->ncs_write_setup > 0)
- config->ncs_write_setup = ns2cyc(timing->ncs_write_setup);
-
- if (timing->nwe_setup > 0)
- config->nwe_setup = ns2cyc(timing->nwe_setup);
-
- if (timing->ncs_read_pulse > 0)
- config->ncs_read_pulse = ns2cyc(timing->ncs_read_pulse);
-
- if (timing->nrd_pulse > 0)
- config->nrd_pulse = ns2cyc(timing->nrd_pulse);
-
- if (timing->ncs_write_pulse > 0)
- config->ncs_write_pulse = ns2cyc(timing->ncs_write_pulse);
-
- if (timing->nwe_pulse > 0)
- config->nwe_pulse = ns2cyc(timing->nwe_pulse);
-
- if (timing->read_cycle > 0)
- config->read_cycle = ns2cyc(timing->read_cycle);
-
- if (timing->write_cycle > 0)
- config->write_cycle = ns2cyc(timing->write_cycle);
-
- /* Extend read cycle in needed */
- if (timing->ncs_read_recover > 0)
- recover = ns2cyc(timing->ncs_read_recover);
- else
- recover = 1;
-
- cycle = config->ncs_read_setup + config->ncs_read_pulse + recover;
-
- if (config->read_cycle < cycle)
- config->read_cycle = cycle;
-
- /* Extend read cycle in needed */
- if (timing->nrd_recover > 0)
- recover = ns2cyc(timing->nrd_recover);
- else
- recover = 1;
-
- cycle = config->nrd_setup + config->nrd_pulse + recover;
-
- if (config->read_cycle < cycle)
- config->read_cycle = cycle;
-
- /* Extend write cycle in needed */
- if (timing->ncs_write_recover > 0)
- recover = ns2cyc(timing->ncs_write_recover);
- else
- recover = 1;
-
- cycle = config->ncs_write_setup + config->ncs_write_pulse + recover;
-
- if (config->write_cycle < cycle)
- config->write_cycle = cycle;
-
- /* Extend write cycle in needed */
- if (timing->nwe_recover > 0)
- recover = ns2cyc(timing->nwe_recover);
- else
- recover = 1;
-
- cycle = config->nwe_setup + config->nwe_pulse + recover;
-
- if (config->write_cycle < cycle)
- config->write_cycle = cycle;
-}
-EXPORT_SYMBOL(smc_set_timing);
-
-int smc_set_configuration(int cs, const struct smc_config *config)
-{
- unsigned long offset;
- u32 setup, pulse, cycle, mode;
-
- if (!hsmc)
- return -ENODEV;
- if (cs >= NR_CHIP_SELECTS)
- return -EINVAL;
-
- setup = (HSMC_BF(NWE_SETUP, config->nwe_setup)
- | HSMC_BF(NCS_WR_SETUP, config->ncs_write_setup)
- | HSMC_BF(NRD_SETUP, config->nrd_setup)
- | HSMC_BF(NCS_RD_SETUP, config->ncs_read_setup));
- pulse = (HSMC_BF(NWE_PULSE, config->nwe_pulse)
- | HSMC_BF(NCS_WR_PULSE, config->ncs_write_pulse)
- | HSMC_BF(NRD_PULSE, config->nrd_pulse)
- | HSMC_BF(NCS_RD_PULSE, config->ncs_read_pulse));
- cycle = (HSMC_BF(NWE_CYCLE, config->write_cycle)
- | HSMC_BF(NRD_CYCLE, config->read_cycle));
-
- switch (config->bus_width) {
- case 1:
- mode = HSMC_BF(DBW, HSMC_DBW_8_BITS);
- break;
- case 2:
- mode = HSMC_BF(DBW, HSMC_DBW_16_BITS);
- break;
- case 4:
- mode = HSMC_BF(DBW, HSMC_DBW_32_BITS);
- break;
- default:
- return -EINVAL;
- }
-
- switch (config->nwait_mode) {
- case 0:
- mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_DISABLED);
- break;
- case 1:
- mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_RESERVED);
- break;
- case 2:
- mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_FROZEN);
- break;
- case 3:
- mode |= HSMC_BF(EXNW_MODE, HSMC_EXNW_MODE_READY);
- break;
- default:
- return -EINVAL;
- }
-
- if (config->tdf_cycles) {
- mode |= HSMC_BF(TDF_CYCLES, config->tdf_cycles);
- }
-
- if (config->nrd_controlled)
- mode |= HSMC_BIT(READ_MODE);
- if (config->nwe_controlled)
- mode |= HSMC_BIT(WRITE_MODE);
- if (config->byte_write)
- mode |= HSMC_BIT(BAT);
- if (config->tdf_mode)
- mode |= HSMC_BIT(TDF_MODE);
-
- pr_debug("smc cs%d: setup/%08x pulse/%08x cycle/%08x mode/%08x\n",
- cs, setup, pulse, cycle, mode);
-
- offset = cs * 0x10;
- hsmc_writel(hsmc, SETUP0 + offset, setup);
- hsmc_writel(hsmc, PULSE0 + offset, pulse);
- hsmc_writel(hsmc, CYCLE0 + offset, cycle);
- hsmc_writel(hsmc, MODE0 + offset, mode);
- hsmc_readl(hsmc, MODE0); /* I/O barrier */
-
- return 0;
-}
-EXPORT_SYMBOL(smc_set_configuration);
-
-static int hsmc_probe(struct platform_device *pdev)
-{
- struct resource *regs;
- struct clk *pclk, *mck;
- int ret;
-
- if (hsmc)
- return -EBUSY;
-
- regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!regs)
- return -ENXIO;
- pclk = clk_get(&pdev->dev, "pclk");
- if (IS_ERR(pclk))
- return PTR_ERR(pclk);
- mck = clk_get(&pdev->dev, "mck");
- if (IS_ERR(mck)) {
- ret = PTR_ERR(mck);
- goto out_put_pclk;
- }
-
- ret = -ENOMEM;
- hsmc = kzalloc(sizeof(struct hsmc), GFP_KERNEL);
- if (!hsmc)
- goto out_put_clocks;
-
- clk_enable(pclk);
- clk_enable(mck);
-
- hsmc->pclk = pclk;
- hsmc->mck = mck;
- hsmc->regs = ioremap(regs->start, resource_size(regs));
- if (!hsmc->regs)
- goto out_disable_clocks;
-
- dev_info(&pdev->dev, "Atmel Static Memory Controller at 0x%08lx\n",
- (unsigned long)regs->start);
-
- platform_set_drvdata(pdev, hsmc);
-
- return 0;
-
-out_disable_clocks:
- clk_disable(mck);
- clk_disable(pclk);
- kfree(hsmc);
-out_put_clocks:
- clk_put(mck);
-out_put_pclk:
- clk_put(pclk);
- hsmc = NULL;
- return ret;
-}
-
-static struct platform_driver hsmc_driver = {
- .probe = hsmc_probe,
- .driver = {
- .name = "smc",
- },
-};
-
-static int __init hsmc_init(void)
-{
- return platform_driver_register(&hsmc_driver);
-}
-core_initcall(hsmc_init);
diff --git a/arch/avr32/mach-at32ap/hsmc.h b/arch/avr32/mach-at32ap/hsmc.h
deleted file mode 100644
index d1d48e26e393..000000000000
--- a/arch/avr32/mach-at32ap/hsmc.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Register definitions for Atmel Static Memory Controller (SMC)
- *
- * Copyright (C) 2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_AVR32_HSMC_H__
-#define __ASM_AVR32_HSMC_H__
-
-/* HSMC register offsets */
-#define HSMC_SETUP0 0x0000
-#define HSMC_PULSE0 0x0004
-#define HSMC_CYCLE0 0x0008
-#define HSMC_MODE0 0x000c
-#define HSMC_SETUP1 0x0010
-#define HSMC_PULSE1 0x0014
-#define HSMC_CYCLE1 0x0018
-#define HSMC_MODE1 0x001c
-#define HSMC_SETUP2 0x0020
-#define HSMC_PULSE2 0x0024
-#define HSMC_CYCLE2 0x0028
-#define HSMC_MODE2 0x002c
-#define HSMC_SETUP3 0x0030
-#define HSMC_PULSE3 0x0034
-#define HSMC_CYCLE3 0x0038
-#define HSMC_MODE3 0x003c
-#define HSMC_SETUP4 0x0040
-#define HSMC_PULSE4 0x0044
-#define HSMC_CYCLE4 0x0048
-#define HSMC_MODE4 0x004c
-#define HSMC_SETUP5 0x0050
-#define HSMC_PULSE5 0x0054
-#define HSMC_CYCLE5 0x0058
-#define HSMC_MODE5 0x005c
-
-/* Bitfields in SETUP0 */
-#define HSMC_NWE_SETUP_OFFSET 0
-#define HSMC_NWE_SETUP_SIZE 6
-#define HSMC_NCS_WR_SETUP_OFFSET 8
-#define HSMC_NCS_WR_SETUP_SIZE 6
-#define HSMC_NRD_SETUP_OFFSET 16
-#define HSMC_NRD_SETUP_SIZE 6
-#define HSMC_NCS_RD_SETUP_OFFSET 24
-#define HSMC_NCS_RD_SETUP_SIZE 6
-
-/* Bitfields in PULSE0 */
-#define HSMC_NWE_PULSE_OFFSET 0
-#define HSMC_NWE_PULSE_SIZE 7
-#define HSMC_NCS_WR_PULSE_OFFSET 8
-#define HSMC_NCS_WR_PULSE_SIZE 7
-#define HSMC_NRD_PULSE_OFFSET 16
-#define HSMC_NRD_PULSE_SIZE 7
-#define HSMC_NCS_RD_PULSE_OFFSET 24
-#define HSMC_NCS_RD_PULSE_SIZE 7
-
-/* Bitfields in CYCLE0 */
-#define HSMC_NWE_CYCLE_OFFSET 0
-#define HSMC_NWE_CYCLE_SIZE 9
-#define HSMC_NRD_CYCLE_OFFSET 16
-#define HSMC_NRD_CYCLE_SIZE 9
-
-/* Bitfields in MODE0 */
-#define HSMC_READ_MODE_OFFSET 0
-#define HSMC_READ_MODE_SIZE 1
-#define HSMC_WRITE_MODE_OFFSET 1
-#define HSMC_WRITE_MODE_SIZE 1
-#define HSMC_EXNW_MODE_OFFSET 4
-#define HSMC_EXNW_MODE_SIZE 2
-#define HSMC_BAT_OFFSET 8
-#define HSMC_BAT_SIZE 1
-#define HSMC_DBW_OFFSET 12
-#define HSMC_DBW_SIZE 2
-#define HSMC_TDF_CYCLES_OFFSET 16
-#define HSMC_TDF_CYCLES_SIZE 4
-#define HSMC_TDF_MODE_OFFSET 20
-#define HSMC_TDF_MODE_SIZE 1
-#define HSMC_PMEN_OFFSET 24
-#define HSMC_PMEN_SIZE 1
-#define HSMC_PS_OFFSET 28
-#define HSMC_PS_SIZE 2
-
-/* Constants for READ_MODE */
-#define HSMC_READ_MODE_NCS_CONTROLLED 0
-#define HSMC_READ_MODE_NRD_CONTROLLED 1
-
-/* Constants for WRITE_MODE */
-#define HSMC_WRITE_MODE_NCS_CONTROLLED 0
-#define HSMC_WRITE_MODE_NWE_CONTROLLED 1
-
-/* Constants for EXNW_MODE */
-#define HSMC_EXNW_MODE_DISABLED 0
-#define HSMC_EXNW_MODE_RESERVED 1
-#define HSMC_EXNW_MODE_FROZEN 2
-#define HSMC_EXNW_MODE_READY 3
-
-/* Constants for BAT */
-#define HSMC_BAT_BYTE_SELECT 0
-#define HSMC_BAT_BYTE_WRITE 1
-
-/* Constants for DBW */
-#define HSMC_DBW_8_BITS 0
-#define HSMC_DBW_16_BITS 1
-#define HSMC_DBW_32_BITS 2
-
-/* Bit manipulation macros */
-#define HSMC_BIT(name) \
- (1 << HSMC_##name##_OFFSET)
-#define HSMC_BF(name,value) \
- (((value) & ((1 << HSMC_##name##_SIZE) - 1)) \
- << HSMC_##name##_OFFSET)
-#define HSMC_BFEXT(name,value) \
- (((value) >> HSMC_##name##_OFFSET) \
- & ((1 << HSMC_##name##_SIZE) - 1))
-#define HSMC_BFINS(name,value,old) \
- (((old) & ~(((1 << HSMC_##name##_SIZE) - 1) \
- << HSMC_##name##_OFFSET)) | HSMC_BF(name,value))
-
-/* Register access macros */
-#define hsmc_readl(port,reg) \
- __raw_readl((port)->regs + HSMC_##reg)
-#define hsmc_writel(port,reg,value) \
- __raw_writel((value), (port)->regs + HSMC_##reg)
-
-#endif /* __ASM_AVR32_HSMC_H__ */
diff --git a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h b/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
deleted file mode 100644
index b9222bf895bc..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/at32ap700x.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/*
- * Pin definitions for AT32AP7000.
- *
- * Copyright (C) 2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_AT32AP700X_H__
-#define __ASM_ARCH_AT32AP700X_H__
-
-#define GPIO_PERIPH_A 0
-#define GPIO_PERIPH_B 1
-
-/*
- * Pin numbers identifying specific GPIO pins on the chip. They can
- * also be converted to IRQ numbers by passing them through
- * gpio_to_irq().
- */
-#define GPIO_PIOA_BASE (0)
-#define GPIO_PIOB_BASE (GPIO_PIOA_BASE + 32)
-#define GPIO_PIOC_BASE (GPIO_PIOB_BASE + 32)
-#define GPIO_PIOD_BASE (GPIO_PIOC_BASE + 32)
-#define GPIO_PIOE_BASE (GPIO_PIOD_BASE + 32)
-
-#define GPIO_PIN_PA(N) (GPIO_PIOA_BASE + (N))
-#define GPIO_PIN_PB(N) (GPIO_PIOB_BASE + (N))
-#define GPIO_PIN_PC(N) (GPIO_PIOC_BASE + (N))
-#define GPIO_PIN_PD(N) (GPIO_PIOD_BASE + (N))
-#define GPIO_PIN_PE(N) (GPIO_PIOE_BASE + (N))
-
-
-/*
- * DMAC peripheral hardware handshaking interfaces, used with dw_dmac
- */
-#define DMAC_MCI_RX 0
-#define DMAC_MCI_TX 1
-#define DMAC_DAC_TX 2
-#define DMAC_AC97_A_RX 3
-#define DMAC_AC97_A_TX 4
-#define DMAC_AC97_B_RX 5
-#define DMAC_AC97_B_TX 6
-#define DMAC_DMAREQ_0 7
-#define DMAC_DMAREQ_1 8
-#define DMAC_DMAREQ_2 9
-#define DMAC_DMAREQ_3 10
-
-/* HSB master IDs */
-#define HMATRIX_MASTER_CPU_DCACHE 0
-#define HMATRIX_MASTER_CPU_ICACHE 1
-#define HMATRIX_MASTER_PDC 2
-#define HMATRIX_MASTER_ISI 3
-#define HMATRIX_MASTER_USBA 4
-#define HMATRIX_MASTER_LCDC 5
-#define HMATRIX_MASTER_MACB0 6
-#define HMATRIX_MASTER_MACB1 7
-#define HMATRIX_MASTER_DMACA_M0 8
-#define HMATRIX_MASTER_DMACA_M1 9
-
-/* HSB slave IDs */
-#define HMATRIX_SLAVE_SRAM0 0
-#define HMATRIX_SLAVE_SRAM1 1
-#define HMATRIX_SLAVE_PBA 2
-#define HMATRIX_SLAVE_PBB 3
-#define HMATRIX_SLAVE_EBI 4
-#define HMATRIX_SLAVE_USBA 5
-#define HMATRIX_SLAVE_LCDC 6
-#define HMATRIX_SLAVE_DMACA 7
-
-/* Bits in HMATRIX SFR4 (EBI) */
-#define HMATRIX_EBI_SDRAM_ENABLE (1 << 1)
-#define HMATRIX_EBI_NAND_ENABLE (1 << 3)
-#define HMATRIX_EBI_CF0_ENABLE (1 << 4)
-#define HMATRIX_EBI_CF1_ENABLE (1 << 5)
-#define HMATRIX_EBI_PULLUP_DISABLE (1 << 8)
-
-/*
- * Base addresses of controllers that may be accessed early by
- * platform code.
- */
-#define PM_BASE 0xfff00000
-#define HMATRIX_BASE 0xfff00800
-#define SDRAMC_BASE 0xfff03800
-
-/* LCDC on port C */
-#define ATMEL_LCDC_PC_CC (1ULL << 19)
-#define ATMEL_LCDC_PC_HSYNC (1ULL << 20)
-#define ATMEL_LCDC_PC_PCLK (1ULL << 21)
-#define ATMEL_LCDC_PC_VSYNC (1ULL << 22)
-#define ATMEL_LCDC_PC_DVAL (1ULL << 23)
-#define ATMEL_LCDC_PC_MODE (1ULL << 24)
-#define ATMEL_LCDC_PC_PWR (1ULL << 25)
-#define ATMEL_LCDC_PC_DATA0 (1ULL << 26)
-#define ATMEL_LCDC_PC_DATA1 (1ULL << 27)
-#define ATMEL_LCDC_PC_DATA2 (1ULL << 28)
-#define ATMEL_LCDC_PC_DATA3 (1ULL << 29)
-#define ATMEL_LCDC_PC_DATA4 (1ULL << 30)
-#define ATMEL_LCDC_PC_DATA5 (1ULL << 31)
-
-/* LCDC on port D */
-#define ATMEL_LCDC_PD_DATA6 (1ULL << 0)
-#define ATMEL_LCDC_PD_DATA7 (1ULL << 1)
-#define ATMEL_LCDC_PD_DATA8 (1ULL << 2)
-#define ATMEL_LCDC_PD_DATA9 (1ULL << 3)
-#define ATMEL_LCDC_PD_DATA10 (1ULL << 4)
-#define ATMEL_LCDC_PD_DATA11 (1ULL << 5)
-#define ATMEL_LCDC_PD_DATA12 (1ULL << 6)
-#define ATMEL_LCDC_PD_DATA13 (1ULL << 7)
-#define ATMEL_LCDC_PD_DATA14 (1ULL << 8)
-#define ATMEL_LCDC_PD_DATA15 (1ULL << 9)
-#define ATMEL_LCDC_PD_DATA16 (1ULL << 10)
-#define ATMEL_LCDC_PD_DATA17 (1ULL << 11)
-#define ATMEL_LCDC_PD_DATA18 (1ULL << 12)
-#define ATMEL_LCDC_PD_DATA19 (1ULL << 13)
-#define ATMEL_LCDC_PD_DATA20 (1ULL << 14)
-#define ATMEL_LCDC_PD_DATA21 (1ULL << 15)
-#define ATMEL_LCDC_PD_DATA22 (1ULL << 16)
-#define ATMEL_LCDC_PD_DATA23 (1ULL << 17)
-
-/* LCDC on port E */
-#define ATMEL_LCDC_PE_CC (1ULL << (32 + 0))
-#define ATMEL_LCDC_PE_DVAL (1ULL << (32 + 1))
-#define ATMEL_LCDC_PE_MODE (1ULL << (32 + 2))
-#define ATMEL_LCDC_PE_DATA0 (1ULL << (32 + 3))
-#define ATMEL_LCDC_PE_DATA1 (1ULL << (32 + 4))
-#define ATMEL_LCDC_PE_DATA2 (1ULL << (32 + 5))
-#define ATMEL_LCDC_PE_DATA3 (1ULL << (32 + 6))
-#define ATMEL_LCDC_PE_DATA4 (1ULL << (32 + 7))
-#define ATMEL_LCDC_PE_DATA8 (1ULL << (32 + 8))
-#define ATMEL_LCDC_PE_DATA9 (1ULL << (32 + 9))
-#define ATMEL_LCDC_PE_DATA10 (1ULL << (32 + 10))
-#define ATMEL_LCDC_PE_DATA11 (1ULL << (32 + 11))
-#define ATMEL_LCDC_PE_DATA12 (1ULL << (32 + 12))
-#define ATMEL_LCDC_PE_DATA16 (1ULL << (32 + 13))
-#define ATMEL_LCDC_PE_DATA17 (1ULL << (32 + 14))
-#define ATMEL_LCDC_PE_DATA18 (1ULL << (32 + 15))
-#define ATMEL_LCDC_PE_DATA19 (1ULL << (32 + 16))
-#define ATMEL_LCDC_PE_DATA20 (1ULL << (32 + 17))
-#define ATMEL_LCDC_PE_DATA21 (1ULL << (32 + 18))
-
-
-#define ATMEL_LCDC(PORT, PIN) (ATMEL_LCDC_##PORT##_##PIN)
-
-
-#define ATMEL_LCDC_PRI_24B_DATA ( \
- ATMEL_LCDC(PC, DATA0) | ATMEL_LCDC(PC, DATA1) | \
- ATMEL_LCDC(PC, DATA2) | ATMEL_LCDC(PC, DATA3) | \
- ATMEL_LCDC(PC, DATA4) | ATMEL_LCDC(PC, DATA5) | \
- ATMEL_LCDC(PD, DATA6) | ATMEL_LCDC(PD, DATA7) | \
- ATMEL_LCDC(PD, DATA8) | ATMEL_LCDC(PD, DATA9) | \
- ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) | \
- ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA13) | \
- ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) | \
- ATMEL_LCDC(PD, DATA16) | ATMEL_LCDC(PD, DATA17) | \
- ATMEL_LCDC(PD, DATA18) | ATMEL_LCDC(PD, DATA19) | \
- ATMEL_LCDC(PD, DATA20) | ATMEL_LCDC(PD, DATA21) | \
- ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
-
-#define ATMEL_LCDC_ALT_24B_DATA ( \
- ATMEL_LCDC(PE, DATA0) | ATMEL_LCDC(PE, DATA1) | \
- ATMEL_LCDC(PE, DATA2) | ATMEL_LCDC(PE, DATA3) | \
- ATMEL_LCDC(PE, DATA4) | ATMEL_LCDC(PC, DATA5) | \
- ATMEL_LCDC(PD, DATA6) | ATMEL_LCDC(PD, DATA7) | \
- ATMEL_LCDC(PE, DATA8) | ATMEL_LCDC(PE, DATA9) | \
- ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) | \
- ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PD, DATA13) | \
- ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) | \
- ATMEL_LCDC(PE, DATA16) | ATMEL_LCDC(PE, DATA17) | \
- ATMEL_LCDC(PE, DATA18) | ATMEL_LCDC(PE, DATA19) | \
- ATMEL_LCDC(PE, DATA20) | ATMEL_LCDC(PE, DATA21) | \
- ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
-
-#define ATMEL_LCDC_PRI_18B_DATA ( \
- ATMEL_LCDC(PC, DATA2) | ATMEL_LCDC(PC, DATA3) | \
- ATMEL_LCDC(PC, DATA4) | ATMEL_LCDC(PC, DATA5) | \
- ATMEL_LCDC(PD, DATA6) | ATMEL_LCDC(PD, DATA7) | \
- ATMEL_LCDC(PD, DATA10) | ATMEL_LCDC(PD, DATA11) | \
- ATMEL_LCDC(PD, DATA12) | ATMEL_LCDC(PD, DATA13) | \
- ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) | \
- ATMEL_LCDC(PD, DATA18) | ATMEL_LCDC(PD, DATA19) | \
- ATMEL_LCDC(PD, DATA20) | ATMEL_LCDC(PD, DATA21) | \
- ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
-
-#define ATMEL_LCDC_ALT_18B_DATA ( \
- ATMEL_LCDC(PE, DATA2) | ATMEL_LCDC(PE, DATA3) | \
- ATMEL_LCDC(PE, DATA4) | ATMEL_LCDC(PC, DATA5) | \
- ATMEL_LCDC(PD, DATA6) | ATMEL_LCDC(PD, DATA7) | \
- ATMEL_LCDC(PE, DATA10) | ATMEL_LCDC(PE, DATA11) | \
- ATMEL_LCDC(PE, DATA12) | ATMEL_LCDC(PD, DATA13) | \
- ATMEL_LCDC(PD, DATA14) | ATMEL_LCDC(PD, DATA15) | \
- ATMEL_LCDC(PE, DATA18) | ATMEL_LCDC(PE, DATA19) | \
- ATMEL_LCDC(PE, DATA20) | ATMEL_LCDC(PE, DATA21) | \
- ATMEL_LCDC(PD, DATA22) | ATMEL_LCDC(PD, DATA23))
-
-#define ATMEL_LCDC_PRI_15B_DATA ( \
- ATMEL_LCDC(PC, DATA3) | ATMEL_LCDC(PC, DATA4) | \
- ATMEL_LCDC(PC, DATA5) | ATMEL_LCDC(PD, DATA6) | \
- ATMEL_LCDC(PD, DATA7) | \
- ATMEL_LCDC(PD, DATA11) | ATMEL_LCDC(PD, DATA12) | \
- ATMEL_LCDC(PD, DATA13) | ATMEL_LCDC(PD, DATA14) | \
- ATMEL_LCDC(PD, DATA15) | \
- ATMEL_LCDC(PD, DATA19) | ATMEL_LCDC(PD, DATA20) | \
- ATMEL_LCDC(PD, DATA21) | ATMEL_LCDC(PD, DATA22) | \
- ATMEL_LCDC(PD, DATA23))
-
-#define ATMEL_LCDC_ALT_15B_DATA ( \
- ATMEL_LCDC(PE, DATA3) | ATMEL_LCDC(PE, DATA4) | \
- ATMEL_LCDC(PC, DATA5) | ATMEL_LCDC(PD, DATA6) | \
- ATMEL_LCDC(PD, DATA7) | \
- ATMEL_LCDC(PE, DATA11) | ATMEL_LCDC(PE, DATA12) | \
- ATMEL_LCDC(PD, DATA13) | ATMEL_LCDC(PD, DATA14) | \
- ATMEL_LCDC(PD, DATA15) | \
- ATMEL_LCDC(PE, DATA19) | ATMEL_LCDC(PE, DATA20) | \
- ATMEL_LCDC(PE, DATA21) | ATMEL_LCDC(PD, DATA22) | \
- ATMEL_LCDC(PD, DATA23))
-
-#define ATMEL_LCDC_PRI_CONTROL ( \
- ATMEL_LCDC(PC, CC) | ATMEL_LCDC(PC, DVAL) | \
- ATMEL_LCDC(PC, MODE) | ATMEL_LCDC(PC, PWR))
-
-#define ATMEL_LCDC_ALT_CONTROL ( \
- ATMEL_LCDC(PE, CC) | ATMEL_LCDC(PE, DVAL) | \
- ATMEL_LCDC(PE, MODE) | ATMEL_LCDC(PC, PWR))
-
-#define ATMEL_LCDC_CONTROL ( \
- ATMEL_LCDC(PC, HSYNC) | ATMEL_LCDC(PC, VSYNC) | \
- ATMEL_LCDC(PC, PCLK))
-
-#define ATMEL_LCDC_PRI_24BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_24B_DATA)
-
-#define ATMEL_LCDC_ALT_24BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_24B_DATA)
-
-#define ATMEL_LCDC_PRI_18BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_18B_DATA)
-
-#define ATMEL_LCDC_ALT_18BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_18B_DATA)
-
-#define ATMEL_LCDC_PRI_15BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_PRI_15B_DATA)
-
-#define ATMEL_LCDC_ALT_15BIT (ATMEL_LCDC_CONTROL | ATMEL_LCDC_ALT_15B_DATA)
-
-/* Bitmask for all EBI data (D16..D31) pins on port E */
-#define ATMEL_EBI_PE_DATA_ALL (0x0000FFFF)
-
-#endif /* __ASM_ARCH_AT32AP700X_H__ */
diff --git a/arch/avr32/mach-at32ap/include/mach/board.h b/arch/avr32/mach-at32ap/include/mach/board.h
deleted file mode 100644
index f1a316d52c73..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/board.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Platform data definitions.
- */
-#ifndef __ASM_ARCH_BOARD_H
-#define __ASM_ARCH_BOARD_H
-
-#include <linux/types.h>
-#include <linux/serial.h>
-#include <linux/platform_data/macb.h>
-#include <linux/platform_data/atmel.h>
-
-#define GPIO_PIN_NONE (-1)
-
-/*
- * Clock rates for various on-board oscillators. The number of entries
- * in this array is chip-dependent.
- */
-extern unsigned long at32_board_osc_rates[];
-
-/*
- * This used to add essential system devices, but this is now done
- * automatically. Please don't use it in new board code.
- */
-static inline void __deprecated at32_add_system_devices(void)
-{
-
-}
-
-extern struct platform_device *atmel_default_console_device;
-
-/* Flags for selecting USART extra pins */
-#define ATMEL_USART_RTS 0x01
-#define ATMEL_USART_CTS 0x02
-#define ATMEL_USART_CLK 0x04
-
-void at32_map_usart(unsigned int hw_id, unsigned int line, int flags);
-struct platform_device *at32_add_device_usart(unsigned int id);
-
-struct platform_device *
-at32_add_device_eth(unsigned int id, struct macb_platform_data *data);
-
-struct spi_board_info;
-struct platform_device *
-at32_add_device_spi(unsigned int id, struct spi_board_info *b, unsigned int n);
-void at32_spi_setup_slaves(unsigned int bus_num, struct spi_board_info *b, unsigned int n);
-
-struct atmel_lcdfb_pdata;
-struct platform_device *
-at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_pdata *data,
- unsigned long fbmem_start, unsigned long fbmem_len,
- u64 pin_mask);
-
-struct usba_platform_data;
-struct platform_device *
-at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
-
-struct ide_platform_data {
- u8 cs;
-};
-struct platform_device *
-at32_add_device_ide(unsigned int id, unsigned int extint,
- struct ide_platform_data *data);
-
-/* mask says which PWM channels to mux */
-struct platform_device *at32_add_device_pwm(u32 mask);
-
-/* depending on what's hooked up, not all SSC pins will be used */
-#define ATMEL_SSC_TK 0x01
-#define ATMEL_SSC_TF 0x02
-#define ATMEL_SSC_TD 0x04
-#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
-
-#define ATMEL_SSC_RK 0x10
-#define ATMEL_SSC_RF 0x20
-#define ATMEL_SSC_RD 0x40
-#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
-
-struct platform_device *
-at32_add_device_ssc(unsigned int id, unsigned int flags);
-
-struct i2c_board_info;
-struct platform_device *at32_add_device_twi(unsigned int id,
- struct i2c_board_info *b,
- unsigned int n);
-
-struct mci_platform_data;
-struct platform_device *
-at32_add_device_mci(unsigned int id, struct mci_platform_data *data);
-
-struct ac97c_platform_data;
-struct platform_device *
-at32_add_device_ac97c(unsigned int id, struct ac97c_platform_data *data,
- unsigned int flags);
-
-struct atmel_abdac_pdata;
-struct platform_device *
-at32_add_device_abdac(unsigned int id, struct atmel_abdac_pdata *data);
-
-struct platform_device *at32_add_device_psif(unsigned int id);
-
-struct cf_platform_data {
- int detect_pin;
- int reset_pin;
- int vcc_pin;
- int ready_pin;
- u8 cs;
-};
-struct platform_device *
-at32_add_device_cf(unsigned int id, unsigned int extint,
- struct cf_platform_data *data);
-
-struct platform_device *
-at32_add_device_nand(unsigned int id, struct atmel_nand_data *data);
-
-#endif /* __ASM_ARCH_BOARD_H */
diff --git a/arch/avr32/mach-at32ap/include/mach/chip.h b/arch/avr32/mach-at32ap/include/mach/chip.h
deleted file mode 100644
index 5efca6da6acb..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/chip.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * AVR32 chip-specific definitions
- *
- * Copyright (C) 2008 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_AVR32_ARCH_CHIP_H__
-#define __ASM_AVR32_ARCH_CHIP_H__
-
-#if defined(CONFIG_CPU_AT32AP700X)
-# include <mach/at32ap700x.h>
-#else
-# error Unknown chip type selected
-#endif
-
-#endif /* __ASM_AVR32_ARCH_CHIP_H__ */
diff --git a/arch/avr32/mach-at32ap/include/mach/cpu.h b/arch/avr32/mach-at32ap/include/mach/cpu.h
deleted file mode 100644
index 4181086f4ddc..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/cpu.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * AVR32 CPU identification
- *
- * Copyright (C) 2007 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_CPU_H
-#define __ASM_ARCH_CPU_H
-
-/*
- * Only AT32AP7000 is defined for now. We can identify the specific
- * chip at runtime, but I'm not sure if it's really worth it.
- */
-#ifdef CONFIG_CPU_AT32AP700X
-# define cpu_is_at32ap7000() (1)
-#else
-# define cpu_is_at32ap7000() (0)
-#endif
-
-#endif /* __ASM_ARCH_CPU_H */
diff --git a/arch/avr32/mach-at32ap/include/mach/gpio.h b/arch/avr32/mach-at32ap/include/mach/gpio.h
deleted file mode 100644
index 0180f584ef03..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/gpio.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifndef __ASM_AVR32_ARCH_GPIO_H
-#define __ASM_AVR32_ARCH_GPIO_H
-
-#include <linux/compiler.h>
-#include <asm/irq.h>
-
-
-/* Some GPIO chips can manage IRQs; some can't. The exact numbers can
- * be changed if needed, but for the moment they're not configurable.
- */
-#define ARCH_NR_GPIOS (NR_GPIO_IRQS + 2 * 32)
-
-
-/* Arch-neutral GPIO API, supporting both "native" and external GPIOs. */
-#include <asm-generic/gpio.h>
-
-static inline int gpio_get_value(unsigned int gpio)
-{
- return __gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned int gpio, int value)
-{
- __gpio_set_value(gpio, value);
-}
-
-static inline int gpio_cansleep(unsigned int gpio)
-{
- return __gpio_cansleep(gpio);
-}
-
-
-static inline int gpio_to_irq(unsigned int gpio)
-{
- if (gpio < NR_GPIO_IRQS)
- return gpio + GPIO_IRQ_BASE;
- return -EINVAL;
-}
-
-static inline int irq_to_gpio(unsigned int irq)
-{
- return irq - GPIO_IRQ_BASE;
-}
-
-#endif /* __ASM_AVR32_ARCH_GPIO_H */
diff --git a/arch/avr32/mach-at32ap/include/mach/hmatrix.h b/arch/avr32/mach-at32ap/include/mach/hmatrix.h
deleted file mode 100644
index 7a368f227ebc..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/hmatrix.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * High-Speed Bus Matrix configuration registers
- *
- * Copyright (C) 2008 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __HMATRIX_H
-#define __HMATRIX_H
-
-extern struct clk at32_hmatrix_clk;
-
-void hmatrix_write_reg(unsigned long offset, u32 value);
-u32 hmatrix_read_reg(unsigned long offset);
-
-void hmatrix_sfr_set_bits(unsigned int slave_id, u32 mask);
-void hmatrix_sfr_clear_bits(unsigned int slave_id, u32 mask);
-
-/* Master Configuration register */
-#define HMATRIX_MCFG(m) (0x0000 + 4 * (m))
-/* Undefined length burst limit */
-# define HMATRIX_MCFG_ULBT_INFINITE 0 /* Infinite length */
-# define HMATRIX_MCFG_ULBT_SINGLE 1 /* Single Access */
-# define HMATRIX_MCFG_ULBT_FOUR_BEAT 2 /* Four beat */
-# define HMATRIX_MCFG_ULBT_EIGHT_BEAT 3 /* Eight beat */
-# define HMATRIX_MCFG_ULBT_SIXTEEN_BEAT 4 /* Sixteen beat */
-
-/* Slave Configuration register */
-#define HMATRIX_SCFG(s) (0x0040 + 4 * (s))
-# define HMATRIX_SCFG_SLOT_CYCLE(x) ((x) << 0) /* Max burst cycles */
-# define HMATRIX_SCFG_DEFMSTR_NONE ( 0 << 16) /* No default master */
-# define HMATRIX_SCFG_DEFMSTR_LAST ( 1 << 16) /* Last def master */
-# define HMATRIX_SCFG_DEFMSTR_FIXED ( 2 << 16) /* Fixed def master */
-# define HMATRIX_SCFG_FIXED_DEFMSTR(m) ((m) << 18) /* Fixed master ID */
-# define HMATRIX_SCFG_ARBT_ROUND_ROBIN ( 0 << 24) /* RR arbitration */
-# define HMATRIX_SCFG_ARBT_FIXED_PRIO ( 1 << 24) /* Fixed priority */
-
-/* Slave Priority register A (master 0..7) */
-#define HMATRIX_PRAS(s) (0x0080 + 8 * (s))
-# define HMATRIX_PRAS_PRIO(m, p) ((p) << ((m) * 4))
-
-/* Slave Priority register A (master 8..15) */
-#define HMATRIX_PRBS(s) (0x0084 + 8 * (s))
-# define HMATRIX_PRBS_PRIO(m, p) ((p) << (((m) - 8) * 4))
-
-/* Master Remap Control Register */
-#define HMATRIX_MRCR 0x0100
-# define HMATRIX_MRCR_REMAP(m) ( 1 << (m)) /* Remap master m */
-
-/* Special Function Register. Bit definitions are chip-specific */
-#define HMATRIX_SFR(s) (0x0110 + 4 * (s))
-
-#endif /* __HMATRIX_H */
diff --git a/arch/avr32/mach-at32ap/include/mach/init.h b/arch/avr32/mach-at32ap/include/mach/init.h
deleted file mode 100644
index bc40e3d46150..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/init.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * AT32AP platform initialization calls.
- *
- * Copyright (C) 2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_AVR32_AT32AP_INIT_H__
-#define __ASM_AVR32_AT32AP_INIT_H__
-
-void setup_platform(void);
-void setup_board(void);
-
-void at32_setup_serial_console(unsigned int usart_id);
-
-#endif /* __ASM_AVR32_AT32AP_INIT_H__ */
diff --git a/arch/avr32/mach-at32ap/include/mach/io.h b/arch/avr32/mach-at32ap/include/mach/io.h
deleted file mode 100644
index 22ea79b74052..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/io.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef __ASM_AVR32_ARCH_AT32AP_IO_H
-#define __ASM_AVR32_ARCH_AT32AP_IO_H
-
-#include <linux/swab.h>
-
-#if defined(CONFIG_AP700X_32_BIT_SMC)
-# define __swizzle_addr_b(addr) (addr ^ 3UL)
-# define __swizzle_addr_w(addr) (addr ^ 2UL)
-# define __swizzle_addr_l(addr) (addr)
-# define ioswabb(a, x) (x)
-# define ioswabw(a, x) (x)
-# define ioswabl(a, x) (x)
-# define __mem_ioswabb(a, x) (x)
-# define __mem_ioswabw(a, x) swab16(x)
-# define __mem_ioswabl(a, x) swab32(x)
-#elif defined(CONFIG_AP700X_16_BIT_SMC)
-# define __swizzle_addr_b(addr) (addr ^ 1UL)
-# define __swizzle_addr_w(addr) (addr)
-# define __swizzle_addr_l(addr) (addr)
-# define ioswabb(a, x) (x)
-# define ioswabw(a, x) (x)
-# define ioswabl(a, x) swahw32(x)
-# define __mem_ioswabb(a, x) (x)
-# define __mem_ioswabw(a, x) swab16(x)
-# define __mem_ioswabl(a, x) swahb32(x)
-#else
-# define __swizzle_addr_b(addr) (addr)
-# define __swizzle_addr_w(addr) (addr)
-# define __swizzle_addr_l(addr) (addr)
-# define ioswabb(a, x) (x)
-# define ioswabw(a, x) swab16(x)
-# define ioswabl(a, x) swab32(x)
-# define __mem_ioswabb(a, x) (x)
-# define __mem_ioswabw(a, x) (x)
-# define __mem_ioswabl(a, x) (x)
-#endif
-
-#endif /* __ASM_AVR32_ARCH_AT32AP_IO_H */
diff --git a/arch/avr32/mach-at32ap/include/mach/irq.h b/arch/avr32/mach-at32ap/include/mach/irq.h
deleted file mode 100644
index 608e350368c7..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/irq.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __ASM_AVR32_ARCH_IRQ_H
-#define __ASM_AVR32_ARCH_IRQ_H
-
-#define EIM_IRQ_BASE NR_INTERNAL_IRQS
-#define NR_EIM_IRQS 32
-#define AT32_EXTINT(n) (EIM_IRQ_BASE + (n))
-
-#define GPIO_IRQ_BASE (EIM_IRQ_BASE + NR_EIM_IRQS)
-#define NR_GPIO_CTLR (5 /*internal*/ + 1 /*external*/)
-#define NR_GPIO_IRQS (NR_GPIO_CTLR * 32)
-
-#define NR_IRQS (GPIO_IRQ_BASE + NR_GPIO_IRQS)
-
-#endif /* __ASM_AVR32_ARCH_IRQ_H */
diff --git a/arch/avr32/mach-at32ap/include/mach/pm.h b/arch/avr32/mach-at32ap/include/mach/pm.h
deleted file mode 100644
index f29ff2cd23d3..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/pm.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * AVR32 AP Power Management.
- *
- * Copyright (C) 2008 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_AVR32_ARCH_PM_H
-#define __ASM_AVR32_ARCH_PM_H
-
-/* Possible arguments to the "sleep" instruction */
-#define CPU_SLEEP_IDLE 0
-#define CPU_SLEEP_FROZEN 1
-#define CPU_SLEEP_STANDBY 2
-#define CPU_SLEEP_STOP 3
-#define CPU_SLEEP_STATIC 5
-
-#ifndef __ASSEMBLY__
-extern void cpu_enter_idle(void);
-extern void cpu_enter_standby(unsigned long sdramc_base);
-
-void intc_set_suspend_handler(unsigned long offset);
-#endif
-
-#endif /* __ASM_AVR32_ARCH_PM_H */
diff --git a/arch/avr32/mach-at32ap/include/mach/portmux.h b/arch/avr32/mach-at32ap/include/mach/portmux.h
deleted file mode 100644
index 4873024e3b96..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/portmux.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * AT32 portmux interface.
- *
- * Copyright (C) 2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_PORTMUX_H__
-#define __ASM_ARCH_PORTMUX_H__
-
-/*
- * Set up pin multiplexing, called from board init only.
- *
- * The following flags determine the initial state of the pin.
- */
-#define AT32_GPIOF_PULLUP 0x00000001 /* (not-OUT) Enable pull-up */
-#define AT32_GPIOF_OUTPUT 0x00000002 /* (OUT) Enable output driver */
-#define AT32_GPIOF_HIGH 0x00000004 /* (OUT) Set output high */
-#define AT32_GPIOF_DEGLITCH 0x00000008 /* (IN) Filter glitches */
-#define AT32_GPIOF_MULTIDRV 0x00000010 /* Enable multidriver option */
-
-void at32_select_periph(unsigned int port, unsigned int pin,
- unsigned int periph, unsigned long flags);
-void at32_select_gpio(unsigned int pin, unsigned long flags);
-void at32_deselect_pin(unsigned int pin);
-void at32_reserve_pin(unsigned int port, u32 pin_mask);
-
-#endif /* __ASM_ARCH_PORTMUX_H__ */
diff --git a/arch/avr32/mach-at32ap/include/mach/smc.h b/arch/avr32/mach-at32ap/include/mach/smc.h
deleted file mode 100644
index c98eea44a70a..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/smc.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Static Memory Controller for AT32 chips
- *
- * Copyright (C) 2006 Atmel Corporation
- *
- * Inspired by the OMAP2 General-Purpose Memory Controller interface
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_AT32AP_SMC_H
-#define __ARCH_AT32AP_SMC_H
-
-/*
- * All timing parameters are in nanoseconds.
- */
-struct smc_timing {
- /* Delay from address valid to assertion of given strobe */
- int ncs_read_setup;
- int nrd_setup;
- int ncs_write_setup;
- int nwe_setup;
-
- /* Pulse length of given strobe */
- int ncs_read_pulse;
- int nrd_pulse;
- int ncs_write_pulse;
- int nwe_pulse;
-
- /* Total cycle length of given operation */
- int read_cycle;
- int write_cycle;
-
- /* Minimal recovery times, will extend cycle if needed */
- int ncs_read_recover;
- int nrd_recover;
- int ncs_write_recover;
- int nwe_recover;
-};
-
-/*
- * All timing parameters are in clock cycles.
- */
-struct smc_config {
-
- /* Delay from address valid to assertion of given strobe */
- u8 ncs_read_setup;
- u8 nrd_setup;
- u8 ncs_write_setup;
- u8 nwe_setup;
-
- /* Pulse length of given strobe */
- u8 ncs_read_pulse;
- u8 nrd_pulse;
- u8 ncs_write_pulse;
- u8 nwe_pulse;
-
- /* Total cycle length of given operation */
- u8 read_cycle;
- u8 write_cycle;
-
- /* Bus width in bytes */
- u8 bus_width;
-
- /*
- * 0: Data is sampled on rising edge of NCS
- * 1: Data is sampled on rising edge of NRD
- */
- unsigned int nrd_controlled:1;
-
- /*
- * 0: Data is driven on falling edge of NCS
- * 1: Data is driven on falling edge of NWR
- */
- unsigned int nwe_controlled:1;
-
- /*
- * 0: NWAIT is disabled
- * 1: Reserved
- * 2: NWAIT is frozen mode
- * 3: NWAIT in ready mode
- */
- unsigned int nwait_mode:2;
-
- /*
- * 0: Byte select access type
- * 1: Byte write access type
- */
- unsigned int byte_write:1;
-
- /*
- * Number of clock cycles before data is released after
- * the rising edge of the read controlling signal
- *
- * Total cycles from SMC is tdf_cycles + 1
- */
- unsigned int tdf_cycles:4;
-
- /*
- * 0: TDF optimization disabled
- * 1: TDF optimization enabled
- */
- unsigned int tdf_mode:1;
-};
-
-extern void smc_set_timing(struct smc_config *config,
- const struct smc_timing *timing);
-
-extern int smc_set_configuration(int cs, const struct smc_config *config);
-extern struct smc_config *smc_get_configuration(int cs);
-
-#endif /* __ARCH_AT32AP_SMC_H */
diff --git a/arch/avr32/mach-at32ap/include/mach/sram.h b/arch/avr32/mach-at32ap/include/mach/sram.h
deleted file mode 100644
index 4838dae7601a..000000000000
--- a/arch/avr32/mach-at32ap/include/mach/sram.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Simple SRAM allocator
- *
- * Copyright (C) 2008 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ASM_AVR32_ARCH_SRAM_H
-#define __ASM_AVR32_ARCH_SRAM_H
-
-#include <linux/genalloc.h>
-
-extern struct gen_pool *sram_pool;
-
-static inline unsigned long sram_alloc(size_t len)
-{
- if (!sram_pool)
- return 0UL;
-
- return gen_pool_alloc(sram_pool, len);
-}
-
-static inline void sram_free(unsigned long addr, size_t len)
-{
- return gen_pool_free(sram_pool, addr, len);
-}
-
-#endif /* __ASM_AVR32_ARCH_SRAM_H */
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
deleted file mode 100644
index aaff83cc50f0..000000000000
--- a/arch/avr32/mach-at32ap/intc.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * Copyright (C) 2006, 2008 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/platform_device.h>
-#include <linux/syscore_ops.h>
-#include <linux/export.h>
-
-#include <asm/io.h>
-
-#include "intc.h"
-
-struct intc {
- void __iomem *regs;
- struct irq_chip chip;
-#ifdef CONFIG_PM
- unsigned long suspend_ipr;
- unsigned long saved_ipr[64];
-#endif
-};
-
-extern struct platform_device at32_intc0_device;
-
-/*
- * TODO: We may be able to implement mask/unmask by setting IxM flags
- * in the status register.
- */
-static void intc_mask_irq(struct irq_data *d)
-{
-
-}
-
-static void intc_unmask_irq(struct irq_data *d)
-{
-
-}
-
-static struct intc intc0 = {
- .chip = {
- .name = "intc",
- .irq_mask = intc_mask_irq,
- .irq_unmask = intc_unmask_irq,
- },
-};
-
-/*
- * All interrupts go via intc at some point.
- */
-asmlinkage void do_IRQ(int level, struct pt_regs *regs)
-{
- struct pt_regs *old_regs;
- unsigned int irq;
- unsigned long status_reg;
-
- local_irq_disable();
-
- old_regs = set_irq_regs(regs);
-
- irq_enter();
-
- irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
- generic_handle_irq(irq);
-
- /*
- * Clear all interrupt level masks so that we may handle
- * interrupts during softirq processing. If this is a nested
- * interrupt, interrupts must stay globally disabled until we
- * return.
- */
- status_reg = sysreg_read(SR);
- status_reg &= ~(SYSREG_BIT(I0M) | SYSREG_BIT(I1M)
- | SYSREG_BIT(I2M) | SYSREG_BIT(I3M));
- sysreg_write(SR, status_reg);
-
- irq_exit();
-
- set_irq_regs(old_regs);
-}
-
-void __init init_IRQ(void)
-{
- extern void _evba(void);
- extern void irq_level0(void);
- struct resource *regs;
- struct clk *pclk;
- unsigned int i;
- u32 offset, readback;
-
- regs = platform_get_resource(&at32_intc0_device, IORESOURCE_MEM, 0);
- if (!regs) {
- printk(KERN_EMERG "intc: no mmio resource defined\n");
- goto fail;
- }
- pclk = clk_get(&at32_intc0_device.dev, "pclk");
- if (IS_ERR(pclk)) {
- printk(KERN_EMERG "intc: no clock defined\n");
- goto fail;
- }
-
- clk_enable(pclk);
-
- intc0.regs = ioremap(regs->start, resource_size(regs));
- if (!intc0.regs) {
- printk(KERN_EMERG "intc: failed to map registers (0x%08lx)\n",
- (unsigned long)regs->start);
- goto fail;
- }
-
- /*
- * Initialize all interrupts to level 0 (lowest priority). The
- * priority level may be changed by calling
- * irq_set_priority().
- *
- */
- offset = (unsigned long)&irq_level0 - (unsigned long)&_evba;
- for (i = 0; i < NR_INTERNAL_IRQS; i++) {
- intc_writel(&intc0, INTPR0 + 4 * i, offset);
- readback = intc_readl(&intc0, INTPR0 + 4 * i);
- if (readback == offset)
- irq_set_chip_and_handler(i, &intc0.chip,
- handle_simple_irq);
- }
-
- /* Unmask all interrupt levels */
- sysreg_write(SR, (sysreg_read(SR)
- & ~(SR_I3M | SR_I2M | SR_I1M | SR_I0M)));
-
- return;
-
-fail:
- panic("Interrupt controller initialization failed!\n");
-}
-
-#ifdef CONFIG_PM
-void intc_set_suspend_handler(unsigned long offset)
-{
- intc0.suspend_ipr = offset;
-}
-
-static int intc_suspend(void)
-{
- int i;
-
- if (unlikely(!irqs_disabled())) {
- pr_err("intc_suspend: called with interrupts enabled\n");
- return -EINVAL;
- }
-
- if (unlikely(!intc0.suspend_ipr)) {
- pr_err("intc_suspend: suspend_ipr not initialized\n");
- return -EINVAL;
- }
-
- for (i = 0; i < 64; i++) {
- intc0.saved_ipr[i] = intc_readl(&intc0, INTPR0 + 4 * i);
- intc_writel(&intc0, INTPR0 + 4 * i, intc0.suspend_ipr);
- }
-
- return 0;
-}
-
-static void intc_resume(void)
-{
- int i;
-
- for (i = 0; i < 64; i++)
- intc_writel(&intc0, INTPR0 + 4 * i, intc0.saved_ipr[i]);
-}
-#else
-#define intc_suspend NULL
-#define intc_resume NULL
-#endif
-
-static struct syscore_ops intc_syscore_ops = {
- .suspend = intc_suspend,
- .resume = intc_resume,
-};
-
-static int __init intc_init_syscore(void)
-{
- register_syscore_ops(&intc_syscore_ops);
-
- return 0;
-}
-device_initcall(intc_init_syscore);
-
-unsigned long intc_get_pending(unsigned int group)
-{
- return intc_readl(&intc0, INTREQ0 + 4 * group);
-}
-EXPORT_SYMBOL_GPL(intc_get_pending);
diff --git a/arch/avr32/mach-at32ap/intc.h b/arch/avr32/mach-at32ap/intc.h
deleted file mode 100644
index 4d3664e43a8e..000000000000
--- a/arch/avr32/mach-at32ap/intc.h
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * Automatically generated by gen-header.xsl
- */
-#ifndef __ASM_AVR32_PERIHP_INTC_H__
-#define __ASM_AVR32_PERIHP_INTC_H__
-
-#define INTC_NUM_INT_GRPS 33
-
-#define INTC_INTPR0 0x0
-# define INTC_INTPR0_INTLEV_OFFSET 30
-# define INTC_INTPR0_INTLEV_SIZE 2
-# define INTC_INTPR0_OFFSET_OFFSET 0
-# define INTC_INTPR0_OFFSET_SIZE 24
-#define INTC_INTREQ0 0x100
-# define INTC_INTREQ0_IREQUEST0_OFFSET 0
-# define INTC_INTREQ0_IREQUEST0_SIZE 1
-# define INTC_INTREQ0_IREQUEST1_OFFSET 1
-# define INTC_INTREQ0_IREQUEST1_SIZE 1
-#define INTC_INTPR1 0x4
-# define INTC_INTPR1_INTLEV_OFFSET 30
-# define INTC_INTPR1_INTLEV_SIZE 2
-# define INTC_INTPR1_OFFSET_OFFSET 0
-# define INTC_INTPR1_OFFSET_SIZE 24
-#define INTC_INTREQ1 0x104
-# define INTC_INTREQ1_IREQUEST32_OFFSET 0
-# define INTC_INTREQ1_IREQUEST32_SIZE 1
-# define INTC_INTREQ1_IREQUEST33_OFFSET 1
-# define INTC_INTREQ1_IREQUEST33_SIZE 1
-# define INTC_INTREQ1_IREQUEST34_OFFSET 2
-# define INTC_INTREQ1_IREQUEST34_SIZE 1
-# define INTC_INTREQ1_IREQUEST35_OFFSET 3
-# define INTC_INTREQ1_IREQUEST35_SIZE 1
-# define INTC_INTREQ1_IREQUEST36_OFFSET 4
-# define INTC_INTREQ1_IREQUEST36_SIZE 1
-# define INTC_INTREQ1_IREQUEST37_OFFSET 5
-# define INTC_INTREQ1_IREQUEST37_SIZE 1
-#define INTC_INTPR2 0x8
-# define INTC_INTPR2_INTLEV_OFFSET 30
-# define INTC_INTPR2_INTLEV_SIZE 2
-# define INTC_INTPR2_OFFSET_OFFSET 0
-# define INTC_INTPR2_OFFSET_SIZE 24
-#define INTC_INTREQ2 0x108
-# define INTC_INTREQ2_IREQUEST64_OFFSET 0
-# define INTC_INTREQ2_IREQUEST64_SIZE 1
-# define INTC_INTREQ2_IREQUEST65_OFFSET 1
-# define INTC_INTREQ2_IREQUEST65_SIZE 1
-# define INTC_INTREQ2_IREQUEST66_OFFSET 2
-# define INTC_INTREQ2_IREQUEST66_SIZE 1
-# define INTC_INTREQ2_IREQUEST67_OFFSET 3
-# define INTC_INTREQ2_IREQUEST67_SIZE 1
-# define INTC_INTREQ2_IREQUEST68_OFFSET 4
-# define INTC_INTREQ2_IREQUEST68_SIZE 1
-#define INTC_INTPR3 0xc
-# define INTC_INTPR3_INTLEV_OFFSET 30
-# define INTC_INTPR3_INTLEV_SIZE 2
-# define INTC_INTPR3_OFFSET_OFFSET 0
-# define INTC_INTPR3_OFFSET_SIZE 24
-#define INTC_INTREQ3 0x10c
-# define INTC_INTREQ3_IREQUEST96_OFFSET 0
-# define INTC_INTREQ3_IREQUEST96_SIZE 1
-#define INTC_INTPR4 0x10
-# define INTC_INTPR4_INTLEV_OFFSET 30
-# define INTC_INTPR4_INTLEV_SIZE 2
-# define INTC_INTPR4_OFFSET_OFFSET 0
-# define INTC_INTPR4_OFFSET_SIZE 24
-#define INTC_INTREQ4 0x110
-# define INTC_INTREQ4_IREQUEST128_OFFSET 0
-# define INTC_INTREQ4_IREQUEST128_SIZE 1
-#define INTC_INTPR5 0x14
-# define INTC_INTPR5_INTLEV_OFFSET 30
-# define INTC_INTPR5_INTLEV_SIZE 2
-# define INTC_INTPR5_OFFSET_OFFSET 0
-# define INTC_INTPR5_OFFSET_SIZE 24
-#define INTC_INTREQ5 0x114
-# define INTC_INTREQ5_IREQUEST160_OFFSET 0
-# define INTC_INTREQ5_IREQUEST160_SIZE 1
-#define INTC_INTPR6 0x18
-# define INTC_INTPR6_INTLEV_OFFSET 30
-# define INTC_INTPR6_INTLEV_SIZE 2
-# define INTC_INTPR6_OFFSET_OFFSET 0
-# define INTC_INTPR6_OFFSET_SIZE 24
-#define INTC_INTREQ6 0x118
-# define INTC_INTREQ6_IREQUEST192_OFFSET 0
-# define INTC_INTREQ6_IREQUEST192_SIZE 1
-#define INTC_INTPR7 0x1c
-# define INTC_INTPR7_INTLEV_OFFSET 30
-# define INTC_INTPR7_INTLEV_SIZE 2
-# define INTC_INTPR7_OFFSET_OFFSET 0
-# define INTC_INTPR7_OFFSET_SIZE 24
-#define INTC_INTREQ7 0x11c
-# define INTC_INTREQ7_IREQUEST224_OFFSET 0
-# define INTC_INTREQ7_IREQUEST224_SIZE 1
-#define INTC_INTPR8 0x20
-# define INTC_INTPR8_INTLEV_OFFSET 30
-# define INTC_INTPR8_INTLEV_SIZE 2
-# define INTC_INTPR8_OFFSET_OFFSET 0
-# define INTC_INTPR8_OFFSET_SIZE 24
-#define INTC_INTREQ8 0x120
-# define INTC_INTREQ8_IREQUEST256_OFFSET 0
-# define INTC_INTREQ8_IREQUEST256_SIZE 1
-#define INTC_INTPR9 0x24
-# define INTC_INTPR9_INTLEV_OFFSET 30
-# define INTC_INTPR9_INTLEV_SIZE 2
-# define INTC_INTPR9_OFFSET_OFFSET 0
-# define INTC_INTPR9_OFFSET_SIZE 24
-#define INTC_INTREQ9 0x124
-# define INTC_INTREQ9_IREQUEST288_OFFSET 0
-# define INTC_INTREQ9_IREQUEST288_SIZE 1
-#define INTC_INTPR10 0x28
-# define INTC_INTPR10_INTLEV_OFFSET 30
-# define INTC_INTPR10_INTLEV_SIZE 2
-# define INTC_INTPR10_OFFSET_OFFSET 0
-# define INTC_INTPR10_OFFSET_SIZE 24
-#define INTC_INTREQ10 0x128
-# define INTC_INTREQ10_IREQUEST320_OFFSET 0
-# define INTC_INTREQ10_IREQUEST320_SIZE 1
-#define INTC_INTPR11 0x2c
-# define INTC_INTPR11_INTLEV_OFFSET 30
-# define INTC_INTPR11_INTLEV_SIZE 2
-# define INTC_INTPR11_OFFSET_OFFSET 0
-# define INTC_INTPR11_OFFSET_SIZE 24
-#define INTC_INTREQ11 0x12c
-# define INTC_INTREQ11_IREQUEST352_OFFSET 0
-# define INTC_INTREQ11_IREQUEST352_SIZE 1
-#define INTC_INTPR12 0x30
-# define INTC_INTPR12_INTLEV_OFFSET 30
-# define INTC_INTPR12_INTLEV_SIZE 2
-# define INTC_INTPR12_OFFSET_OFFSET 0
-# define INTC_INTPR12_OFFSET_SIZE 24
-#define INTC_INTREQ12 0x130
-# define INTC_INTREQ12_IREQUEST384_OFFSET 0
-# define INTC_INTREQ12_IREQUEST384_SIZE 1
-#define INTC_INTPR13 0x34
-# define INTC_INTPR13_INTLEV_OFFSET 30
-# define INTC_INTPR13_INTLEV_SIZE 2
-# define INTC_INTPR13_OFFSET_OFFSET 0
-# define INTC_INTPR13_OFFSET_SIZE 24
-#define INTC_INTREQ13 0x134
-# define INTC_INTREQ13_IREQUEST416_OFFSET 0
-# define INTC_INTREQ13_IREQUEST416_SIZE 1
-#define INTC_INTPR14 0x38
-# define INTC_INTPR14_INTLEV_OFFSET 30
-# define INTC_INTPR14_INTLEV_SIZE 2
-# define INTC_INTPR14_OFFSET_OFFSET 0
-# define INTC_INTPR14_OFFSET_SIZE 24
-#define INTC_INTREQ14 0x138
-# define INTC_INTREQ14_IREQUEST448_OFFSET 0
-# define INTC_INTREQ14_IREQUEST448_SIZE 1
-#define INTC_INTPR15 0x3c
-# define INTC_INTPR15_INTLEV_OFFSET 30
-# define INTC_INTPR15_INTLEV_SIZE 2
-# define INTC_INTPR15_OFFSET_OFFSET 0
-# define INTC_INTPR15_OFFSET_SIZE 24
-#define INTC_INTREQ15 0x13c
-# define INTC_INTREQ15_IREQUEST480_OFFSET 0
-# define INTC_INTREQ15_IREQUEST480_SIZE 1
-#define INTC_INTPR16 0x40
-# define INTC_INTPR16_INTLEV_OFFSET 30
-# define INTC_INTPR16_INTLEV_SIZE 2
-# define INTC_INTPR16_OFFSET_OFFSET 0
-# define INTC_INTPR16_OFFSET_SIZE 24
-#define INTC_INTREQ16 0x140
-# define INTC_INTREQ16_IREQUEST512_OFFSET 0
-# define INTC_INTREQ16_IREQUEST512_SIZE 1
-#define INTC_INTPR17 0x44
-# define INTC_INTPR17_INTLEV_OFFSET 30
-# define INTC_INTPR17_INTLEV_SIZE 2
-# define INTC_INTPR17_OFFSET_OFFSET 0
-# define INTC_INTPR17_OFFSET_SIZE 24
-#define INTC_INTREQ17 0x144
-# define INTC_INTREQ17_IREQUEST544_OFFSET 0
-# define INTC_INTREQ17_IREQUEST544_SIZE 1
-#define INTC_INTPR18 0x48
-# define INTC_INTPR18_INTLEV_OFFSET 30
-# define INTC_INTPR18_INTLEV_SIZE 2
-# define INTC_INTPR18_OFFSET_OFFSET 0
-# define INTC_INTPR18_OFFSET_SIZE 24
-#define INTC_INTREQ18 0x148
-# define INTC_INTREQ18_IREQUEST576_OFFSET 0
-# define INTC_INTREQ18_IREQUEST576_SIZE 1
-#define INTC_INTPR19 0x4c
-# define INTC_INTPR19_INTLEV_OFFSET 30
-# define INTC_INTPR19_INTLEV_SIZE 2
-# define INTC_INTPR19_OFFSET_OFFSET 0
-# define INTC_INTPR19_OFFSET_SIZE 24
-#define INTC_INTREQ19 0x14c
-# define INTC_INTREQ19_IREQUEST608_OFFSET 0
-# define INTC_INTREQ19_IREQUEST608_SIZE 1
-# define INTC_INTREQ19_IREQUEST609_OFFSET 1
-# define INTC_INTREQ19_IREQUEST609_SIZE 1
-# define INTC_INTREQ19_IREQUEST610_OFFSET 2
-# define INTC_INTREQ19_IREQUEST610_SIZE 1
-# define INTC_INTREQ19_IREQUEST611_OFFSET 3
-# define INTC_INTREQ19_IREQUEST611_SIZE 1
-#define INTC_INTPR20 0x50
-# define INTC_INTPR20_INTLEV_OFFSET 30
-# define INTC_INTPR20_INTLEV_SIZE 2
-# define INTC_INTPR20_OFFSET_OFFSET 0
-# define INTC_INTPR20_OFFSET_SIZE 24
-#define INTC_INTREQ20 0x150
-# define INTC_INTREQ20_IREQUEST640_OFFSET 0
-# define INTC_INTREQ20_IREQUEST640_SIZE 1
-#define INTC_INTPR21 0x54
-# define INTC_INTPR21_INTLEV_OFFSET 30
-# define INTC_INTPR21_INTLEV_SIZE 2
-# define INTC_INTPR21_OFFSET_OFFSET 0
-# define INTC_INTPR21_OFFSET_SIZE 24
-#define INTC_INTREQ21 0x154
-# define INTC_INTREQ21_IREQUEST672_OFFSET 0
-# define INTC_INTREQ21_IREQUEST672_SIZE 1
-#define INTC_INTPR22 0x58
-# define INTC_INTPR22_INTLEV_OFFSET 30
-# define INTC_INTPR22_INTLEV_SIZE 2
-# define INTC_INTPR22_OFFSET_OFFSET 0
-# define INTC_INTPR22_OFFSET_SIZE 24
-#define INTC_INTREQ22 0x158
-# define INTC_INTREQ22_IREQUEST704_OFFSET 0
-# define INTC_INTREQ22_IREQUEST704_SIZE 1
-# define INTC_INTREQ22_IREQUEST705_OFFSET 1
-# define INTC_INTREQ22_IREQUEST705_SIZE 1
-# define INTC_INTREQ22_IREQUEST706_OFFSET 2
-# define INTC_INTREQ22_IREQUEST706_SIZE 1
-#define INTC_INTPR23 0x5c
-# define INTC_INTPR23_INTLEV_OFFSET 30
-# define INTC_INTPR23_INTLEV_SIZE 2
-# define INTC_INTPR23_OFFSET_OFFSET 0
-# define INTC_INTPR23_OFFSET_SIZE 24
-#define INTC_INTREQ23 0x15c
-# define INTC_INTREQ23_IREQUEST736_OFFSET 0
-# define INTC_INTREQ23_IREQUEST736_SIZE 1
-# define INTC_INTREQ23_IREQUEST737_OFFSET 1
-# define INTC_INTREQ23_IREQUEST737_SIZE 1
-# define INTC_INTREQ23_IREQUEST738_OFFSET 2
-# define INTC_INTREQ23_IREQUEST738_SIZE 1
-#define INTC_INTPR24 0x60
-# define INTC_INTPR24_INTLEV_OFFSET 30
-# define INTC_INTPR24_INTLEV_SIZE 2
-# define INTC_INTPR24_OFFSET_OFFSET 0
-# define INTC_INTPR24_OFFSET_SIZE 24
-#define INTC_INTREQ24 0x160
-# define INTC_INTREQ24_IREQUEST768_OFFSET 0
-# define INTC_INTREQ24_IREQUEST768_SIZE 1
-#define INTC_INTPR25 0x64
-# define INTC_INTPR25_INTLEV_OFFSET 30
-# define INTC_INTPR25_INTLEV_SIZE 2
-# define INTC_INTPR25_OFFSET_OFFSET 0
-# define INTC_INTPR25_OFFSET_SIZE 24
-#define INTC_INTREQ25 0x164
-# define INTC_INTREQ25_IREQUEST800_OFFSET 0
-# define INTC_INTREQ25_IREQUEST800_SIZE 1
-#define INTC_INTPR26 0x68
-# define INTC_INTPR26_INTLEV_OFFSET 30
-# define INTC_INTPR26_INTLEV_SIZE 2
-# define INTC_INTPR26_OFFSET_OFFSET 0
-# define INTC_INTPR26_OFFSET_SIZE 24
-#define INTC_INTREQ26 0x168
-# define INTC_INTREQ26_IREQUEST832_OFFSET 0
-# define INTC_INTREQ26_IREQUEST832_SIZE 1
-#define INTC_INTPR27 0x6c
-# define INTC_INTPR27_INTLEV_OFFSET 30
-# define INTC_INTPR27_INTLEV_SIZE 2
-# define INTC_INTPR27_OFFSET_OFFSET 0
-# define INTC_INTPR27_OFFSET_SIZE 24
-#define INTC_INTREQ27 0x16c
-# define INTC_INTREQ27_IREQUEST864_OFFSET 0
-# define INTC_INTREQ27_IREQUEST864_SIZE 1
-#define INTC_INTPR28 0x70
-# define INTC_INTPR28_INTLEV_OFFSET 30
-# define INTC_INTPR28_INTLEV_SIZE 2
-# define INTC_INTPR28_OFFSET_OFFSET 0
-# define INTC_INTPR28_OFFSET_SIZE 24
-#define INTC_INTREQ28 0x170
-# define INTC_INTREQ28_IREQUEST896_OFFSET 0
-# define INTC_INTREQ28_IREQUEST896_SIZE 1
-#define INTC_INTPR29 0x74
-# define INTC_INTPR29_INTLEV_OFFSET 30
-# define INTC_INTPR29_INTLEV_SIZE 2
-# define INTC_INTPR29_OFFSET_OFFSET 0
-# define INTC_INTPR29_OFFSET_SIZE 24
-#define INTC_INTREQ29 0x174
-# define INTC_INTREQ29_IREQUEST928_OFFSET 0
-# define INTC_INTREQ29_IREQUEST928_SIZE 1
-#define INTC_INTPR30 0x78
-# define INTC_INTPR30_INTLEV_OFFSET 30
-# define INTC_INTPR30_INTLEV_SIZE 2
-# define INTC_INTPR30_OFFSET_OFFSET 0
-# define INTC_INTPR30_OFFSET_SIZE 24
-#define INTC_INTREQ30 0x178
-# define INTC_INTREQ30_IREQUEST960_OFFSET 0
-# define INTC_INTREQ30_IREQUEST960_SIZE 1
-#define INTC_INTPR31 0x7c
-# define INTC_INTPR31_INTLEV_OFFSET 30
-# define INTC_INTPR31_INTLEV_SIZE 2
-# define INTC_INTPR31_OFFSET_OFFSET 0
-# define INTC_INTPR31_OFFSET_SIZE 24
-#define INTC_INTREQ31 0x17c
-# define INTC_INTREQ31_IREQUEST992_OFFSET 0
-# define INTC_INTREQ31_IREQUEST992_SIZE 1
-#define INTC_INTPR32 0x80
-# define INTC_INTPR32_INTLEV_OFFSET 30
-# define INTC_INTPR32_INTLEV_SIZE 2
-# define INTC_INTPR32_OFFSET_OFFSET 0
-# define INTC_INTPR32_OFFSET_SIZE 24
-#define INTC_INTREQ32 0x180
-# define INTC_INTREQ32_IREQUEST1024_OFFSET 0
-# define INTC_INTREQ32_IREQUEST1024_SIZE 1
-#define INTC_INTCAUSE0 0x20c
-# define INTC_INTCAUSE0_CAUSEGRP_OFFSET 0
-# define INTC_INTCAUSE0_CAUSEGRP_SIZE 6
-#define INTC_INTCAUSE1 0x208
-# define INTC_INTCAUSE1_CAUSEGRP_OFFSET 0
-# define INTC_INTCAUSE1_CAUSEGRP_SIZE 6
-#define INTC_INTCAUSE2 0x204
-# define INTC_INTCAUSE2_CAUSEGRP_OFFSET 0
-# define INTC_INTCAUSE2_CAUSEGRP_SIZE 6
-#define INTC_INTCAUSE3 0x200
-# define INTC_INTCAUSE3_CAUSEGRP_OFFSET 0
-# define INTC_INTCAUSE3_CAUSEGRP_SIZE 6
-
-#define INTC_BIT(name) (1 << INTC_##name##_OFFSET)
-#define INTC_MKBF(name, value) (((value) & ((1 << INTC_##name##_SIZE) - 1)) << INTC_##name##_OFFSET)
-#define INTC_GETBF(name, value) (((value) >> INTC_##name##_OFFSET) & ((1 << INTC_##name##_SIZE) - 1))
-
-#define intc_readl(port,reg) \
- __raw_readl((port)->regs + INTC_##reg)
-#define intc_writel(port,reg,value) \
- __raw_writel((value), (port)->regs + INTC_##reg)
-
-#endif /* __ASM_AVR32_PERIHP_INTC_H__ */
diff --git a/arch/avr32/mach-at32ap/pdc.c b/arch/avr32/mach-at32ap/pdc.c
deleted file mode 100644
index 61ab15aae970..000000000000
--- a/arch/avr32/mach-at32ap/pdc.c
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (C) 2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-static int __init pdc_probe(struct platform_device *pdev)
-{
- struct clk *pclk, *hclk;
-
- pclk = clk_get(&pdev->dev, "pclk");
- if (IS_ERR(pclk)) {
- dev_err(&pdev->dev, "no pclk defined\n");
- return PTR_ERR(pclk);
- }
- hclk = clk_get(&pdev->dev, "hclk");
- if (IS_ERR(hclk)) {
- dev_err(&pdev->dev, "no hclk defined\n");
- clk_put(pclk);
- return PTR_ERR(hclk);
- }
-
- clk_enable(pclk);
- clk_enable(hclk);
-
- dev_info(&pdev->dev, "Atmel Peripheral DMA Controller enabled\n");
- return 0;
-}
-
-static struct platform_driver pdc_driver = {
- .driver = {
- .name = "pdc",
- },
-};
-
-static int __init pdc_init(void)
-{
- return platform_driver_probe(&pdc_driver, pdc_probe);
-}
-arch_initcall(pdc_init);
diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
deleted file mode 100644
index 7fae6ec7e8ec..000000000000
--- a/arch/avr32/mach-at32ap/pio.c
+++ /dev/null
@@ -1,470 +0,0 @@
-/*
- * Atmel PIO2 Port Multiplexer support
- *
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/clk.h>
-#include <linux/debugfs.h>
-#include <linux/export.h>
-#include <linux/fs.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-
-#include <asm/io.h>
-
-#include <mach/portmux.h>
-
-#include "pio.h"
-
-#define MAX_NR_PIO_DEVICES 8
-
-struct pio_device {
- struct gpio_chip chip;
- void __iomem *regs;
- const struct platform_device *pdev;
- struct clk *clk;
- u32 pinmux_mask;
- char name[8];
-};
-
-static struct pio_device pio_dev[MAX_NR_PIO_DEVICES];
-
-static struct pio_device *gpio_to_pio(unsigned int gpio)
-{
- struct pio_device *pio;
- unsigned int index;
-
- index = gpio >> 5;
- if (index >= MAX_NR_PIO_DEVICES)
- return NULL;
- pio = &pio_dev[index];
- if (!pio->regs)
- return NULL;
-
- return pio;
-}
-
-/* Pin multiplexing API */
-static DEFINE_SPINLOCK(pio_lock);
-
-void __init at32_select_periph(unsigned int port, u32 pin_mask,
- unsigned int periph, unsigned long flags)
-{
- struct pio_device *pio;
-
- /* assign and verify pio */
- pio = gpio_to_pio(port);
- if (unlikely(!pio)) {
- printk(KERN_WARNING "pio: invalid port %u\n", port);
- goto fail;
- }
-
- /* Test if any of the requested pins is already muxed */
- spin_lock(&pio_lock);
- if (unlikely(pio->pinmux_mask & pin_mask)) {
- printk(KERN_WARNING "%s: pin(s) busy (requested 0x%x, busy 0x%x)\n",
- pio->name, pin_mask, pio->pinmux_mask & pin_mask);
- spin_unlock(&pio_lock);
- goto fail;
- }
-
- pio->pinmux_mask |= pin_mask;
-
- /* enable pull ups */
- pio_writel(pio, PUER, pin_mask);
-
- /* select either peripheral A or B */
- if (periph)
- pio_writel(pio, BSR, pin_mask);
- else
- pio_writel(pio, ASR, pin_mask);
-
- /* enable peripheral control */
- pio_writel(pio, PDR, pin_mask);
-
- /* Disable pull ups if not requested. */
- if (!(flags & AT32_GPIOF_PULLUP))
- pio_writel(pio, PUDR, pin_mask);
-
- spin_unlock(&pio_lock);
-
- return;
-
-fail:
- dump_stack();
-}
-
-void __init at32_select_gpio(unsigned int pin, unsigned long flags)
-{
- struct pio_device *pio;
- unsigned int pin_index = pin & 0x1f;
- u32 mask = 1 << pin_index;
-
- pio = gpio_to_pio(pin);
- if (unlikely(!pio)) {
- printk("pio: invalid pin %u\n", pin);
- goto fail;
- }
-
- if (unlikely(test_and_set_bit(pin_index, &pio->pinmux_mask))) {
- printk("%s: pin %u is busy\n", pio->name, pin_index);
- goto fail;
- }
-
- if (flags & AT32_GPIOF_OUTPUT) {
- if (flags & AT32_GPIOF_HIGH)
- pio_writel(pio, SODR, mask);
- else
- pio_writel(pio, CODR, mask);
- if (flags & AT32_GPIOF_MULTIDRV)
- pio_writel(pio, MDER, mask);
- else
- pio_writel(pio, MDDR, mask);
- pio_writel(pio, PUDR, mask);
- pio_writel(pio, OER, mask);
- } else {
- if (flags & AT32_GPIOF_PULLUP)
- pio_writel(pio, PUER, mask);
- else
- pio_writel(pio, PUDR, mask);
- if (flags & AT32_GPIOF_DEGLITCH)
- pio_writel(pio, IFER, mask);
- else
- pio_writel(pio, IFDR, mask);
- pio_writel(pio, ODR, mask);
- }
-
- pio_writel(pio, PER, mask);
-
- return;
-
-fail:
- dump_stack();
-}
-
-/*
- * Undo a previous pin reservation. Will not affect the hardware
- * configuration.
- */
-void at32_deselect_pin(unsigned int pin)
-{
- struct pio_device *pio;
- unsigned int pin_index = pin & 0x1f;
-
- pio = gpio_to_pio(pin);
- if (unlikely(!pio)) {
- printk("pio: invalid pin %u\n", pin);
- dump_stack();
- return;
- }
-
- clear_bit(pin_index, &pio->pinmux_mask);
-}
-
-/* Reserve a pin, preventing anyone else from changing its configuration. */
-void __init at32_reserve_pin(unsigned int port, u32 pin_mask)
-{
- struct pio_device *pio;
-
- /* assign and verify pio */
- pio = gpio_to_pio(port);
- if (unlikely(!pio)) {
- printk(KERN_WARNING "pio: invalid port %u\n", port);
- goto fail;
- }
-
- /* Test if any of the requested pins is already muxed */
- spin_lock(&pio_lock);
- if (unlikely(pio->pinmux_mask & pin_mask)) {
- printk(KERN_WARNING "%s: pin(s) busy (req. 0x%x, busy 0x%x)\n",
- pio->name, pin_mask, pio->pinmux_mask & pin_mask);
- spin_unlock(&pio_lock);
- goto fail;
- }
-
- /* Reserve pins */
- pio->pinmux_mask |= pin_mask;
- spin_unlock(&pio_lock);
- return;
-
-fail:
- dump_stack();
-}
-
-/*--------------------------------------------------------------------------*/
-
-/* GPIO API */
-
-static int direction_input(struct gpio_chip *chip, unsigned offset)
-{
- struct pio_device *pio = gpiochip_get_data(chip);
- u32 mask = 1 << offset;
-
- if (!(pio_readl(pio, PSR) & mask))
- return -EINVAL;
-
- pio_writel(pio, ODR, mask);
- return 0;
-}
-
-static int gpio_get(struct gpio_chip *chip, unsigned offset)
-{
- struct pio_device *pio = gpiochip_get_data(chip);
-
- return (pio_readl(pio, PDSR) >> offset) & 1;
-}
-
-static void gpio_set(struct gpio_chip *chip, unsigned offset, int value);
-
-static int direction_output(struct gpio_chip *chip, unsigned offset, int value)
-{
- struct pio_device *pio = gpiochip_get_data(chip);
- u32 mask = 1 << offset;
-
- if (!(pio_readl(pio, PSR) & mask))
- return -EINVAL;
-
- gpio_set(chip, offset, value);
- pio_writel(pio, OER, mask);
- return 0;
-}
-
-static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
-{
- struct pio_device *pio = gpiochip_get_data(chip);
- u32 mask = 1 << offset;
-
- if (value)
- pio_writel(pio, SODR, mask);
- else
- pio_writel(pio, CODR, mask);
-}
-
-/*--------------------------------------------------------------------------*/
-
-/* GPIO IRQ support */
-
-static void gpio_irq_mask(struct irq_data *d)
-{
- unsigned gpio = irq_to_gpio(d->irq);
- struct pio_device *pio = &pio_dev[gpio >> 5];
-
- pio_writel(pio, IDR, 1 << (gpio & 0x1f));
-}
-
-static void gpio_irq_unmask(struct irq_data *d)
-{
- unsigned gpio = irq_to_gpio(d->irq);
- struct pio_device *pio = &pio_dev[gpio >> 5];
-
- pio_writel(pio, IER, 1 << (gpio & 0x1f));
-}
-
-static int gpio_irq_type(struct irq_data *d, unsigned type)
-{
- if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE)
- return -EINVAL;
-
- return 0;
-}
-
-static struct irq_chip gpio_irqchip = {
- .name = "gpio",
- .irq_mask = gpio_irq_mask,
- .irq_unmask = gpio_irq_unmask,
- .irq_set_type = gpio_irq_type,
-};
-
-static void gpio_irq_handler(struct irq_desc *desc)
-{
- struct pio_device *pio = irq_desc_get_chip_data(desc);
- unsigned gpio_irq;
-
- gpio_irq = (unsigned) irq_desc_get_handler_data(desc);
- for (;;) {
- u32 isr;
-
- /* ack pending GPIO interrupts */
- isr = pio_readl(pio, ISR) & pio_readl(pio, IMR);
- if (!isr)
- break;
- do {
- int i;
-
- i = ffs(isr) - 1;
- isr &= ~(1 << i);
-
- i += gpio_irq;
- generic_handle_irq(i);
- } while (isr);
- }
-}
-
-static void __init
-gpio_irq_setup(struct pio_device *pio, int irq, int gpio_irq)
-{
- unsigned i;
-
- irq_set_chip_data(irq, pio);
-
- for (i = 0; i < 32; i++, gpio_irq++) {
- irq_set_chip_data(gpio_irq, pio);
- irq_set_chip_and_handler(gpio_irq, &gpio_irqchip,
- handle_simple_irq);
- }
-
- irq_set_chained_handler_and_data(irq, gpio_irq_handler,
- (void *)gpio_irq);
-}
-
-/*--------------------------------------------------------------------------*/
-
-#ifdef CONFIG_DEBUG_FS
-
-#include <linux/seq_file.h>
-
-/*
- * This shows more info than the generic gpio dump code:
- * pullups, deglitching, open drain drive.
- */
-static void pio_bank_show(struct seq_file *s, struct gpio_chip *chip)
-{
- struct pio_device *pio = gpiochip_get_data(chip);
- u32 psr, osr, imr, pdsr, pusr, ifsr, mdsr;
- unsigned i;
- u32 mask;
- char bank;
-
- psr = pio_readl(pio, PSR);
- osr = pio_readl(pio, OSR);
- imr = pio_readl(pio, IMR);
- pdsr = pio_readl(pio, PDSR);
- pusr = pio_readl(pio, PUSR);
- ifsr = pio_readl(pio, IFSR);
- mdsr = pio_readl(pio, MDSR);
-
- bank = 'A' + pio->pdev->id;
-
- for (i = 0, mask = 1; i < 32; i++, mask <<= 1) {
- const char *label;
-
- label = gpiochip_is_requested(chip, i);
- if (!label && (imr & mask))
- label = "[irq]";
- if (!label)
- continue;
-
- seq_printf(s, " gpio-%-3d P%c%-2d (%-12s) %s %s %s",
- chip->base + i, bank, i,
- label,
- (osr & mask) ? "out" : "in ",
- (mask & pdsr) ? "hi" : "lo",
- (mask & pusr) ? " " : "up");
- if (ifsr & mask)
- seq_puts(s, " deglitch");
- if ((osr & mdsr) & mask)
- seq_puts(s, " open-drain");
- if (imr & mask)
- seq_printf(s, " irq-%d edge-both",
- gpio_to_irq(chip->base + i));
- seq_putc(s, '\n');
- }
-}
-
-#else
-#define pio_bank_show NULL
-#endif
-
-
-/*--------------------------------------------------------------------------*/
-
-static int __init pio_probe(struct platform_device *pdev)
-{
- struct pio_device *pio = NULL;
- int irq = platform_get_irq(pdev, 0);
- int gpio_irq_base = GPIO_IRQ_BASE + pdev->id * 32;
-
- BUG_ON(pdev->id >= MAX_NR_PIO_DEVICES);
- pio = &pio_dev[pdev->id];
- BUG_ON(!pio->regs);
-
- pio->chip.label = pio->name;
- pio->chip.base = pdev->id * 32;
- pio->chip.ngpio = 32;
- pio->chip.parent = &pdev->dev;
- pio->chip.owner = THIS_MODULE;
-
- pio->chip.direction_input = direction_input;
- pio->chip.get = gpio_get;
- pio->chip.direction_output = direction_output;
- pio->chip.set = gpio_set;
- pio->chip.dbg_show = pio_bank_show;
-
- gpiochip_add_data(&pio->chip, pio);
-
- gpio_irq_setup(pio, irq, gpio_irq_base);
-
- platform_set_drvdata(pdev, pio);
-
- printk(KERN_DEBUG "%s: base 0x%p, irq %d chains %d..%d\n",
- pio->name, pio->regs, irq, gpio_irq_base, gpio_irq_base + 31);
-
- return 0;
-}
-
-static struct platform_driver pio_driver = {
- .driver = {
- .name = "pio",
- },
-};
-
-static int __init pio_init(void)
-{
- return platform_driver_probe(&pio_driver, pio_probe);
-}
-postcore_initcall(pio_init);
-
-void __init at32_init_pio(struct platform_device *pdev)
-{
- struct resource *regs;
- struct pio_device *pio;
-
- if (pdev->id >= MAX_NR_PIO_DEVICES) {
- dev_err(&pdev->dev, "only %d PIO devices supported\n",
- MAX_NR_PIO_DEVICES);
- return;
- }
-
- pio = &pio_dev[pdev->id];
- snprintf(pio->name, sizeof(pio->name), "pio%d", pdev->id);
-
- regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!regs) {
- dev_err(&pdev->dev, "no mmio resource defined\n");
- return;
- }
-
- pio->clk = clk_get(&pdev->dev, "mck");
- if (IS_ERR(pio->clk))
- /*
- * This is a fatal error, but if we continue we might
- * be so lucky that we manage to initialize the
- * console and display this message...
- */
- dev_err(&pdev->dev, "no mck clock defined\n");
- else
- clk_enable(pio->clk);
-
- pio->pdev = pdev;
- pio->regs = ioremap(regs->start, resource_size(regs));
-
- /* start with irqs disabled and acked */
- pio_writel(pio, IDR, ~0UL);
- (void) pio_readl(pio, ISR);
-}
diff --git a/arch/avr32/mach-at32ap/pio.h b/arch/avr32/mach-at32ap/pio.h
deleted file mode 100644
index 9484dfcc08f2..000000000000
--- a/arch/avr32/mach-at32ap/pio.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Atmel PIO2 Port Multiplexer support
- *
- * Copyright (C) 2004-2006 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef __ARCH_AVR32_AT32AP_PIO_H__
-#define __ARCH_AVR32_AT32AP_PIO_H__
-
-/* PIO register offsets */
-#define PIO_PER 0x0000
-#define PIO_PDR 0x0004
-#define PIO_PSR 0x0008
-#define PIO_OER 0x0010
-#define PIO_ODR 0x0014
-#define PIO_OSR 0x0018
-#define PIO_IFER 0x0020
-#define PIO_IFDR 0x0024
-#define PIO_IFSR 0x0028
-#define PIO_SODR 0x0030
-#define PIO_CODR 0x0034
-#define PIO_ODSR 0x0038
-#define PIO_PDSR 0x003c
-#define PIO_IER 0x0040
-#define PIO_IDR 0x0044
-#define PIO_IMR 0x0048
-#define PIO_ISR 0x004c
-#define PIO_MDER 0x0050
-#define PIO_MDDR 0x0054
-#define PIO_MDSR 0x0058
-#define PIO_PUDR 0x0060
-#define PIO_PUER 0x0064
-#define PIO_PUSR 0x0068
-#define PIO_ASR 0x0070
-#define PIO_BSR 0x0074
-#define PIO_ABSR 0x0078
-#define PIO_OWER 0x00a0
-#define PIO_OWDR 0x00a4
-#define PIO_OWSR 0x00a8
-
-/* Bitfields in PER */
-
-/* Bitfields in PDR */
-
-/* Bitfields in PSR */
-
-/* Bitfields in OER */
-
-/* Bitfields in ODR */
-
-/* Bitfields in OSR */
-
-/* Bitfields in IFER */
-
-/* Bitfields in IFDR */
-
-/* Bitfields in IFSR */
-
-/* Bitfields in SODR */
-
-/* Bitfields in CODR */
-
-/* Bitfields in ODSR */
-
-/* Bitfields in PDSR */
-
-/* Bitfields in IER */
-
-/* Bitfields in IDR */
-
-/* Bitfields in IMR */
-
-/* Bitfields in ISR */
-
-/* Bitfields in MDER */
-
-/* Bitfields in MDDR */
-
-/* Bitfields in MDSR */
-
-/* Bitfields in PUDR */
-
-/* Bitfields in PUER */
-
-/* Bitfields in PUSR */
-
-/* Bitfields in ASR */
-
-/* Bitfields in BSR */
-
-/* Bitfields in ABSR */
-#define PIO_P0_OFFSET 0
-#define PIO_P0_SIZE 1
-#define PIO_P1_OFFSET 1
-#define PIO_P1_SIZE 1
-#define PIO_P2_OFFSET 2
-#define PIO_P2_SIZE 1
-#define PIO_P3_OFFSET 3
-#define PIO_P3_SIZE 1
-#define PIO_P4_OFFSET 4
-#define PIO_P4_SIZE 1
-#define PIO_P5_OFFSET 5
-#define PIO_P5_SIZE 1
-#define PIO_P6_OFFSET 6
-#define PIO_P6_SIZE 1
-#define PIO_P7_OFFSET 7
-#define PIO_P7_SIZE 1
-#define PIO_P8_OFFSET 8
-#define PIO_P8_SIZE 1
-#define PIO_P9_OFFSET 9
-#define PIO_P9_SIZE 1
-#define PIO_P10_OFFSET 10
-#define PIO_P10_SIZE 1
-#define PIO_P11_OFFSET 11
-#define PIO_P11_SIZE 1
-#define PIO_P12_OFFSET 12
-#define PIO_P12_SIZE 1
-#define PIO_P13_OFFSET 13
-#define PIO_P13_SIZE 1
-#define PIO_P14_OFFSET 14
-#define PIO_P14_SIZE 1
-#define PIO_P15_OFFSET 15
-#define PIO_P15_SIZE 1
-#define PIO_P16_OFFSET 16
-#define PIO_P16_SIZE 1
-#define PIO_P17_OFFSET 17
-#define PIO_P17_SIZE 1
-#define PIO_P18_OFFSET 18
-#define PIO_P18_SIZE 1
-#define PIO_P19_OFFSET 19
-#define PIO_P19_SIZE 1
-#define PIO_P20_OFFSET 20
-#define PIO_P20_SIZE 1
-#define PIO_P21_OFFSET 21
-#define PIO_P21_SIZE 1
-#define PIO_P22_OFFSET 22
-#define PIO_P22_SIZE 1
-#define PIO_P23_OFFSET 23
-#define PIO_P23_SIZE 1
-#define PIO_P24_OFFSET 24
-#define PIO_P24_SIZE 1
-#define PIO_P25_OFFSET 25
-#define PIO_P25_SIZE 1
-#define PIO_P26_OFFSET 26
-#define PIO_P26_SIZE 1
-#define PIO_P27_OFFSET 27
-#define PIO_P27_SIZE 1
-#define PIO_P28_OFFSET 28
-#define PIO_P28_SIZE 1
-#define PIO_P29_OFFSET 29
-#define PIO_P29_SIZE 1
-#define PIO_P30_OFFSET 30
-#define PIO_P30_SIZE 1
-#define PIO_P31_OFFSET 31
-#define PIO_P31_SIZE 1
-
-/* Bitfields in OWER */
-
-/* Bitfields in OWDR */
-
-/* Bitfields in OWSR */
-
-/* Bit manipulation macros */
-#define PIO_BIT(name) (1 << PIO_##name##_OFFSET)
-#define PIO_BF(name,value) (((value) & ((1 << PIO_##name##_SIZE) - 1)) << PIO_##name##_OFFSET)
-#define PIO_BFEXT(name,value) (((value) >> PIO_##name##_OFFSET) & ((1 << PIO_##name##_SIZE) - 1))
-#define PIO_BFINS(name,value,old) (((old) & ~(((1 << PIO_##name##_SIZE) - 1) << PIO_##name##_OFFSET)) | PIO_BF(name,value))
-
-/* Register access macros */
-#define pio_readl(port,reg) \
- __raw_readl((port)->regs + PIO_##reg)
-#define pio_writel(port,reg,value) \
- __raw_writel((value), (port)->regs + PIO_##reg)
-
-void at32_init_pio(struct platform_device *pdev);
-
-#endif /* __ARCH_AVR32_AT32AP_PIO_H__ */
diff --git a/arch/avr32/mach-at32ap/pm-at32ap700x.S b/arch/avr32/mach-at32ap/pm-at32ap700x.S
deleted file mode 100644
index 1c8e4e6bff03..000000000000
--- a/arch/avr32/mach-at32ap/pm-at32ap700x.S
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * Low-level Power Management code.
- *
- * Copyright (C) 2008 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <asm/asm.h>
-#include <asm/asm-offsets.h>
-#include <asm/thread_info.h>
-#include <mach/pm.h>
-
-#include "pm.h"
-#include "sdramc.h"
-
-/* Same as 0xfff00000 but fits in a 21 bit signed immediate */
-#define PM_BASE -0x100000
-
- /* Keep this close to the irq handlers */
- .section .irq.text, "ax", @progbits
-
- /*
- * void cpu_enter_idle(void)
- *
- * Put the CPU into "idle" mode, in which it will consume
- * significantly less power.
- *
- * If an interrupt comes along in the window between
- * unmask_interrupts and the sleep instruction below, the
- * interrupt code will adjust the return address so that we
- * never execute the sleep instruction. This is required
- * because the AP7000 doesn't unmask interrupts when entering
- * sleep modes; later CPUs may not need this workaround.
- */
- .global cpu_enter_idle
- .type cpu_enter_idle, @function
-cpu_enter_idle:
- mask_interrupts
- get_thread_info r8
- ld.w r9, r8[TI_flags]
- bld r9, TIF_NEED_RESCHED
- brcs .Lret_from_sleep
- sbr r9, TIF_CPU_GOING_TO_SLEEP
- st.w r8[TI_flags], r9
- unmask_interrupts
- sleep CPU_SLEEP_IDLE
- .size cpu_enter_idle, . - cpu_enter_idle
-
- /*
- * Common return path for PM functions that don't run from
- * SRAM.
- */
- .global cpu_idle_skip_sleep
- .type cpu_idle_skip_sleep, @function
-cpu_idle_skip_sleep:
- mask_interrupts
- ld.w r9, r8[TI_flags]
- cbr r9, TIF_CPU_GOING_TO_SLEEP
- st.w r8[TI_flags], r9
-.Lret_from_sleep:
- unmask_interrupts
- retal r12
- .size cpu_idle_skip_sleep, . - cpu_idle_skip_sleep
-
-#ifdef CONFIG_PM
- .section .init.text, "ax", @progbits
-
- .global pm_exception
- .type pm_exception, @function
-pm_exception:
- /*
- * Exceptions are masked when we switch to this handler, so
- * we'll only get "unrecoverable" exceptions (offset 0.)
- */
- sub r12, pc, . - .Lpanic_msg
- lddpc pc, .Lpanic_addr
-
- .align 2
-.Lpanic_addr:
- .long panic
-.Lpanic_msg:
- .asciz "Unrecoverable exception during suspend\n"
- .size pm_exception, . - pm_exception
-
- .global pm_irq0
- .type pm_irq0, @function
-pm_irq0:
- /* Disable interrupts and return after the sleep instruction */
- mfsr r9, SYSREG_RSR_INT0
- mtsr SYSREG_RAR_INT0, r8
- sbr r9, SYSREG_GM_OFFSET
- mtsr SYSREG_RSR_INT0, r9
- rete
-
- /*
- * void cpu_enter_standby(unsigned long sdramc_base)
- *
- * Enter PM_SUSPEND_STANDBY mode. At this point, all drivers
- * are suspended and interrupts are disabled. Interrupts
- * marked as 'wakeup' event sources may still come along and
- * get us out of here.
- *
- * The SDRAM will be put into self-refresh mode (which does
- * not require a clock from the CPU), and the CPU will be put
- * into "frozen" mode (HSB bus stopped). The SDRAM controller
- * will automatically bring the SDRAM into normal mode on the
- * first access, and the power manager will automatically
- * start the HSB and CPU clocks upon a wakeup event.
- *
- * This code uses the same "skip sleep" technique as above.
- * It is very important that we jump directly to
- * cpu_after_sleep after the sleep instruction since that's
- * where we'll end up if the interrupt handler decides that we
- * need to skip the sleep instruction.
- */
- .global pm_standby
- .type pm_standby, @function
-pm_standby:
- /*
- * interrupts are already masked at this point, and EVBA
- * points to pm_exception above.
- */
- ld.w r10, r12[SDRAMC_LPR]
- sub r8, pc, . - 1f /* return address for irq handler */
- mov r11, SDRAMC_LPR_LPCB_SELF_RFR
- bfins r10, r11, 0, 2 /* LPCB <- self Refresh */
- sync 0 /* flush write buffer */
- st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
- ld.w r11, r12[SDRAMC_LPR]
- unmask_interrupts
- sleep CPU_SLEEP_FROZEN
-1: mask_interrupts
- retal r12
- .size pm_standby, . - pm_standby
-
- .global pm_suspend_to_ram
- .type pm_suspend_to_ram, @function
-pm_suspend_to_ram:
- /*
- * interrupts are already masked at this point, and EVBA
- * points to pm_exception above.
- */
- mov r11, 0
- cache r11[2], 8 /* clean all dcache lines */
- sync 0 /* flush write buffer */
- ld.w r10, r12[SDRAMC_LPR]
- sub r8, pc, . - 1f /* return address for irq handler */
- mov r11, SDRAMC_LPR_LPCB_SELF_RFR
- bfins r10, r11, 0, 2 /* LPCB <- self refresh */
- st.w r12[SDRAMC_LPR], r10 /* put SDRAM in self-refresh mode */
- ld.w r11, r12[SDRAMC_LPR]
-
- unmask_interrupts
- sleep CPU_SLEEP_STOP
-1: mask_interrupts
-
- retal r12
- .size pm_suspend_to_ram, . - pm_suspend_to_ram
-
- .global pm_sram_end
- .type pm_sram_end, @function
-pm_sram_end:
- .size pm_sram_end, 0
-
-#endif /* CONFIG_PM */
diff --git a/arch/avr32/mach-at32ap/pm.c b/arch/avr32/mach-at32ap/pm.c
deleted file mode 100644
index db190842b80c..000000000000
--- a/arch/avr32/mach-at32ap/pm.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * AVR32 AP Power Management
- *
- * Copyright (C) 2008 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- */
-#include <linux/io.h>
-#include <linux/suspend.h>
-#include <linux/vmalloc.h>
-
-#include <asm/cacheflush.h>
-#include <asm/sysreg.h>
-
-#include <mach/chip.h>
-#include <mach/pm.h>
-#include <mach/sram.h>
-
-#include "sdramc.h"
-
-#define SRAM_PAGE_FLAGS (SYSREG_BIT(TLBELO_D) | SYSREG_BF(SZ, 1) \
- | SYSREG_BF(AP, 3) | SYSREG_BIT(G))
-
-
-static unsigned long pm_sram_start;
-static size_t pm_sram_size;
-static struct vm_struct *pm_sram_area;
-
-static void (*avr32_pm_enter_standby)(unsigned long sdramc_base);
-static void (*avr32_pm_enter_str)(unsigned long sdramc_base);
-
-/*
- * Must be called with interrupts disabled. Exceptions will be masked
- * on return (i.e. all exceptions will be "unrecoverable".)
- */
-static void *avr32_pm_map_sram(void)
-{
- unsigned long vaddr;
- unsigned long page_addr;
- u32 tlbehi;
- u32 mmucr;
-
- vaddr = (unsigned long)pm_sram_area->addr;
- page_addr = pm_sram_start & PAGE_MASK;
-
- /*
- * Mask exceptions and grab the first TLB entry. We won't be
- * needing it while sleeping.
- */
- asm volatile("ssrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
-
- mmucr = sysreg_read(MMUCR);
- tlbehi = sysreg_read(TLBEHI);
- sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
-
- tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
- tlbehi |= vaddr & PAGE_MASK;
- tlbehi |= SYSREG_BIT(TLBEHI_V);
-
- sysreg_write(TLBELO, page_addr | SRAM_PAGE_FLAGS);
- sysreg_write(TLBEHI, tlbehi);
- __builtin_tlbw();
-
- return (void *)(vaddr + pm_sram_start - page_addr);
-}
-
-/*
- * Must be called with interrupts disabled. Exceptions will be
- * unmasked on return.
- */
-static void avr32_pm_unmap_sram(void)
-{
- u32 mmucr;
- u32 tlbehi;
- u32 tlbarlo;
-
- /* Going to update TLB entry at index 0 */
- mmucr = sysreg_read(MMUCR);
- tlbehi = sysreg_read(TLBEHI);
- sysreg_write(MMUCR, SYSREG_BFINS(DRP, 0, mmucr));
-
- /* Clear the "valid" bit */
- tlbehi = SYSREG_BF(ASID, SYSREG_BFEXT(ASID, tlbehi));
- sysreg_write(TLBEHI, tlbehi);
-
- /* Mark it as "not accessed" */
- tlbarlo = sysreg_read(TLBARLO);
- sysreg_write(TLBARLO, tlbarlo | 0x80000000U);
-
- /* Update the TLB */
- __builtin_tlbw();
-
- /* Unmask exceptions */
- asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET) : "memory");
-}
-
-static int avr32_pm_valid_state(suspend_state_t state)
-{
- switch (state) {
- case PM_SUSPEND_ON:
- case PM_SUSPEND_STANDBY:
- case PM_SUSPEND_MEM:
- return 1;
-
- default:
- return 0;
- }
-}
-
-static int avr32_pm_enter(suspend_state_t state)
-{
- u32 lpr_saved;
- u32 evba_saved;
- void *sram;
-
- switch (state) {
- case PM_SUSPEND_STANDBY:
- sram = avr32_pm_map_sram();
-
- /* Switch to in-sram exception handlers */
- evba_saved = sysreg_read(EVBA);
- sysreg_write(EVBA, (unsigned long)sram);
-
- /*
- * Save the LPR register so that we can re-enable
- * SDRAM Low Power mode on resume.
- */
- lpr_saved = sdramc_readl(LPR);
- pr_debug("%s: Entering standby...\n", __func__);
- avr32_pm_enter_standby(SDRAMC_BASE);
- sdramc_writel(LPR, lpr_saved);
-
- /* Switch back to regular exception handlers */
- sysreg_write(EVBA, evba_saved);
-
- avr32_pm_unmap_sram();
- break;
-
- case PM_SUSPEND_MEM:
- sram = avr32_pm_map_sram();
-
- /* Switch to in-sram exception handlers */
- evba_saved = sysreg_read(EVBA);
- sysreg_write(EVBA, (unsigned long)sram);
-
- /*
- * Save the LPR register so that we can re-enable
- * SDRAM Low Power mode on resume.
- */
- lpr_saved = sdramc_readl(LPR);
- pr_debug("%s: Entering suspend-to-ram...\n", __func__);
- avr32_pm_enter_str(SDRAMC_BASE);
- sdramc_writel(LPR, lpr_saved);
-
- /* Switch back to regular exception handlers */
- sysreg_write(EVBA, evba_saved);
-
- avr32_pm_unmap_sram();
- break;
-
- case PM_SUSPEND_ON:
- pr_debug("%s: Entering idle...\n", __func__);
- cpu_enter_idle();
- break;
-
- default:
- pr_debug("%s: Invalid suspend state %d\n", __func__, state);
- goto out;
- }
-
- pr_debug("%s: wakeup\n", __func__);
-
-out:
- return 0;
-}
-
-static const struct platform_suspend_ops avr32_pm_ops = {
- .valid = avr32_pm_valid_state,
- .enter = avr32_pm_enter,
-};
-
-static unsigned long __init avr32_pm_offset(void *symbol)
-{
- extern u8 pm_exception[];
-
- return (unsigned long)symbol - (unsigned long)pm_exception;
-}
-
-static int __init avr32_pm_init(void)
-{
- extern u8 pm_exception[];
- extern u8 pm_irq0[];
- extern u8 pm_standby[];
- extern u8 pm_suspend_to_ram[];
- extern u8 pm_sram_end[];
- void *dst;
-
- /*
- * To keep things simple, we depend on not needing more than a
- * single page.
- */
- pm_sram_size = avr32_pm_offset(pm_sram_end);
- if (pm_sram_size > PAGE_SIZE)
- goto err;
-
- pm_sram_start = sram_alloc(pm_sram_size);
- if (!pm_sram_start)
- goto err_alloc_sram;
-
- /* Grab a virtual area we can use later on. */
- pm_sram_area = get_vm_area(pm_sram_size, VM_IOREMAP);
- if (!pm_sram_area)
- goto err_vm_area;
- pm_sram_area->phys_addr = pm_sram_start;
-
- local_irq_disable();
- dst = avr32_pm_map_sram();
- memcpy(dst, pm_exception, pm_sram_size);
- flush_dcache_region(dst, pm_sram_size);
- invalidate_icache_region(dst, pm_sram_size);
- avr32_pm_unmap_sram();
- local_irq_enable();
-
- avr32_pm_enter_standby = dst + avr32_pm_offset(pm_standby);
- avr32_pm_enter_str = dst + avr32_pm_offset(pm_suspend_to_ram);
- intc_set_suspend_handler(avr32_pm_offset(pm_irq0));
-
- suspend_set_ops(&avr32_pm_ops);
-
- printk("AVR32 AP Power Management enabled\n");
-
- return 0;
-
-err_vm_area:
- sram_free(pm_sram_start, pm_sram_size);
-err_alloc_sram:
-err:
- pr_err("AVR32 Power Management initialization failed\n");
- return -ENOMEM;
-}
-arch_initcall(avr32_pm_init);
diff --git a/arch/avr32/mach-at32ap/pm.h b/arch/avr32/mach-at32ap/pm.h
deleted file mode 100644
index 532a3732c214..000000000000
--- a/arch/avr32/mach-at32ap/pm.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Register definitions for the Power Manager (PM)
- */
-#ifndef __ARCH_AVR32_MACH_AT32AP_PM_H__
-#define __ARCH_AVR32_MACH_AT32AP_PM_H__
-
-/* PM register offsets */
-#define PM_MCCTRL 0x0000
-#define PM_CKSEL 0x0004
-#define PM_CPU_MASK 0x0008
-#define PM_HSB_MASK 0x000c
-#define PM_PBA_MASK 0x0010
-#define PM_PBB_MASK 0x0014
-#define PM_PLL0 0x0020
-#define PM_PLL1 0x0024
-#define PM_IER 0x0040
-#define PM_IDR 0x0044
-#define PM_IMR 0x0048
-#define PM_ISR 0x004c
-#define PM_ICR 0x0050
-#define PM_GCCTRL(x) (0x0060 + 4 * (x))
-#define PM_RCAUSE 0x00c0
-
-/* Bitfields in CKSEL */
-#define PM_CPUSEL_OFFSET 0
-#define PM_CPUSEL_SIZE 3
-#define PM_CPUDIV_OFFSET 7
-#define PM_CPUDIV_SIZE 1
-#define PM_HSBSEL_OFFSET 8
-#define PM_HSBSEL_SIZE 3
-#define PM_HSBDIV_OFFSET 15
-#define PM_HSBDIV_SIZE 1
-#define PM_PBASEL_OFFSET 16
-#define PM_PBASEL_SIZE 3
-#define PM_PBADIV_OFFSET 23
-#define PM_PBADIV_SIZE 1
-#define PM_PBBSEL_OFFSET 24
-#define PM_PBBSEL_SIZE 3
-#define PM_PBBDIV_OFFSET 31
-#define PM_PBBDIV_SIZE 1
-
-/* Bitfields in PLL0 */
-#define PM_PLLEN_OFFSET 0
-#define PM_PLLEN_SIZE 1
-#define PM_PLLOSC_OFFSET 1
-#define PM_PLLOSC_SIZE 1
-#define PM_PLLOPT_OFFSET 2
-#define PM_PLLOPT_SIZE 3
-#define PM_PLLDIV_OFFSET 8
-#define PM_PLLDIV_SIZE 8
-#define PM_PLLMUL_OFFSET 16
-#define PM_PLLMUL_SIZE 8
-#define PM_PLLCOUNT_OFFSET 24
-#define PM_PLLCOUNT_SIZE 6
-#define PM_PLLTEST_OFFSET 31
-#define PM_PLLTEST_SIZE 1
-
-/* Bitfields in ICR */
-#define PM_LOCK0_OFFSET 0
-#define PM_LOCK0_SIZE 1
-#define PM_LOCK1_OFFSET 1
-#define PM_LOCK1_SIZE 1
-#define PM_WAKE_OFFSET 2
-#define PM_WAKE_SIZE 1
-#define PM_CKRDY_OFFSET 5
-#define PM_CKRDY_SIZE 1
-#define PM_MSKRDY_OFFSET 6
-#define PM_MSKRDY_SIZE 1
-
-/* Bitfields in GCCTRL0 */
-#define PM_OSCSEL_OFFSET 0
-#define PM_OSCSEL_SIZE 1
-#define PM_PLLSEL_OFFSET 1
-#define PM_PLLSEL_SIZE 1
-#define PM_CEN_OFFSET 2
-#define PM_CEN_SIZE 1
-#define PM_DIVEN_OFFSET 4
-#define PM_DIVEN_SIZE 1
-#define PM_DIV_OFFSET 8
-#define PM_DIV_SIZE 8
-
-/* Bitfields in RCAUSE */
-#define PM_POR_OFFSET 0
-#define PM_POR_SIZE 1
-#define PM_EXT_OFFSET 2
-#define PM_EXT_SIZE 1
-#define PM_WDT_OFFSET 3
-#define PM_WDT_SIZE 1
-#define PM_NTAE_OFFSET 4
-#define PM_NTAE_SIZE 1
-
-/* Bit manipulation macros */
-#define PM_BIT(name) \
- (1 << PM_##name##_OFFSET)
-#define PM_BF(name,value) \
- (((value) & ((1 << PM_##name##_SIZE) - 1)) \
- << PM_##name##_OFFSET)
-#define PM_BFEXT(name,value) \
- (((value) >> PM_##name##_OFFSET) \
- & ((1 << PM_##name##_SIZE) - 1))
-#define PM_BFINS(name,value,old)\
- (((old) & ~(((1 << PM_##name##_SIZE) - 1) \
- << PM_##name##_OFFSET)) \
- | PM_BF(name,value))
-
-/* Register access macros */
-#define pm_readl(reg) \
- __raw_readl((void __iomem __force *)PM_BASE + PM_##reg)
-#define pm_writel(reg,value) \
- __raw_writel((value), (void __iomem __force *)PM_BASE + PM_##reg)
-
-#endif /* __ARCH_AVR32_MACH_AT32AP_PM_H__ */
diff --git a/arch/avr32/mach-at32ap/sdramc.h b/arch/avr32/mach-at32ap/sdramc.h
deleted file mode 100644
index 66eeaed49073..000000000000
--- a/arch/avr32/mach-at32ap/sdramc.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Register definitions for the AT32AP SDRAM Controller
- *
- * Copyright (C) 2008 Atmel Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- */
-
-/* Register offsets */
-#define SDRAMC_MR 0x0000
-#define SDRAMC_TR 0x0004
-#define SDRAMC_CR 0x0008
-#define SDRAMC_HSR 0x000c
-#define SDRAMC_LPR 0x0010
-#define SDRAMC_IER 0x0014
-#define SDRAMC_IDR 0x0018
-#define SDRAMC_IMR 0x001c
-#define SDRAMC_ISR 0x0020
-#define SDRAMC_MDR 0x0024
-
-/* MR - Mode Register */
-#define SDRAMC_MR_MODE_NORMAL ( 0 << 0)
-#define SDRAMC_MR_MODE_NOP ( 1 << 0)
-#define SDRAMC_MR_MODE_BANKS_PRECHARGE ( 2 << 0)
-#define SDRAMC_MR_MODE_LOAD_MODE ( 3 << 0)
-#define SDRAMC_MR_MODE_AUTO_REFRESH ( 4 << 0)
-#define SDRAMC_MR_MODE_EXT_LOAD_MODE ( 5 << 0)
-#define SDRAMC_MR_MODE_POWER_DOWN ( 6 << 0)
-
-/* CR - Configuration Register */
-#define SDRAMC_CR_NC_8_BITS ( 0 << 0)
-#define SDRAMC_CR_NC_9_BITS ( 1 << 0)
-#define SDRAMC_CR_NC_10_BITS ( 2 << 0)
-#define SDRAMC_CR_NC_11_BITS ( 3 << 0)
-#define SDRAMC_CR_NR_11_BITS ( 0 << 2)
-#define SDRAMC_CR_NR_12_BITS ( 1 << 2)
-#define SDRAMC_CR_NR_13_BITS ( 2 << 2)
-#define SDRAMC_CR_NB_2_BANKS ( 0 << 4)
-#define SDRAMC_CR_NB_4_BANKS ( 1 << 4)
-#define SDRAMC_CR_CAS(x) ((x) << 5)
-#define SDRAMC_CR_DBW_32_BITS ( 0 << 7)
-#define SDRAMC_CR_DBW_16_BITS ( 1 << 7)
-#define SDRAMC_CR_TWR(x) ((x) << 8)
-#define SDRAMC_CR_TRC(x) ((x) << 12)
-#define SDRAMC_CR_TRP(x) ((x) << 16)
-#define SDRAMC_CR_TRCD(x) ((x) << 20)
-#define SDRAMC_CR_TRAS(x) ((x) << 24)
-#define SDRAMC_CR_TXSR(x) ((x) << 28)
-
-/* HSR - High Speed Register */
-#define SDRAMC_HSR_DA ( 1 << 0)
-
-/* LPR - Low Power Register */
-#define SDRAMC_LPR_LPCB_INHIBIT ( 0 << 0)
-#define SDRAMC_LPR_LPCB_SELF_RFR ( 1 << 0)
-#define SDRAMC_LPR_LPCB_PDOWN ( 2 << 0)
-#define SDRAMC_LPR_LPCB_DEEP_PDOWN ( 3 << 0)
-#define SDRAMC_LPR_PASR(x) ((x) << 4)
-#define SDRAMC_LPR_TCSR(x) ((x) << 8)
-#define SDRAMC_LPR_DS(x) ((x) << 10)
-#define SDRAMC_LPR_TIMEOUT(x) ((x) << 12)
-
-/* IER/IDR/IMR/ISR - Interrupt Enable/Disable/Mask/Status Register */
-#define SDRAMC_ISR_RES ( 1 << 0)
-
-/* MDR - Memory Device Register */
-#define SDRAMC_MDR_MD_SDRAM ( 0 << 0)
-#define SDRAMC_MDR_MD_LOW_PWR_SDRAM ( 1 << 0)
-
-/* Register access macros */
-#define sdramc_readl(reg) \
- __raw_readl((void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
-#define sdramc_writel(reg, value) \
- __raw_writel(value, (void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)