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| author | Atish Patra <atishp@rivosinc.com> | 2022-07-22 18:50:47 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2022-08-12 16:43:57 +0200 |
| commit | 8f5cb44b1bae8520c0705ce348b30ffb1fdda43a (patch) | |
| tree | 4e80fff0b3baebf935b46b2aa13a2c62678754a6 /arch/riscv/include/uapi | |
| parent | perf: riscv_pmu{,_sbi}: Miscallenous improvement & fixes (diff) | |
| download | linux-8f5cb44b1bae8520c0705ce348b30ffb1fdda43a.tar.xz linux-8f5cb44b1bae8520c0705ce348b30ffb1fdda43a.zip | |
RISC-V: KVM: Support sstc extension
Sstc extension allows the guest to program the vstimecmp CSR directly
instead of making an SBI call to the hypervisor to program the next
event. The timer interrupt is also directly injected to the guest by
the hardware in this case. To maintain backward compatibility, the
hypervisors also update the vstimecmp in an SBI set_time call if
the hardware supports it. Thus, the older kernels in guest also
take advantage of the sstc extension.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Acked-by: Anup Patel <anup@brainfault.org>
Link: https://lore.kernel.org/all/CAAhSdy2mb6wyqy0NAn9BcTWKMYEc0Z4zU3s3j7oNqBz6eDQ9sg@mail.gmail.com/
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'arch/riscv/include/uapi')
| -rw-r--r-- | arch/riscv/include/uapi/asm/kvm.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 24b2a6e27698..7351417afd62 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -97,6 +97,7 @@ enum KVM_RISCV_ISA_EXT_ID { KVM_RISCV_ISA_EXT_I, KVM_RISCV_ISA_EXT_M, KVM_RISCV_ISA_EXT_SVPBMT, + KVM_RISCV_ISA_EXT_SSTC, KVM_RISCV_ISA_EXT_MAX, }; |