diff options
| author | Kim Phillips <kim.phillips@amd.com> | 2020-04-17 16:33:56 +0200 |
|---|---|---|
| committer | Borislav Petkov <bp@suse.de> | 2020-05-07 17:30:14 +0200 |
| commit | e2abfc0448a46d8a137505aa180caf14070ec535 (patch) | |
| tree | 3bbe0d705fc00cc8b19152c3ea847b1136e405f2 /arch/x86/include/asm/archrandom.h | |
| parent | x86/apic: Convert the TSC deadline timer matching to steppings macro (diff) | |
| download | linux-e2abfc0448a46d8a137505aa180caf14070ec535.tar.xz linux-e2abfc0448a46d8a137505aa180caf14070ec535.zip | |
x86/cpu/amd: Make erratum #1054 a legacy erratum
Commit
21b5ee59ef18 ("x86/cpu/amd: Enable the fixed Instructions Retired
counter IRPERF")
mistakenly added erratum #1054 as an OS Visible Workaround (OSVW) ID 0.
Erratum #1054 is not OSVW ID 0 [1], so make it a legacy erratum.
There would never have been a false positive on older hardware that
has OSVW bit 0 set, since the IRPERF feature was not available.
However, save a couple of RDMSR executions per thread, on modern
system configurations that correctly set non-zero values in their
OSVW_ID_Length MSRs.
[1] Revision Guide for AMD Family 17h Models 00h-0Fh Processors. The
revision guide is available from the bugzilla link below.
Fixes: 21b5ee59ef18 ("x86/cpu/amd: Enable the fixed Instructions Retired counter IRPERF")
Reported-by: Andrew Cooper <andrew.cooper3@citrix.com>
Signed-off-by: Kim Phillips <kim.phillips@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lkml.kernel.org/r/20200417143356.26054-1-kim.phillips@amd.com
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Diffstat (limited to 'arch/x86/include/asm/archrandom.h')
0 files changed, 0 insertions, 0 deletions