diff options
| author | Jerome Brunet <jbrunet@baylibre.com> | 2018-08-01 16:00:51 +0200 |
|---|---|---|
| committer | Jerome Brunet <jbrunet@baylibre.com> | 2018-09-26 12:00:28 +0200 |
| commit | 2303a9ca693e585a558497ad737728fec97e2b8a (patch) | |
| tree | 69cc8cbe75ffd3db797ceb7356a7338b7131c920 /drivers/clk/meson/axg.c | |
| parent | clk: meson: clk-pll: add enable bit (diff) | |
| download | linux-2303a9ca693e585a558497ad737728fec97e2b8a.tar.xz linux-2303a9ca693e585a558497ad737728fec97e2b8a.zip | |
clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
CLK_GET_RATE_NOCACHE should only be necessary when the registers
controlling the rate of clock may change outside of CCF. On Amlogic,
it should only be the case for the hdmi pll which is directly controlled
by the display driver (WIP to fix this).
The other plls should not require this flag.
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Diffstat (limited to 'drivers/clk/meson/axg.c')
| -rw-r--r-- | drivers/clk/meson/axg.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c index 6d8976554656..991fa511c05a 100644 --- a/drivers/clk/meson/axg.c +++ b/drivers/clk/meson/axg.c @@ -106,7 +106,6 @@ static struct clk_regmap axg_sys_pll = { .ops = &meson_clk_pll_ro_ops, .parent_names = (const char *[]){ "xtal" }, .num_parents = 1, - .flags = CLK_GET_RATE_NOCACHE, }, }; |