diff options
| author | Wolfram Sang <wsa+renesas@sang-engineering.com> | 2021-11-10 20:15:51 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2021-11-19 11:27:58 +0100 |
| commit | 1abd04480866cead7b4129bd03246315b4575334 (patch) | |
| tree | 077d4a5076fd6fb3a6742ebcd5b55d18b587a2e3 /drivers/clk/renesas/r8a77990-cpg-mssr.c | |
| parent | clk: renesas: rcar-gen3: Add dummy SDnH clock (diff) | |
| download | linux-1abd04480866cead7b4129bd03246315b4575334.tar.xz linux-1abd04480866cead7b4129bd03246315b4575334.zip | |
clk: renesas: rcar-gen3: Add SDnH clock
Currently a pass-through clock but we will make it a real divider clock
in the next patches.
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20211110191610.5664-3-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/r8a77990-cpg-mssr.c')
| -rw-r--r-- | drivers/clk/renesas/r8a77990-cpg-mssr.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index a582f2ec3294..faf60f7adc8d 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -100,9 +100,12 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { DEF_FIXED("s3d2", R8A77990_CLK_S3D2, CLK_S3, 2, 1), DEF_FIXED("s3d4", R8A77990_CLK_S3D4, CLK_S3, 4, 1), - DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, CLK_SDSRC, 0x0074), - DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, CLK_SDSRC, 0x0078), - DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, CLK_SDSRC, 0x026c), + DEF_GEN3_SDH("sd0h", R8A77990_CLK_SD0H, CLK_SDSRC, 0x0074), + DEF_GEN3_SDH("sd1h", R8A77990_CLK_SD1H, CLK_SDSRC, 0x0078), + DEF_GEN3_SDH("sd3h", R8A77990_CLK_SD3H, CLK_SDSRC, 0x026c), + DEF_GEN3_SD("sd0", R8A77990_CLK_SD0, R8A77990_CLK_SD0H, 0x0074), + DEF_GEN3_SD("sd1", R8A77990_CLK_SD1, R8A77990_CLK_SD1H, 0x0078), + DEF_GEN3_SD("sd3", R8A77990_CLK_SD3, R8A77990_CLK_SD3H, 0x026c), DEF_FIXED("cl", R8A77990_CLK_CL, CLK_PLL1, 48, 1), DEF_FIXED("cr", R8A77990_CLK_CR, CLK_PLL1D2, 2, 1), |