diff options
| author | Bartosz Wawrzyniak <bwawrzyn@cisco.com> | 2023-03-16 11:03:39 +0100 |
|---|---|---|
| committer | David S. Miller <davem@davemloft.net> | 2023-03-19 09:39:21 +0100 |
| commit | b31587feaa0133b19a1900a26bce07a3c6d21af6 (patch) | |
| tree | c4949401f178536981907560e73a01aa58b6a347 /drivers/net/ethernet/cadence | |
| parent | Merge branch 'net-better-const' (diff) | |
| download | linux-b31587feaa0133b19a1900a26bce07a3c6d21af6.tar.xz linux-b31587feaa0133b19a1900a26bce07a3c6d21af6.zip | |
net: macb: Set MDIO clock divisor for pclk higher than 160MHz
Currently macb sets clock divisor for pclk up to 160 MHz.
Function gem_mdc_clk_div was updated to enable divisor
for higher values of pclk.
Signed-off-by: Bartosz Wawrzyniak <bwawrzyn@cisco.com>
Reviewed-by: Michal Kubiak <michal.kubiak@intel.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/ethernet/cadence')
| -rw-r--r-- | drivers/net/ethernet/cadence/macb.h | 2 | ||||
| -rw-r--r-- | drivers/net/ethernet/cadence/macb_main.c | 6 |
2 files changed, 7 insertions, 1 deletions
diff --git a/drivers/net/ethernet/cadence/macb.h b/drivers/net/ethernet/cadence/macb.h index 14dfec4db8f9..c1fc91c97cee 100644 --- a/drivers/net/ethernet/cadence/macb.h +++ b/drivers/net/ethernet/cadence/macb.h @@ -692,6 +692,8 @@ #define GEM_CLK_DIV48 3 #define GEM_CLK_DIV64 4 #define GEM_CLK_DIV96 5 +#define GEM_CLK_DIV128 6 +#define GEM_CLK_DIV224 7 /* Constants for MAN register */ #define MACB_MAN_C22_SOF 1 diff --git a/drivers/net/ethernet/cadence/macb_main.c b/drivers/net/ethernet/cadence/macb_main.c index c4edd20c1c66..7698719b1909 100644 --- a/drivers/net/ethernet/cadence/macb_main.c +++ b/drivers/net/ethernet/cadence/macb_main.c @@ -2640,8 +2640,12 @@ static u32 gem_mdc_clk_div(struct macb *bp) config = GEM_BF(CLK, GEM_CLK_DIV48); else if (pclk_hz <= 160000000) config = GEM_BF(CLK, GEM_CLK_DIV64); - else + else if (pclk_hz <= 240000000) config = GEM_BF(CLK, GEM_CLK_DIV96); + else if (pclk_hz <= 320000000) + config = GEM_BF(CLK, GEM_CLK_DIV128); + else + config = GEM_BF(CLK, GEM_CLK_DIV224); return config; } |