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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2020-06-26 21:30:07 +0200 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2020-06-26 21:30:07 +0200 |
| commit | bd37cdf8ba1b56a968173560314398d5d3b2d37a (patch) | |
| tree | ee66fa706f39c6d18b4f2d66a4cdca3f50d4dd71 /include | |
| parent | Merge tag 'drm-fixes-2020-06-26' of git://anongit.freedesktop.org/drm/drm (diff) | |
| parent | iommu/vt-d: Fix misuse of iommu_domain_identity_map() (diff) | |
| download | linux-bd37cdf8ba1b56a968173560314398d5d3b2d37a.tar.xz linux-bd37cdf8ba1b56a968173560314398d5d3b2d37a.zip | |
Merge tag 'iommu-fixes-v5.8-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu fixes from Joerg Roedel:
"A couple of Intel VT-d fixes:
- Make Intel SVM code 64bit only. The code uses pgd_t* and the IOMMU
only supports long-mode page-table formats, so its broken on 32bit
anyway.
- Make sure GFX quirks in for Intel VT-d are not applied to untrusted
devices. Those devices might gain full memory access otherwise.
- Identity mapping setup fix.
- Fix ACS enabling when Intel IOMMU is off and untrusted devices are
detected.
- Two smaller fixes for coherency and IO page-table setup"
* tag 'iommu-fixes-v5.8-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu:
iommu/vt-d: Fix misuse of iommu_domain_identity_map()
iommu/vt-d: Update scalable mode paging structure coherency
iommu/vt-d: Enable PCI ACS for platform opt in hint
iommu/vt-d: Don't apply gfx quirks to untrusted devices
iommu/vt-d: Set U/S bit in first level page table by default
iommu/vt-d: Make Intel SVM code 64-bit only
Diffstat (limited to 'include')
| -rw-r--r-- | include/linux/intel-iommu.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 4100bd224f5c..3e8fa1c7a1e6 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -41,6 +41,7 @@ #define DMA_PTE_SNP BIT_ULL(11) #define DMA_FL_PTE_PRESENT BIT_ULL(0) +#define DMA_FL_PTE_US BIT_ULL(2) #define DMA_FL_PTE_XD BIT_ULL(63) #define ADDR_WIDTH_5LEVEL (57) |