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authorPankaj Dubey <pankaj.dubey@samsung.com>2014-09-29 09:47:46 +0200
committerSylwester Nawrocki <s.nawrocki@samsung.com>2014-12-02 12:28:20 +0100
commit2e41b9fc11f2d242f39b36ceba833471629ba3d5 (patch)
tree59a7114db7a741606aa1f74b62a85b8de832c9ec /mm/pagewalk.c
parentclk: samsung: exynos7: add gate clock for ADC block (diff)
downloadlinux-2e41b9fc11f2d242f39b36ceba833471629ba3d5.tar.xz
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clk: samsung: Spelling s/bwtween/between/
Fix a typo in comment section of "struct samsung_clk_provider". Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Diffstat (limited to 'mm/pagewalk.c')
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