diff options
59 files changed, 3229 insertions, 1894 deletions
diff --git a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml index 762be3f96ce9..7dc13a4b1805 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8mq-vpu.yaml @@ -5,7 +5,7 @@ $id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" -title: Hantro G1/G2 VPU codecs implemented on i.MX8MQ SoCs +title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs maintainers: - Philipp Zabel <p.zabel@pengutronix.de> @@ -15,33 +15,21 @@ description: properties: compatible: - const: nxp,imx8mq-vpu + oneOf: + - const: nxp,imx8mq-vpu + deprecated: true + - const: nxp,imx8mq-vpu-g1 + - const: nxp,imx8mq-vpu-g2 + - const: nxp,imx8mm-vpu-g1 reg: - maxItems: 3 - - reg-names: - items: - - const: g1 - - const: g2 - - const: ctrl + maxItems: 1 interrupts: - maxItems: 2 - - interrupt-names: - items: - - const: g1 - - const: g2 + maxItems: 1 clocks: - maxItems: 3 - - clock-names: - items: - - const: g1 - - const: g2 - - const: bus + maxItems: 1 power-domains: maxItems: 1 @@ -49,31 +37,33 @@ properties: required: - compatible - reg - - reg-names - interrupts - - interrupt-names - clocks - - clock-names additionalProperties: false examples: - | #include <dt-bindings/clock/imx8mq-clock.h> + #include <dt-bindings/power/imx8mq-power.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + vpu_g1: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g1"; + reg = <0x38300000 0x10000>; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; + }; + - | + #include <dt-bindings/clock/imx8mq-clock.h> + #include <dt-bindings/power/imx8mq-power.h> #include <dt-bindings/interrupt-controller/arm-gic.h> - vpu: video-codec@38300000 { - compatible = "nxp,imx8mq-vpu"; - reg = <0x38300000 0x10000>, - <0x38310000 0x10000>, - <0x38320000 0x10000>; - reg-names = "g1", "g2", "ctrl"; - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "g1", "g2"; - clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; - clock-names = "g1", "g2", "bus"; - power-domains = <&pgc_vpu>; + vpu_g2: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu-g2"; + reg = <0x38310000 0x10000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; }; diff --git a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml index 9404d6b9db54..f9a003882f84 100644 --- a/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sdm845-camss.yaml @@ -186,9 +186,13 @@ properties: - const: vfe1 - const: vfe_lite - vdda-supply: + vdda-phy-supply: description: - Definition of the regulator used as analog power supply. + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. required: - clock-names @@ -200,7 +204,8 @@ required: - power-domains - reg - reg-names - - vdda-supply + - vdda-phy-supply + - vdda-pll-supply additionalProperties: false @@ -344,7 +349,8 @@ examples: "vfe1", "vfe_lite"; - vdda-supply = <®_2v8>; + vdda-phy-supply = <&vreg_l1a_0p875>; + vdda-pll-supply = <&vreg_l26a_1p2>; ports { #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml index af877d61b607..07a2af12f37d 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8250-camss.yaml @@ -265,6 +265,14 @@ properties: - const: vfe_lite0 - const: vfe_lite1 + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + required: - clock-names - clocks @@ -277,6 +285,8 @@ required: - power-domains - reg - reg-names + - vdda-phy-supply + - vdda-pll-supply additionalProperties: false @@ -316,6 +326,9 @@ examples: "vfe_lite0", "vfe_lite1"; + vdda-phy-supply = <&vreg_l5a_0p88>; + vdda-pll-supply = <&vreg_l9a_1p2>; + interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, diff --git a/Documentation/devicetree/bindings/media/renesas,csi2.yaml b/Documentation/devicetree/bindings/media/renesas,csi2.yaml index e6a036721082..b520d6c5c102 100644 --- a/Documentation/devicetree/bindings/media/renesas,csi2.yaml +++ b/Documentation/devicetree/bindings/media/renesas,csi2.yaml @@ -67,7 +67,10 @@ properties: maxItems: 1 data-lanes: - maxItems: 1 + minItems: 1 + maxItems: 4 + items: + maximum: 4 required: - clock-lanes diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst index cc080c4257d0..f87584ad90ba 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec-stateless.rst @@ -616,6 +616,12 @@ Stateless Codec Control ID * - ``V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD`` - 0x00000004 - + * - ``V4L2_H264_DECODE_PARAM_FLAG_PFRAME`` + - 0x00000008 + - + * - ``V4L2_H264_DECODE_PARAM_FLAG_BFRAME`` + - 0x00000010 + - .. raw:: latex diff --git a/Documentation/userspace-api/media/v4l/pixfmt-rgb.rst b/Documentation/userspace-api/media/v4l/pixfmt-rgb.rst index 48b0f787274c..30f51cd33f99 100644 --- a/Documentation/userspace-api/media/v4l/pixfmt-rgb.rst +++ b/Documentation/userspace-api/media/v4l/pixfmt-rgb.rst @@ -672,8 +672,8 @@ nomenclature that instead use the order of components as seen in a 24- or - ``V4L2_PIX_FMT_BGR24`` - 'BGR3' - - G\ :sub:`7-0` - B\ :sub:`7-0` + - G\ :sub:`7-0` - R\ :sub:`7-0` - * .. _V4L2-PIX-FMT-RGB24: diff --git a/MAINTAINERS b/MAINTAINERS index 83d27b57016f..f2d313bf0c54 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -11947,7 +11947,7 @@ L: linux-tegra@vger.kernel.org S: Maintained T: git git://linuxtv.org/media_tree.git F: Documentation/devicetree/bindings/media/nvidia,tegra-vde.txt -F: drivers/staging/media/tegra-vde/ +F: drivers/media/platform/tegra/vde/ MEDIA DRIVERS FOR RENESAS - CEU M: Jacopo Mondi <jacopo@jmondi.org> diff --git a/drivers/media/cec/platform/seco/seco-cec.c b/drivers/media/cec/platform/seco/seco-cec.c index ae138cc253fd..78856a55e637 100644 --- a/drivers/media/cec/platform/seco/seco-cec.c +++ b/drivers/media/cec/platform/seco/seco-cec.c @@ -129,7 +129,7 @@ static int secocec_adap_enable(struct cec_adapter *adap, bool enable) if (status) goto err; - dev_dbg(dev, "Device enabled"); + dev_dbg(dev, "Device enabled\n"); } else { /* Clear the status register */ status = smb_rd16(SECOCEC_STATUS_REG_1, &val); @@ -141,7 +141,7 @@ static int secocec_adap_enable(struct cec_adapter *adap, bool enable) ~SECOCEC_ENABLE_REG_1_CEC & ~SECOCEC_ENABLE_REG_1_IR); - dev_dbg(dev, "Device disabled"); + dev_dbg(dev, "Device disabled\n"); } return 0; @@ -264,12 +264,12 @@ static void secocec_rx_done(struct cec_adapter *adap, u16 status_val) if (status_val & SECOCEC_STATUS_RX_OVERFLOW_MASK) { /* NOTE: Untested, it also might not be necessary */ - dev_warn(dev, "Received more than 16 bytes. Discarding"); + dev_warn(dev, "Received more than 16 bytes. Discarding\n"); flag_overflow = true; } if (status_val & SECOCEC_STATUS_RX_ERROR_MASK) { - dev_warn(dev, "Message received with errors. Discarding"); + dev_warn(dev, "Message received with errors. Discarding\n"); status = -EIO; goto rxerr; } @@ -390,12 +390,12 @@ static int secocec_ir_probe(void *priv) if (status != 0) goto err; - dev_dbg(dev, "IR enabled"); + dev_dbg(dev, "IR enabled\n"); status = devm_rc_register_device(dev, cec->ir); if (status) { - dev_err(dev, "Failed to prepare input device"); + dev_err(dev, "Failed to prepare input device\n"); cec->ir = NULL; goto err; } @@ -408,7 +408,7 @@ err: smb_wr16(SECOCEC_ENABLE_REG_1, val & ~SECOCEC_ENABLE_REG_1_IR); - dev_dbg(dev, "IR disabled"); + dev_dbg(dev, "IR disabled\n"); return status; } @@ -431,13 +431,13 @@ static int secocec_ir_rx(struct secocec_data *priv) rc_keydown(cec->ir, RC_PROTO_RC5, RC_SCANCODE_RC5(addr, key), toggle); - dev_dbg(dev, "IR key pressed: 0x%02x addr 0x%02x toggle 0x%02x", key, + dev_dbg(dev, "IR key pressed: 0x%02x addr 0x%02x toggle 0x%02x\n", key, addr, toggle); return 0; err: - dev_err(dev, "IR Receive message failed (%d)", status); + dev_err(dev, "IR Receive message failed (%d)\n", status); return -EIO; } #else @@ -497,7 +497,7 @@ static irqreturn_t secocec_irq_handler(int irq, void *priv) return IRQ_HANDLED; err: - dev_err_once(dev, "IRQ: R/W SMBus operation failed (%d)", status); + dev_err_once(dev, "IRQ: R/W SMBus operation failed %d\n", status); /* Reset status register */ val = SECOCEC_STATUS_REG_1_CEC | SECOCEC_STATUS_REG_1_IR; @@ -553,16 +553,16 @@ static int secocec_acpi_probe(struct secocec_data *sdev) gpio = devm_gpiod_get(dev, NULL, GPIOF_IN); if (IS_ERR(gpio)) { - dev_err(dev, "Cannot request interrupt gpio"); + dev_err(dev, "Cannot request interrupt gpio\n"); return PTR_ERR(gpio); } irq = gpiod_to_irq(gpio); if (irq < 0) { - dev_err(dev, "Cannot find valid irq"); + dev_err(dev, "Cannot find valid irq\n"); return -ENODEV; } - dev_dbg(dev, "irq-gpio is bound to IRQ %d", irq); + dev_dbg(dev, "irq-gpio is bound to IRQ %d\n", irq); sdev->irq = irq; @@ -590,7 +590,7 @@ static int secocec_probe(struct platform_device *pdev) /* Request SMBus regions */ if (!request_muxed_region(BRA_SMB_BASE_ADDR, 7, "CEC00001")) { - dev_err(dev, "Request memory region failed"); + dev_err(dev, "Request memory region failed\n"); return -ENXIO; } @@ -598,14 +598,14 @@ static int secocec_probe(struct platform_device *pdev) secocec->dev = dev; if (!has_acpi_companion(dev)) { - dev_dbg(dev, "Cannot find any ACPI companion"); + dev_dbg(dev, "Cannot find any ACPI companion\n"); ret = -ENODEV; goto err; } ret = secocec_acpi_probe(secocec); if (ret) { - dev_err(dev, "Cannot assign gpio to IRQ"); + dev_err(dev, "Cannot assign gpio to IRQ\n"); ret = -ENODEV; goto err; } @@ -613,11 +613,11 @@ static int secocec_probe(struct platform_device *pdev) /* Firmware version check */ ret = smb_rd16(SECOCEC_VERSION, &val); if (ret) { - dev_err(dev, "Cannot check fw version"); + dev_err(dev, "Cannot check fw version\n"); goto err; } if (val < SECOCEC_LATEST_FW) { - dev_err(dev, "CEC Firmware not supported (v.%04x). Use ver > v.%04x", + dev_err(dev, "CEC Firmware not supported (v.%04x). Use ver > v.%04x\n", val, SECOCEC_LATEST_FW); ret = -EINVAL; goto err; @@ -631,7 +631,7 @@ static int secocec_probe(struct platform_device *pdev) dev_name(&pdev->dev), secocec); if (ret) { - dev_err(dev, "Cannot request IRQ %d", secocec->irq); + dev_err(dev, "Cannot request IRQ %d\n", secocec->irq); ret = -EIO; goto err; } @@ -666,7 +666,7 @@ static int secocec_probe(struct platform_device *pdev) platform_set_drvdata(pdev, secocec); - dev_dbg(dev, "Device registered"); + dev_dbg(dev, "Device registered\n"); return ret; @@ -691,14 +691,14 @@ static int secocec_remove(struct platform_device *pdev) smb_wr16(SECOCEC_ENABLE_REG_1, val & ~SECOCEC_ENABLE_REG_1_IR); - dev_dbg(&pdev->dev, "IR disabled"); + dev_dbg(&pdev->dev, "IR disabled\n"); } cec_notifier_cec_adap_unregister(secocec->notifier, secocec->cec_adap); cec_unregister_adapter(secocec->cec_adap); release_region(BRA_SMB_BASE_ADDR, 7); - dev_dbg(&pdev->dev, "CEC device removed"); + dev_dbg(&pdev->dev, "CEC device removed\n"); return 0; } @@ -709,7 +709,7 @@ static int secocec_suspend(struct device *dev) int status; u16 val; - dev_dbg(dev, "Device going to suspend, disabling"); + dev_dbg(dev, "Device going to suspend, disabling\n"); /* Clear the status register */ status = smb_rd16(SECOCEC_STATUS_REG_1, &val); @@ -733,7 +733,7 @@ static int secocec_suspend(struct device *dev) return 0; err: - dev_err(dev, "Suspend failed (err: %d)", status); + dev_err(dev, "Suspend failed: %d\n", status); return status; } @@ -742,7 +742,7 @@ static int secocec_resume(struct device *dev) int status; u16 val; - dev_dbg(dev, "Resuming device from suspend"); + dev_dbg(dev, "Resuming device from suspend\n"); /* Clear the status register */ status = smb_rd16(SECOCEC_STATUS_REG_1, &val); @@ -762,12 +762,12 @@ static int secocec_resume(struct device *dev) if (status) goto err; - dev_dbg(dev, "Device resumed from suspend"); + dev_dbg(dev, "Device resumed from suspend\n"); return 0; err: - dev_err(dev, "Resume failed (err: %d)", status); + dev_err(dev, "Resume failed: %d\n", status); return status; } diff --git a/drivers/media/common/videobuf2/videobuf2-dma-contig.c b/drivers/media/common/videobuf2/videobuf2-dma-contig.c index 7c4096e62173..0e3f264122af 100644 --- a/drivers/media/common/videobuf2/videobuf2-dma-contig.c +++ b/drivers/media/common/videobuf2/videobuf2-dma-contig.c @@ -132,12 +132,12 @@ static void vb2_dc_prepare(void *buf_priv) if (!buf->non_coherent_mem) return; - /* For both USERPTR and non-coherent MMAP */ - dma_sync_sgtable_for_device(buf->dev, sgt, buf->dma_dir); - /* Non-coherent MMAP only */ if (buf->vaddr) flush_kernel_vmap_range(buf->vaddr, buf->size); + + /* For both USERPTR and non-coherent MMAP */ + dma_sync_sgtable_for_device(buf->dev, sgt, buf->dma_dir); } static void vb2_dc_finish(void *buf_priv) @@ -152,12 +152,12 @@ static void vb2_dc_finish(void *buf_priv) if (!buf->non_coherent_mem) return; - /* For both USERPTR and non-coherent MMAP */ - dma_sync_sgtable_for_cpu(buf->dev, sgt, buf->dma_dir); - /* Non-coherent MMAP only */ if (buf->vaddr) invalidate_kernel_vmap_range(buf->vaddr, buf->size); + + /* For both USERPTR and non-coherent MMAP */ + dma_sync_sgtable_for_cpu(buf->dev, sgt, buf->dma_dir); } /*********************************************/ diff --git a/drivers/media/dvb-frontends/dib3000mc.c b/drivers/media/dvb-frontends/dib3000mc.c index 692600ce5f23..2e11a246aae0 100644 --- a/drivers/media/dvb-frontends/dib3000mc.c +++ b/drivers/media/dvb-frontends/dib3000mc.c @@ -859,7 +859,7 @@ int dib3000mc_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 defa int k; u8 new_addr; - static u8 DIB3000MC_I2C_ADDRESS[] = {20,22,24,26}; + static const u8 DIB3000MC_I2C_ADDRESS[] = { 20, 22, 24, 26 }; dmcst = kzalloc(sizeof(struct dib3000mc_state), GFP_KERNEL); if (dmcst == NULL) diff --git a/drivers/media/dvb-frontends/dib7000p.c b/drivers/media/dvb-frontends/dib7000p.c index 55bee50aa871..a90d2f51868f 100644 --- a/drivers/media/dvb-frontends/dib7000p.c +++ b/drivers/media/dvb-frontends/dib7000p.c @@ -1188,8 +1188,8 @@ static int dib7000p_autosearch_is_irq(struct dvb_frontend *demod) static void dib7000p_spur_protect(struct dib7000p_state *state, u32 rf_khz, u32 bw) { - static s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 }; - static u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22, + static const s16 notch[] = { 16143, 14402, 12238, 9713, 6902, 3888, 759, -2392 }; + static const u8 sine[] = { 0, 2, 3, 5, 6, 8, 9, 11, 13, 14, 16, 17, 19, 20, 22, 24, 25, 27, 28, 30, 31, 33, 34, 36, 38, 39, 41, 42, 44, 45, 47, 48, 50, 51, 53, 55, 56, 58, 59, 61, 62, 64, 65, 67, 68, 70, 71, 73, 74, 76, 77, 79, 80, 82, 83, 85, 86, 88, 89, 91, 92, 94, 95, 97, 98, 99, 101, 102, 104, 105, diff --git a/drivers/media/dvb-frontends/stv0299.c b/drivers/media/dvb-frontends/stv0299.c index 00b2c63e2192..b5263a0ee5aa 100644 --- a/drivers/media/dvb-frontends/stv0299.c +++ b/drivers/media/dvb-frontends/stv0299.c @@ -161,8 +161,9 @@ static int stv0299_set_FEC(struct stv0299_state *state, enum fe_code_rate fec) static enum fe_code_rate stv0299_get_fec(struct stv0299_state *state) { - static enum fe_code_rate fec_tab[] = { FEC_2_3, FEC_3_4, FEC_5_6, - FEC_7_8, FEC_1_2 }; + static const enum fe_code_rate fec_tab[] = { + FEC_2_3, FEC_3_4, FEC_5_6, FEC_7_8, FEC_1_2 + }; u8 index; dprintk ("%s\n", __func__); diff --git a/drivers/media/pci/cx18/cx18-queue.h b/drivers/media/pci/cx18/cx18-queue.h index e0a34bd6539e..26f2097c0496 100644 --- a/drivers/media/pci/cx18/cx18-queue.h +++ b/drivers/media/pci/cx18/cx18-queue.h @@ -15,15 +15,15 @@ static inline void cx18_buf_sync_for_cpu(struct cx18_stream *s, struct cx18_buffer *buf) { - pci_dma_sync_single_for_cpu(s->cx->pci_dev, buf->dma_handle, + dma_sync_single_for_cpu(&s->cx->pci_dev->dev, buf->dma_handle, s->buf_size, s->dma); } static inline void cx18_buf_sync_for_device(struct cx18_stream *s, struct cx18_buffer *buf) { - pci_dma_sync_single_for_device(s->cx->pci_dev, buf->dma_handle, - s->buf_size, s->dma); + dma_sync_single_for_device(&s->cx->pci_dev->dev, buf->dma_handle, + s->buf_size, s->dma); } void _cx18_mdl_sync_for_device(struct cx18_stream *s, struct cx18_mdl *mdl); diff --git a/drivers/media/pci/ivtv/ivtv-queue.h b/drivers/media/pci/ivtv/ivtv-queue.h index 586b0bf63c26..983e99642364 100644 --- a/drivers/media/pci/ivtv/ivtv-queue.h +++ b/drivers/media/pci/ivtv/ivtv-queue.h @@ -17,20 +17,20 @@ static inline int ivtv_might_use_pio(struct ivtv_stream *s) { - return s->dma == PCI_DMA_NONE || (SLICED_VBI_PIO && s->type == IVTV_ENC_STREAM_TYPE_VBI); + return s->dma == DMA_NONE || (SLICED_VBI_PIO && s->type == IVTV_ENC_STREAM_TYPE_VBI); } static inline int ivtv_use_pio(struct ivtv_stream *s) { struct ivtv *itv = s->itv; - return s->dma == PCI_DMA_NONE || + return s->dma == DMA_NONE || (SLICED_VBI_PIO && s->type == IVTV_ENC_STREAM_TYPE_VBI && itv->vbi.sliced_in->service_set); } static inline int ivtv_might_use_dma(struct ivtv_stream *s) { - return s->dma != PCI_DMA_NONE; + return s->dma != DMA_NONE; } static inline int ivtv_use_dma(struct ivtv_stream *s) @@ -41,15 +41,16 @@ static inline int ivtv_use_dma(struct ivtv_stream *s) static inline void ivtv_buf_sync_for_cpu(struct ivtv_stream *s, struct ivtv_buffer *buf) { if (ivtv_use_dma(s)) - pci_dma_sync_single_for_cpu(s->itv->pdev, buf->dma_handle, - s->buf_size + 256, s->dma); + dma_sync_single_for_cpu(&s->itv->pdev->dev, buf->dma_handle, + s->buf_size + 256, s->dma); } static inline void ivtv_buf_sync_for_device(struct ivtv_stream *s, struct ivtv_buffer *buf) { if (ivtv_use_dma(s)) - pci_dma_sync_single_for_device(s->itv->pdev, buf->dma_handle, - s->buf_size + 256, s->dma); + dma_sync_single_for_device(&s->itv->pdev->dev, + buf->dma_handle, s->buf_size + 256, + s->dma); } int ivtv_buf_copy_from_user(struct ivtv_stream *s, struct ivtv_buffer *buf, const char __user *src, int copybytes); @@ -70,15 +71,17 @@ void ivtv_stream_free(struct ivtv_stream *s); static inline void ivtv_stream_sync_for_cpu(struct ivtv_stream *s) { if (ivtv_use_dma(s)) - pci_dma_sync_single_for_cpu(s->itv->pdev, s->sg_handle, - sizeof(struct ivtv_sg_element), PCI_DMA_TODEVICE); + dma_sync_single_for_cpu(&s->itv->pdev->dev, s->sg_handle, + sizeof(struct ivtv_sg_element), + DMA_TO_DEVICE); } static inline void ivtv_stream_sync_for_device(struct ivtv_stream *s) { if (ivtv_use_dma(s)) - pci_dma_sync_single_for_device(s->itv->pdev, s->sg_handle, - sizeof(struct ivtv_sg_element), PCI_DMA_TODEVICE); + dma_sync_single_for_device(&s->itv->pdev->dev, s->sg_handle, + sizeof(struct ivtv_sg_element), + DMA_TO_DEVICE); } #endif diff --git a/drivers/media/pci/ivtv/ivtv-udma.h b/drivers/media/pci/ivtv/ivtv-udma.h index 0eef104e03b9..12b9426b2db2 100644 --- a/drivers/media/pci/ivtv/ivtv-udma.h +++ b/drivers/media/pci/ivtv/ivtv-udma.h @@ -23,14 +23,14 @@ void ivtv_udma_start(struct ivtv *itv); static inline void ivtv_udma_sync_for_device(struct ivtv *itv) { - pci_dma_sync_single_for_device(itv->pdev, itv->udma.SG_handle, - sizeof(itv->udma.SGarray), PCI_DMA_TODEVICE); + dma_sync_single_for_device(&itv->pdev->dev, itv->udma.SG_handle, + sizeof(itv->udma.SGarray), DMA_TO_DEVICE); } static inline void ivtv_udma_sync_for_cpu(struct ivtv *itv) { - pci_dma_sync_single_for_cpu(itv->pdev, itv->udma.SG_handle, - sizeof(itv->udma.SGarray), PCI_DMA_TODEVICE); + dma_sync_single_for_cpu(&itv->pdev->dev, itv->udma.SG_handle, + sizeof(itv->udma.SGarray), DMA_TO_DEVICE); } #endif diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig index 9fbdba0fd1e7..97a191a3c0a1 100644 --- a/drivers/media/platform/Kconfig +++ b/drivers/media/platform/Kconfig @@ -630,6 +630,23 @@ config VIDEO_SUN8I_ROTATE Support for the Allwinner DE2 rotation unit. To compile this driver as a module choose m here. +config VIDEO_TEGRA_VDE + tristate "NVIDIA Tegra Video Decoder Engine driver" + depends on ARCH_TEGRA || COMPILE_TEST + depends on VIDEO_DEV && VIDEO_V4L2 + select DMA_SHARED_BUFFER + select IOMMU_IOVA + select MEDIA_CONTROLLER + select MEDIA_CONTROLLER_REQUEST_API + select SRAM + select VIDEOBUF2_DMA_CONTIG + select VIDEOBUF2_DMA_SG + select V4L2_H264 + select V4L2_MEM2MEM_DEV + help + Support for the NVIDIA Tegra video decoder unit. + To compile this driver as a module choose m here. + endif # V4L_MEM2MEM_DRIVERS # TI VIDEO PORT Helper Modules diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile index 28eb4aadbf45..4c6fdca75b9f 100644 --- a/drivers/media/platform/Makefile +++ b/drivers/media/platform/Makefile @@ -89,3 +89,5 @@ obj-$(CONFIG_VIDEO_QCOM_VENUS) += qcom/venus/ obj-y += sunxi/ obj-$(CONFIG_VIDEO_MESON_GE2D) += meson/ge2d/ + +obj-$(CONFIG_VIDEO_TEGRA_VDE) += tegra/vde/ diff --git a/drivers/media/platform/davinci/vpif.c b/drivers/media/platform/davinci/vpif.c index 03b4e51bb13a..97ef770266af 100644 --- a/drivers/media/platform/davinci/vpif.c +++ b/drivers/media/platform/davinci/vpif.c @@ -20,8 +20,10 @@ #include <linux/err.h> #include <linux/init.h> #include <linux/io.h> +#include <linux/irq.h> #include <linux/kernel.h> #include <linux/module.h> +#include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/spinlock.h> @@ -437,11 +439,12 @@ static void vpif_pdev_release(struct device *dev) static int vpif_probe(struct platform_device *pdev) { - static struct resource *res_irq; + static struct resource res_irq; struct platform_device *pdev_capture, *pdev_display; struct device_node *endpoint = NULL; struct vpif_data *data; int ret; + int irq; vpif_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(vpif_base)) @@ -471,12 +474,13 @@ static int vpif_probe(struct platform_device *pdev) * For DT platforms, manually create platform_devices for * capture/display drivers. */ - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_irq) { - dev_warn(&pdev->dev, "Missing IRQ resource.\n"); - ret = -EINVAL; + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + ret = irq; goto err_put_rpm; } + res_irq = (struct resource)DEFINE_RES_IRQ_NAMED(irq, of_node_full_name(pdev->dev.of_node)); + res_irq.flags |= irq_get_trigger_type(irq); pdev_capture = kzalloc(sizeof(*pdev_capture), GFP_KERNEL); if (!pdev_capture) { @@ -486,7 +490,7 @@ static int vpif_probe(struct platform_device *pdev) pdev_capture->name = "vpif_capture"; pdev_capture->id = -1; - pdev_capture->resource = res_irq; + pdev_capture->resource = &res_irq; pdev_capture->num_resources = 1; pdev_capture->dev.dma_mask = pdev->dev.dma_mask; pdev_capture->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask; @@ -505,7 +509,7 @@ static int vpif_probe(struct platform_device *pdev) pdev_display->name = "vpif_display"; pdev_display->id = -1; - pdev_display->resource = res_irq; + pdev_display->resource = &res_irq; pdev_display->num_resources = 1; pdev_display->dev.dma_mask = pdev->dev.dma_mask; pdev_display->dev.coherent_dma_mask = pdev->dev.coherent_dma_mask; diff --git a/drivers/media/platform/davinci/vpif_capture.c b/drivers/media/platform/davinci/vpif_capture.c index 8fe55374c5a3..bf76c5c83743 100644 --- a/drivers/media/platform/davinci/vpif_capture.c +++ b/drivers/media/platform/davinci/vpif_capture.c @@ -1607,7 +1607,6 @@ static __init int vpif_probe(struct platform_device *pdev) { struct vpif_subdev_info *subdevdata; struct i2c_adapter *i2c_adap; - struct resource *res; int subdev_count; int res_idx = 0; int i, err; @@ -1632,17 +1631,23 @@ static __init int vpif_probe(struct platform_device *pdev) goto vpif_free; } - while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, res_idx))) { - err = devm_request_irq(&pdev->dev, res->start, vpif_channel_isr, - IRQF_SHARED, VPIF_DRIVER_NAME, - (void *)(&vpif_obj.dev[res_idx]-> - channel_id)); - if (err) { - err = -EINVAL; + do { + int irq; + + err = platform_get_irq_optional(pdev, res_idx); + if (err < 0 && err != -ENXIO) goto vpif_unregister; - } - res_idx++; - } + if (err > 0) + irq = err; + else + break; + + err = devm_request_irq(&pdev->dev, irq, vpif_channel_isr, + IRQF_SHARED, VPIF_DRIVER_NAME, + (void *)(&vpif_obj.dev[res_idx]->channel_id)); + if (err) + goto vpif_unregister; + } while (++res_idx); vpif_obj.config = pdev->dev.platform_data; diff --git a/drivers/media/platform/davinci/vpif_display.c b/drivers/media/platform/davinci/vpif_display.c index 59f6b782e104..fca148b66471 100644 --- a/drivers/media/platform/davinci/vpif_display.c +++ b/drivers/media/platform/davinci/vpif_display.c @@ -1221,7 +1221,6 @@ static __init int vpif_probe(struct platform_device *pdev) { struct vpif_subdev_info *subdevdata; struct i2c_adapter *i2c_adap; - struct resource *res; int subdev_count; int res_idx = 0; int i, err; @@ -1245,18 +1244,25 @@ static __init int vpif_probe(struct platform_device *pdev) goto vpif_free; } - while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, res_idx))) { - err = devm_request_irq(&pdev->dev, res->start, vpif_channel_isr, - IRQF_SHARED, VPIF_DRIVER_NAME, - (void *)(&vpif_obj.dev[res_idx]-> - channel_id)); + do { + int irq; + + err = platform_get_irq_optional(pdev, res_idx); + if (err < 0 && err != -ENXIO) + goto vpif_unregister; + if (err > 0) + irq = err; + else + break; + + err = devm_request_irq(&pdev->dev, irq, vpif_channel_isr, + IRQF_SHARED, VPIF_DRIVER_NAME, + (void *)(&vpif_obj.dev[res_idx]->channel_id)); if (err) { - err = -EINVAL; vpif_err("VPIF IRQ request failed\n"); goto vpif_unregister; } - res_idx++; - } + } while (++res_idx); vpif_obj.config = pdev->dev.platform_data; subdev_count = vpif_obj.config->subdev_count; diff --git a/drivers/media/platform/mtk-mdp/mtk_mdp_core.c b/drivers/media/platform/mtk-mdp/mtk_mdp_core.c index 3d395948b3c5..d83c4964eaf9 100644 --- a/drivers/media/platform/mtk-mdp/mtk_mdp_core.c +++ b/drivers/media/platform/mtk-mdp/mtk_mdp_core.c @@ -245,10 +245,8 @@ static int mtk_mdp_remove(struct platform_device *pdev) mtk_mdp_unregister_m2m_device(mdp); v4l2_device_unregister(&mdp->v4l2_dev); - flush_workqueue(mdp->wdt_wq); destroy_workqueue(mdp->wdt_wq); - flush_workqueue(mdp->job_wq); destroy_workqueue(mdp->job_wq); list_for_each_entry_safe(comp, comp_temp, &mdp->comp_list, node) { diff --git a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c index 2f2fe452c7ff..5172cfe0db4a 100644 --- a/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c +++ b/drivers/media/platform/mtk-vcodec/mtk_vcodec_enc_drv.c @@ -15,7 +15,6 @@ #include <media/v4l2-event.h> #include <media/v4l2-mem2mem.h> #include <media/videobuf2-dma-contig.h> -#include <linux/pm_runtime.h> #include "mtk_vcodec_drv.h" #include "mtk_vcodec_enc.h" diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index 97e0dc3f0cdb..f993f349b66b 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -160,7 +160,7 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) struct device *dev = camss->dev; struct vfe_device *vfe = &camss->vfe[csid->id]; u32 version = camss->version; - int ret; + int ret = 0; if (on) { if (version == CAMSS_8250 || version == CAMSS_845) { @@ -173,7 +173,8 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) if (ret < 0) return ret; - ret = csid->vdda ? regulator_enable(csid->vdda) : 0; + ret = regulator_bulk_enable(csid->num_supplies, + csid->supplies); if (ret < 0) { pm_runtime_put_sync(dev); return ret; @@ -181,16 +182,16 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) ret = csid_set_clock_rates(csid); if (ret < 0) { - if (csid->vdda) - regulator_disable(csid->vdda); + regulator_bulk_disable(csid->num_supplies, + csid->supplies); pm_runtime_put_sync(dev); return ret; } ret = camss_enable_clocks(csid->nclocks, csid->clock, dev); if (ret < 0) { - if (csid->vdda) - regulator_disable(csid->vdda); + regulator_bulk_disable(csid->num_supplies, + csid->supplies); pm_runtime_put_sync(dev); return ret; } @@ -201,8 +202,8 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) if (ret < 0) { disable_irq(csid->irq); camss_disable_clocks(csid->nclocks, csid->clock); - if (csid->vdda) - regulator_disable(csid->vdda); + regulator_bulk_disable(csid->num_supplies, + csid->supplies); pm_runtime_put_sync(dev); return ret; } @@ -211,7 +212,8 @@ static int csid_set_power(struct v4l2_subdev *sd, int on) } else { disable_irq(csid->irq); camss_disable_clocks(csid->nclocks, csid->clock); - ret = csid->vdda ? regulator_disable(csid->vdda) : 0; + regulator_bulk_disable(csid->num_supplies, + csid->supplies); pm_runtime_put_sync(dev); if (version == CAMSS_8250 || version == CAMSS_845) vfe_put(vfe); @@ -656,15 +658,28 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, } /* Regulator */ + for (i = 0; i < ARRAY_SIZE(res->regulators); i++) { + if (res->regulators[i]) + csid->num_supplies++; + } - csid->vdda = NULL; - if (res->regulator[0]) - csid->vdda = devm_regulator_get(dev, res->regulator[0]); - if (IS_ERR(csid->vdda)) { - dev_err(dev, "could not get regulator\n"); - return PTR_ERR(csid->vdda); + if (csid->num_supplies) { + csid->supplies = devm_kmalloc_array(camss->dev, + csid->num_supplies, + sizeof(csid->supplies), + GFP_KERNEL); + if (!csid->supplies) + return -ENOMEM; } + for (i = 0; i < csid->num_supplies; i++) + csid->supplies[i].supply = res->regulators[i]; + + ret = devm_regulator_bulk_get(camss->dev, csid->num_supplies, + csid->supplies); + if (ret) + return ret; + init_completion(&csid->reset_complete); return 0; diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index 17a50fa426be..f06040e44c51 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -152,7 +152,8 @@ struct csid_device { char irq_name[30]; struct camss_clock *clock; int nclocks; - struct regulator *vdda; + struct regulator_bulk_data *supplies; + int num_supplies; struct completion reset_complete; struct csid_testgen_config testgen; struct csid_phy_config phy; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 04be5e71feca..79ad82e233cb 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -34,7 +34,7 @@ static const struct resources csiphy_res_8x16[] = { /* CSIPHY0 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, .clock_rate = { { 0 }, { 0 }, @@ -46,7 +46,7 @@ static const struct resources csiphy_res_8x16[] = { /* CSIPHY1 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, .clock_rate = { { 0 }, { 0 }, @@ -60,7 +60,7 @@ static const struct resources csiphy_res_8x16[] = { static const struct resources csid_res_8x16[] = { /* CSID0 */ { - .regulator = { "vdda" }, + .regulators = { "vdda" }, .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, .clock_rate = { { 0 }, @@ -77,7 +77,7 @@ static const struct resources csid_res_8x16[] = { /* CSID1 */ { - .regulator = { "vdda" }, + .regulators = { "vdda" }, .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, .clock_rate = { { 0 }, @@ -107,7 +107,7 @@ static const struct resources_ispif ispif_res_8x16 = { static const struct resources vfe_res_8x16[] = { /* VFE0 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "vfe0", "csi_vfe0", "vfe_ahb", "vfe_axi", "ahb" }, .clock_rate = { { 0 }, @@ -129,7 +129,7 @@ static const struct resources vfe_res_8x16[] = { static const struct resources csiphy_res_8x96[] = { /* CSIPHY0 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer" }, .clock_rate = { { 0 }, { 0 }, @@ -141,7 +141,7 @@ static const struct resources csiphy_res_8x96[] = { /* CSIPHY1 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer" }, .clock_rate = { { 0 }, { 0 }, @@ -153,7 +153,7 @@ static const struct resources csiphy_res_8x96[] = { /* CSIPHY2 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer" }, .clock_rate = { { 0 }, { 0 }, @@ -167,7 +167,7 @@ static const struct resources csiphy_res_8x96[] = { static const struct resources csid_res_8x96[] = { /* CSID0 */ { - .regulator = { "vdda" }, + .regulators = { "vdda" }, .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", "csi0", "csi0_phy", "csi0_pix", "csi0_rdi" }, .clock_rate = { { 0 }, @@ -184,7 +184,7 @@ static const struct resources csid_res_8x96[] = { /* CSID1 */ { - .regulator = { "vdda" }, + .regulators = { "vdda" }, .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", "csi1", "csi1_phy", "csi1_pix", "csi1_rdi" }, .clock_rate = { { 0 }, @@ -201,7 +201,7 @@ static const struct resources csid_res_8x96[] = { /* CSID2 */ { - .regulator = { "vdda" }, + .regulators = { "vdda" }, .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", "csi2", "csi2_phy", "csi2_pix", "csi2_rdi" }, .clock_rate = { { 0 }, @@ -218,7 +218,7 @@ static const struct resources csid_res_8x96[] = { /* CSID3 */ { - .regulator = { "vdda" }, + .regulators = { "vdda" }, .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", "csi3", "csi3_phy", "csi3_pix", "csi3_rdi" }, .clock_rate = { { 0 }, @@ -249,7 +249,7 @@ static const struct resources_ispif ispif_res_8x96 = { static const struct resources vfe_res_8x96[] = { /* VFE0 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb", "vfe0_ahb", "vfe_axi", "vfe0_stream"}, .clock_rate = { { 0 }, @@ -267,7 +267,7 @@ static const struct resources vfe_res_8x96[] = { /* VFE1 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb", "vfe1_ahb", "vfe_axi", "vfe1_stream"}, .clock_rate = { { 0 }, @@ -287,7 +287,7 @@ static const struct resources vfe_res_8x96[] = { static const struct resources csiphy_res_660[] = { /* CSIPHY0 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy0_timer", "csi0_phy", "csiphy_ahb2crif" }, .clock_rate = { { 0 }, @@ -301,7 +301,7 @@ static const struct resources csiphy_res_660[] = { /* CSIPHY1 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy1_timer", "csi1_phy", "csiphy_ahb2crif" }, .clock_rate = { { 0 }, @@ -315,7 +315,7 @@ static const struct resources csiphy_res_660[] = { /* CSIPHY2 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "top_ahb", "ispif_ahb", "ahb", "csiphy2_timer", "csi2_phy", "csiphy_ahb2crif" }, .clock_rate = { { 0 }, @@ -331,7 +331,7 @@ static const struct resources csiphy_res_660[] = { static const struct resources csid_res_660[] = { /* CSID0 */ { - .regulator = { "vdda", "vdd_sec" }, + .regulators = { "vdda", "vdd_sec" }, .clock = { "top_ahb", "ispif_ahb", "csi0_ahb", "ahb", "csi0", "csi0_phy", "csi0_pix", "csi0_rdi", "cphy_csid0" }, @@ -351,7 +351,7 @@ static const struct resources csid_res_660[] = { /* CSID1 */ { - .regulator = { "vdda", "vdd_sec" }, + .regulators = { "vdda", "vdd_sec" }, .clock = { "top_ahb", "ispif_ahb", "csi1_ahb", "ahb", "csi1", "csi1_phy", "csi1_pix", "csi1_rdi", "cphy_csid1" }, @@ -371,7 +371,7 @@ static const struct resources csid_res_660[] = { /* CSID2 */ { - .regulator = { "vdda", "vdd_sec" }, + .regulators = { "vdda", "vdd_sec" }, .clock = { "top_ahb", "ispif_ahb", "csi2_ahb", "ahb", "csi2", "csi2_phy", "csi2_pix", "csi2_rdi", "cphy_csid2" }, @@ -391,7 +391,7 @@ static const struct resources csid_res_660[] = { /* CSID3 */ { - .regulator = { "vdda", "vdd_sec" }, + .regulators = { "vdda", "vdd_sec" }, .clock = { "top_ahb", "ispif_ahb", "csi3_ahb", "ahb", "csi3", "csi3_phy", "csi3_pix", "csi3_rdi", "cphy_csid3" }, @@ -425,7 +425,7 @@ static const struct resources_ispif ispif_res_660 = { static const struct resources vfe_res_660[] = { /* VFE0 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "throttle_axi", "top_ahb", "ahb", "vfe0", "csi_vfe0", "vfe_ahb", "vfe0_ahb", "vfe_axi", "vfe0_stream"}, @@ -446,7 +446,7 @@ static const struct resources vfe_res_660[] = { /* VFE1 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "throttle_axi", "top_ahb", "ahb", "vfe1", "csi_vfe1", "vfe_ahb", "vfe1_ahb", "vfe_axi", "vfe1_stream"}, @@ -469,7 +469,7 @@ static const struct resources vfe_res_660[] = { static const struct resources csiphy_res_845[] = { /* CSIPHY0 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", "cpas_ahb", "cphy_rx_src", "csiphy0", "csiphy0_timer_src", "csiphy0_timer" }, @@ -487,7 +487,7 @@ static const struct resources csiphy_res_845[] = { /* CSIPHY1 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", "cpas_ahb", "cphy_rx_src", "csiphy1", "csiphy1_timer_src", "csiphy1_timer" }, @@ -505,7 +505,7 @@ static const struct resources csiphy_res_845[] = { /* CSIPHY2 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", "cpas_ahb", "cphy_rx_src", "csiphy2", "csiphy2_timer_src", "csiphy2_timer" }, @@ -523,7 +523,7 @@ static const struct resources csiphy_res_845[] = { /* CSIPHY3 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi", "soc_ahb", "slow_ahb_src", "cpas_ahb", "cphy_rx_src", "csiphy3", "csiphy3_timer_src", "csiphy3_timer" }, @@ -543,7 +543,7 @@ static const struct resources csiphy_res_845[] = { static const struct resources csid_res_845[] = { /* CSID0 */ { - .regulator = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", "soc_ahb", "vfe0", "vfe0_src", "vfe0_cphy_rx", "csi0", @@ -563,7 +563,7 @@ static const struct resources csid_res_845[] = { /* CSID1 */ { - .regulator = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", "soc_ahb", "vfe1", "vfe1_src", "vfe1_cphy_rx", "csi1", @@ -583,7 +583,7 @@ static const struct resources csid_res_845[] = { /* CSID2 */ { - .regulator = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "cpas_ahb", "cphy_rx_src", "slow_ahb_src", "soc_ahb", "vfe_lite", "vfe_lite_src", "vfe_lite_cphy_rx", "csi2", @@ -605,7 +605,7 @@ static const struct resources csid_res_845[] = { static const struct resources vfe_res_845[] = { /* VFE0 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src", "soc_ahb", "vfe0", "vfe0_axi", "vfe0_src", "csi0", @@ -625,7 +625,7 @@ static const struct resources vfe_res_845[] = { /* VFE1 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src", "soc_ahb", "vfe1", "vfe1_axi", "vfe1_src", "csi1", @@ -645,7 +645,7 @@ static const struct resources vfe_res_845[] = { /* VFE-lite */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi", "cpas_ahb", "slow_ahb_src", "soc_ahb", "vfe_lite", "vfe_lite_src", "csi2", @@ -666,7 +666,7 @@ static const struct resources vfe_res_845[] = { static const struct resources csiphy_res_8250[] = { /* CSIPHY0 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "csiphy0", "csiphy0_timer" }, .clock_rate = { { 400000000 }, { 300000000 } }, @@ -675,7 +675,7 @@ static const struct resources csiphy_res_8250[] = { }, /* CSIPHY1 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "csiphy1", "csiphy1_timer" }, .clock_rate = { { 400000000 }, { 300000000 } }, @@ -684,7 +684,7 @@ static const struct resources csiphy_res_8250[] = { }, /* CSIPHY2 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "csiphy2", "csiphy2_timer" }, .clock_rate = { { 400000000 }, { 300000000 } }, @@ -693,7 +693,7 @@ static const struct resources csiphy_res_8250[] = { }, /* CSIPHY3 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "csiphy3", "csiphy3_timer" }, .clock_rate = { { 400000000 }, { 300000000 } }, @@ -702,7 +702,7 @@ static const struct resources csiphy_res_8250[] = { }, /* CSIPHY4 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "csiphy4", "csiphy4_timer" }, .clock_rate = { { 400000000 }, { 300000000 } }, @@ -711,7 +711,7 @@ static const struct resources csiphy_res_8250[] = { }, /* CSIPHY5 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "csiphy5", "csiphy5_timer" }, .clock_rate = { { 400000000 }, { 300000000 } }, @@ -723,7 +723,7 @@ static const struct resources csiphy_res_8250[] = { static const struct resources csid_res_8250[] = { /* CSID0 */ { - .regulator = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0", "vfe0_areg", "vfe0_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, @@ -735,7 +735,7 @@ static const struct resources csid_res_8250[] = { }, /* CSID1 */ { - .regulator = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1", "vfe1_areg", "vfe1_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, @@ -747,7 +747,7 @@ static const struct resources csid_res_8250[] = { }, /* CSID2 */ { - .regulator = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, @@ -758,7 +758,7 @@ static const struct resources csid_res_8250[] = { }, /* CSID3 */ { - .regulator = { NULL }, + .regulators = { "vdda-phy", "vdda-pll" }, .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx", "vfe_lite", "vfe_lite_ahb" }, .clock_rate = { { 400000000 }, { 400000000 }, @@ -772,7 +772,7 @@ static const struct resources csid_res_8250[] = { static const struct resources vfe_res_8250[] = { /* VFE0 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", "camnoc_axi", "vfe0_ahb", "vfe0_areg", "vfe0", "vfe0_axi", "cam_hf_axi" }, @@ -790,7 +790,7 @@ static const struct resources vfe_res_8250[] = { }, /* VFE1 */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", "camnoc_axi", "vfe1_ahb", "vfe1_areg", "vfe1", "vfe1_axi", "cam_hf_axi" }, @@ -808,7 +808,7 @@ static const struct resources vfe_res_8250[] = { }, /* VFE2 (lite) */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi", "vfe_lite", "cam_hf_axi" }, @@ -825,7 +825,7 @@ static const struct resources vfe_res_8250[] = { }, /* VFE3 (lite) */ { - .regulator = { NULL }, + .regulators = {}, .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", "camnoc_axi", "vfe_lite_ahb", "vfe_lite_axi", "vfe_lite", "cam_hf_axi" }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 9c644e638a94..c9b3e0df5be8 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -42,7 +42,7 @@ #define CAMSS_RES_MAX 17 struct resources { - char *regulator[CAMSS_RES_MAX]; + char *regulators[CAMSS_RES_MAX]; char *clock[CAMSS_RES_MAX]; u32 clock_rate[CAMSS_RES_MAX][CAMSS_RES_MAX]; char *reg[CAMSS_RES_MAX]; diff --git a/drivers/media/platform/qcom/venus/core.h b/drivers/media/platform/qcom/venus/core.h index 7c3bac01cd49..c3023340d95c 100644 --- a/drivers/media/platform/qcom/venus/core.h +++ b/drivers/media/platform/qcom/venus/core.h @@ -127,6 +127,7 @@ struct venus_format { * @done: a completion for sync HFI operations * @error: an error returned during last HFI sync operations * @sys_error: an error flag that signal system error event + * @sys_err_done: a waitqueue to wait for system error recovery end * @core_ops: the core operations * @pm_ops: a pointer to pm operations * @pm_lock: a lock for PM operations @@ -346,6 +347,7 @@ enum venus_inst_modes { * @width: current capture width * @height: current capture height * @crop: current crop rectangle + * @fw_min_cnt: firmware minimum buffer count * @out_width: current output width * @out_height: current output height * @colorspace: current color space @@ -390,6 +392,8 @@ enum venus_inst_modes { * @pic_struct: bitstream progressive vs interlaced * @next_buf_last: a flag to mark next queued capture buffer as last * @drain_active: Drain sequence is in progress + * @flags: bitmask flags describing current instance mode + * @dpb_ids: DPB buffer ID's */ struct venus_inst { struct list_head list; diff --git a/drivers/media/platform/qcom/venus/helpers.c b/drivers/media/platform/qcom/venus/helpers.c index 84c3a511ec31..0bca95d01650 100644 --- a/drivers/media/platform/qcom/venus/helpers.c +++ b/drivers/media/platform/qcom/venus/helpers.c @@ -189,7 +189,6 @@ int venus_helper_alloc_dpb_bufs(struct venus_inst *inst) buf->va = dma_alloc_attrs(dev, buf->size, &buf->da, GFP_KERNEL, buf->attrs); if (!buf->va) { - kfree(buf); ret = -ENOMEM; goto fail; } @@ -209,6 +208,7 @@ int venus_helper_alloc_dpb_bufs(struct venus_inst *inst) return 0; fail: + kfree(buf); venus_helper_free_dpb_bufs(inst); return ret; } diff --git a/drivers/media/platform/qcom/venus/hfi_cmds.c b/drivers/media/platform/qcom/venus/hfi_cmds.c index 5aea07307e02..4ecd444050bb 100644 --- a/drivers/media/platform/qcom/venus/hfi_cmds.c +++ b/drivers/media/platform/qcom/venus/hfi_cmds.c @@ -1054,6 +1054,8 @@ static int pkt_session_set_property_1x(struct hfi_session_set_property_pkt *pkt, pkt->shdr.hdr.size += sizeof(u32) + sizeof(*info); break; } + case HFI_PROPERTY_PARAM_VENC_HDR10_PQ_SEI: + return -ENOTSUPP; /* FOLLOWING PROPERTIES ARE NOT IMPLEMENTED IN CORE YET */ case HFI_PROPERTY_CONFIG_BUFFER_REQUIREMENTS: diff --git a/drivers/media/platform/qcom/venus/venc.c b/drivers/media/platform/qcom/venus/venc.c index 84bafc3118cc..adea4c3b8c20 100644 --- a/drivers/media/platform/qcom/venus/venc.c +++ b/drivers/media/platform/qcom/venus/venc.c @@ -662,8 +662,8 @@ static int venc_set_properties(struct venus_inst *inst) ptype = HFI_PROPERTY_PARAM_VENC_H264_TRANSFORM_8X8; h264_transform.enable_type = 0; - if (ctr->profile.h264 == HFI_H264_PROFILE_HIGH || - ctr->profile.h264 == HFI_H264_PROFILE_CONSTRAINED_HIGH) + if (ctr->profile.h264 == V4L2_MPEG_VIDEO_H264_PROFILE_HIGH || + ctr->profile.h264 == V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) h264_transform.enable_type = ctr->h264_8x8_transform; ret = hfi_session_set_property(inst, ptype, &h264_transform); diff --git a/drivers/media/platform/qcom/venus/venc_ctrls.c b/drivers/media/platform/qcom/venus/venc_ctrls.c index 1ada42df314d..ea5805e71c14 100644 --- a/drivers/media/platform/qcom/venus/venc_ctrls.c +++ b/drivers/media/platform/qcom/venus/venc_ctrls.c @@ -320,8 +320,8 @@ static int venc_op_s_ctrl(struct v4l2_ctrl *ctrl) ctr->intra_refresh_period = ctrl->val; break; case V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM: - if (ctr->profile.h264 != HFI_H264_PROFILE_HIGH && - ctr->profile.h264 != HFI_H264_PROFILE_CONSTRAINED_HIGH) + if (ctr->profile.h264 != V4L2_MPEG_VIDEO_H264_PROFILE_HIGH && + ctr->profile.h264 != V4L2_MPEG_VIDEO_H264_PROFILE_CONSTRAINED_HIGH) return -EINVAL; /* @@ -457,7 +457,7 @@ int venc_ctrl_init(struct venus_inst *inst) V4L2_CID_MPEG_VIDEO_H264_I_FRAME_MIN_QP, 1, 51, 1, 1); v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, - V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, 0, 1, 1, 0); + V4L2_CID_MPEG_VIDEO_H264_8X8_TRANSFORM, 0, 1, 1, 1); v4l2_ctrl_new_std(&inst->ctrl_handler, &venc_ctrl_ops, V4L2_CID_MPEG_VIDEO_H264_P_FRAME_MIN_QP, 1, 51, 1, 1); diff --git a/drivers/media/platform/tegra/vde/Makefile b/drivers/media/platform/tegra/vde/Makefile new file mode 100644 index 000000000000..4e96f3305567 --- /dev/null +++ b/drivers/media/platform/tegra/vde/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 +tegra-vde-y := vde.o iommu.o dmabuf-cache.o h264.o v4l2.o +obj-$(CONFIG_VIDEO_TEGRA_VDE) += tegra-vde.o diff --git a/drivers/staging/media/tegra-vde/dmabuf-cache.c b/drivers/media/platform/tegra/vde/dmabuf-cache.c index a98d03419b8f..69c346148070 100644 --- a/drivers/staging/media/tegra-vde/dmabuf-cache.c +++ b/drivers/media/platform/tegra/vde/dmabuf-cache.c @@ -66,9 +66,9 @@ int tegra_vde_dmabuf_cache_map(struct tegra_vde *vde, struct dma_buf_attachment **ap, dma_addr_t *addrp) { - struct device *dev = vde->miscdev.parent; struct dma_buf_attachment *attachment; struct tegra_vde_cache_entry *entry; + struct device *dev = vde->dev; struct sg_table *sgt; struct iova *iova; int err; diff --git a/drivers/media/platform/tegra/vde/h264.c b/drivers/media/platform/tegra/vde/h264.c new file mode 100644 index 000000000000..d8e5534e80c8 --- /dev/null +++ b/drivers/media/platform/tegra/vde/h264.c @@ -0,0 +1,946 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NVIDIA Tegra Video decoder driver + * + * Copyright (C) 2016-2022 Dmitry Osipenko <digetx@gmail.com> + * + */ + +#include <linux/iopoll.h> +#include <linux/pm_runtime.h> +#include <linux/reset.h> +#include <linux/slab.h> + +#include <media/v4l2-h264.h> + +#include "trace.h" +#include "vde.h" + +#define FLAG_B_FRAME 0x1 +#define FLAG_REFERENCE 0x2 + +struct tegra_vde_h264_frame { + unsigned int frame_num; + unsigned int flags; +}; + +struct tegra_vde_h264_decoder_ctx { + unsigned int dpb_frames_nb; + unsigned int dpb_ref_frames_with_earlier_poc_nb; + unsigned int baseline_profile; + unsigned int level_idc; + unsigned int log2_max_pic_order_cnt_lsb; + unsigned int log2_max_frame_num; + unsigned int pic_order_cnt_type; + unsigned int direct_8x8_inference_flag; + unsigned int pic_width_in_mbs; + unsigned int pic_height_in_mbs; + unsigned int pic_init_qp; + unsigned int deblocking_filter_control_present_flag; + unsigned int constrained_intra_pred_flag; + unsigned int chroma_qp_index_offset; + unsigned int pic_order_present_flag; + unsigned int num_ref_idx_l0_active_minus1; + unsigned int num_ref_idx_l1_active_minus1; +}; + +struct h264_reflists { + u8 p[V4L2_H264_NUM_DPB_ENTRIES]; + u8 b0[V4L2_H264_NUM_DPB_ENTRIES]; + u8 b1[V4L2_H264_NUM_DPB_ENTRIES]; +}; + +static int tegra_vde_wait_mbe(struct tegra_vde *vde) +{ + u32 tmp; + + return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp, + tmp >= 0x10, 1, 100); +} + +static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde, + unsigned int refs_nb, + bool setup_refs) +{ + u32 value, frame_idx_enb_mask = 0; + unsigned int frame_idx; + unsigned int idx; + int err; + + tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80); + tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80); + + err = tegra_vde_wait_mbe(vde); + if (err) + return err; + + if (!setup_refs) + return 0; + + for (idx = 0, frame_idx = 1; idx < refs_nb; idx++, frame_idx++) { + tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23), + vde->mbe, 0x80); + tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23), + vde->mbe, 0x80); + + frame_idx_enb_mask |= frame_idx << (6 * (idx % 4)); + + if (idx % 4 == 3 || idx == refs_nb - 1) { + value = 0xC0000000; + value |= (idx >> 2) << 24; + value |= frame_idx_enb_mask; + + tegra_vde_writel(vde, value, vde->mbe, 0x80); + + err = tegra_vde_wait_mbe(vde); + if (err) + return err; + + frame_idx_enb_mask = 0; + } + } + + return 0; +} + +static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val) +{ + tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF), + vde->mbe, 0x80); + tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16), + vde->mbe, 0x80); +} + +static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma) +{ + struct device *dev = vde->dev; + u32 value; + int err; + + err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, + !(value & BIT(2)), 1, 100); + if (err) { + dev_err(dev, "BSEV unknown bit timeout\n"); + return err; + } + + err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, + (value & BSE_ICMDQUE_EMPTY), 1, 100); + if (err) { + dev_err(dev, "BSEV ICMDQUE flush timeout\n"); + return err; + } + + if (!wait_dma) + return 0; + + err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, + !(value & BSE_DMA_BUSY), 1, 1000); + if (err) { + dev_err(dev, "BSEV DMA timeout\n"); + return err; + } + + return 0; +} + +static int tegra_vde_push_to_bsev_icmdqueue(struct tegra_vde *vde, + u32 value, bool wait_dma) +{ + tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR); + + return tegra_vde_wait_bsev(vde, wait_dma); +} + +static void tegra_vde_setup_frameid(struct tegra_vde *vde, + struct tegra_video_frame *frame, + unsigned int frameid, + u32 mbs_width, u32 mbs_height) +{ + u32 y_addr = frame ? frame->y_addr : 0x6CDEAD00; + u32 cb_addr = frame ? frame->cb_addr : 0x6CDEAD00; + u32 cr_addr = frame ? frame->cr_addr : 0x6CDEAD00; + u32 value1 = frame ? ((frame->luma_atoms_pitch << 16) | mbs_height) : 0; + u32 value2 = frame ? ((frame->chroma_atoms_pitch << 6) | 1) : 0; + + tegra_vde_writel(vde, y_addr >> 8, vde->frameid, 0x000 + frameid * 4); + tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4); + tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4); + tegra_vde_writel(vde, value1, vde->frameid, 0x080 + frameid * 4); + tegra_vde_writel(vde, value2, vde->frameid, 0x280 + frameid * 4); +} + +static void tegra_setup_frameidx(struct tegra_vde *vde, + struct tegra_video_frame *frames, + unsigned int frames_nb, + u32 mbs_width, u32 mbs_height) +{ + unsigned int idx; + + for (idx = 0; idx < frames_nb; idx++) + tegra_vde_setup_frameid(vde, &frames[idx], idx, + mbs_width, mbs_height); + + for (; idx < 17; idx++) + tegra_vde_setup_frameid(vde, NULL, idx, 0, 0); +} + +static void tegra_vde_setup_iram_entry(struct tegra_vde *vde, + unsigned int table, + unsigned int row, + u32 value1, u32 value2) +{ + u32 *iram_tables = vde->iram; + + trace_vde_setup_iram_entry(table, row, value1, value2); + + iram_tables[0x20 * table + row * 2 + 0] = value1; + iram_tables[0x20 * table + row * 2 + 1] = value2; +} + +static void tegra_vde_setup_iram_tables(struct tegra_vde *vde, + struct tegra_video_frame *dpb_frames, + unsigned int ref_frames_nb, + unsigned int with_earlier_poc_nb) +{ + struct tegra_video_frame *frame; + int with_later_poc_nb; + u32 value, aux_addr; + unsigned int i, k; + + trace_vde_ref_l0(dpb_frames[0].frame_num); + + for (i = 0; i < 16; i++) { + if (i < ref_frames_nb) { + frame = &dpb_frames[i + 1]; + + aux_addr = frame->aux_addr; + + value = (i + 1) << 26; + value |= !(frame->flags & FLAG_B_FRAME) << 25; + value |= 1 << 24; + value |= frame->frame_num; + } else { + aux_addr = 0x6ADEAD00; + value = 0x3f; + } + + tegra_vde_setup_iram_entry(vde, 0, i, value, aux_addr); + tegra_vde_setup_iram_entry(vde, 1, i, value, aux_addr); + tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); + tegra_vde_setup_iram_entry(vde, 3, i, value, aux_addr); + } + + if (!(dpb_frames[0].flags & FLAG_B_FRAME)) + return; + + if (with_earlier_poc_nb >= ref_frames_nb) + return; + + with_later_poc_nb = ref_frames_nb - with_earlier_poc_nb; + + trace_vde_ref_l1(with_later_poc_nb, with_earlier_poc_nb); + + for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) { + frame = &dpb_frames[k + 1]; + + aux_addr = frame->aux_addr; + + value = (k + 1) << 26; + value |= !(frame->flags & FLAG_B_FRAME) << 25; + value |= 1 << 24; + value |= frame->frame_num; + + tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); + } + + for (k = 0; i < ref_frames_nb; i++, k++) { + frame = &dpb_frames[k + 1]; + + aux_addr = frame->aux_addr; + + value = (k + 1) << 26; + value |= !(frame->flags & FLAG_B_FRAME) << 25; + value |= 1 << 24; + value |= frame->frame_num; + + tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); + } +} + +static int tegra_vde_setup_hw_context(struct tegra_vde *vde, + struct tegra_vde_h264_decoder_ctx *ctx, + struct tegra_video_frame *dpb_frames, + dma_addr_t bitstream_data_addr, + size_t bitstream_data_size, + unsigned int macroblocks_nb) +{ + struct device *dev = vde->dev; + u32 value; + int err; + + tegra_vde_set_bits(vde, 0x000A, vde->sxe, 0xF0); + tegra_vde_set_bits(vde, 0x000B, vde->bsev, CMDQUE_CONTROL); + tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50); + tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0); + tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14); + tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28); + tegra_vde_set_bits(vde, 0x0A00, vde->mce, 0x08); + tegra_vde_set_bits(vde, 0x000A, vde->tfe, 0x00); + tegra_vde_set_bits(vde, 0x0005, vde->vdma, 0x04); + + tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C); + tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00); + tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04); + tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200); + tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04); + tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84); + tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08); + tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54); + tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58); + tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C); + tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10); + tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); + tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG); + tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB); + tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98); + tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C); + + memset(vde->iram + 128, 0, macroblocks_nb / 2); + + tegra_setup_frameidx(vde, dpb_frames, ctx->dpb_frames_nb, + ctx->pic_width_in_mbs, ctx->pic_height_in_mbs); + + tegra_vde_setup_iram_tables(vde, dpb_frames, + ctx->dpb_frames_nb - 1, + ctx->dpb_ref_frames_with_earlier_poc_nb); + + /* + * The IRAM mapping is write-combine, ensure that CPU buffers have + * been flushed at this point. + */ + wmb(); + + tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C); + tegra_vde_writel(vde, bitstream_data_addr + bitstream_data_size, + vde->bsev, 0x54); + + vde->bitstream_data_addr = bitstream_data_addr; + + value = ctx->pic_width_in_mbs << 11 | ctx->pic_height_in_mbs << 3; + + tegra_vde_writel(vde, value, vde->bsev, 0x88); + + err = tegra_vde_wait_bsev(vde, false); + if (err) + return err; + + err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x800003FC, false); + if (err) + return err; + + value = 0x01500000; + value |= ((vde->iram_lists_addr + 512) >> 2) & 0xFFFF; + + err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true); + if (err) + return err; + + err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x840F054C, false); + if (err) + return err; + + err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x80000080, false); + if (err) + return err; + + value = 0x0E340000 | ((vde->iram_lists_addr >> 2) & 0xFFFF); + + err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true); + if (err) + return err; + + value = 0x00800005; + value |= ctx->pic_width_in_mbs << 11; + value |= ctx->pic_height_in_mbs << 3; + + tegra_vde_writel(vde, value, vde->sxe, 0x10); + + value = !ctx->baseline_profile << 17; + value |= ctx->level_idc << 13; + value |= ctx->log2_max_pic_order_cnt_lsb << 7; + value |= ctx->pic_order_cnt_type << 5; + value |= ctx->log2_max_frame_num; + + tegra_vde_writel(vde, value, vde->sxe, 0x40); + + value = ctx->pic_init_qp << 25; + value |= !!(ctx->deblocking_filter_control_present_flag) << 2; + value |= !!ctx->pic_order_present_flag; + + tegra_vde_writel(vde, value, vde->sxe, 0x44); + + value = ctx->chroma_qp_index_offset; + value |= ctx->num_ref_idx_l0_active_minus1 << 5; + value |= ctx->num_ref_idx_l1_active_minus1 << 10; + value |= !!ctx->constrained_intra_pred_flag << 15; + + tegra_vde_writel(vde, value, vde->sxe, 0x48); + + value = 0x0C000000; + value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 24; + + tegra_vde_writel(vde, value, vde->sxe, 0x4C); + + value = 0x03800000; + value |= bitstream_data_size & GENMASK(19, 15); + + tegra_vde_writel(vde, value, vde->sxe, 0x68); + + tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C); + + if (vde->soc->supports_ref_pic_marking) + tegra_vde_writel(vde, vde->secure_bo->dma_addr, vde->sxe, 0x7c); + + value = 0x10000005; + value |= ctx->pic_width_in_mbs << 11; + value |= ctx->pic_height_in_mbs << 3; + + tegra_vde_writel(vde, value, vde->mbe, 0x80); + + value = 0x26800000; + value |= ctx->level_idc << 4; + value |= !ctx->baseline_profile << 1; + value |= !!ctx->direct_8x8_inference_flag; + + tegra_vde_writel(vde, value, vde->mbe, 0x80); + + tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80); + tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80); + tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80); + + value = 0x20000000; + value |= ctx->chroma_qp_index_offset << 8; + + tegra_vde_writel(vde, value, vde->mbe, 0x80); + + err = tegra_vde_setup_mbe_frame_idx(vde, + ctx->dpb_frames_nb - 1, + ctx->pic_order_cnt_type == 0); + if (err) { + dev_err(dev, "MBE frames setup failed %d\n", err); + return err; + } + + tegra_vde_mbe_set_0xa_reg(vde, 0, 0x000009FC); + tegra_vde_mbe_set_0xa_reg(vde, 2, 0x61DEAD00); + tegra_vde_mbe_set_0xa_reg(vde, 4, 0x62DEAD00); + tegra_vde_mbe_set_0xa_reg(vde, 6, 0x63DEAD00); + tegra_vde_mbe_set_0xa_reg(vde, 8, dpb_frames[0].aux_addr); + + value = 0xFC000000; + value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 2; + + if (!ctx->baseline_profile) + value |= !!(dpb_frames[0].flags & FLAG_REFERENCE) << 1; + + tegra_vde_writel(vde, value, vde->mbe, 0x80); + + err = tegra_vde_wait_mbe(vde); + if (err) { + dev_err(dev, "MBE programming failed %d\n", err); + return err; + } + + return 0; +} + +static void tegra_vde_decode_frame(struct tegra_vde *vde, + unsigned int macroblocks_nb) +{ + reinit_completion(&vde->decode_completion); + + tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C); + tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1), + vde->sxe, 0x00); +} + +static int tegra_vde_validate_h264_ctx(struct device *dev, + struct tegra_vde_h264_decoder_ctx *ctx) +{ + if (ctx->dpb_frames_nb == 0 || ctx->dpb_frames_nb > 17) { + dev_err(dev, "Bad DPB size %u\n", ctx->dpb_frames_nb); + return -EINVAL; + } + + if (ctx->level_idc > 15) { + dev_err(dev, "Bad level value %u\n", ctx->level_idc); + return -EINVAL; + } + + if (ctx->pic_init_qp > 52) { + dev_err(dev, "Bad pic_init_qp value %u\n", ctx->pic_init_qp); + return -EINVAL; + } + + if (ctx->log2_max_pic_order_cnt_lsb > 16) { + dev_err(dev, "Bad log2_max_pic_order_cnt_lsb value %u\n", + ctx->log2_max_pic_order_cnt_lsb); + return -EINVAL; + } + + if (ctx->log2_max_frame_num > 16) { + dev_err(dev, "Bad log2_max_frame_num value %u\n", + ctx->log2_max_frame_num); + return -EINVAL; + } + + if (ctx->chroma_qp_index_offset > 31) { + dev_err(dev, "Bad chroma_qp_index_offset value %u\n", + ctx->chroma_qp_index_offset); + return -EINVAL; + } + + if (ctx->pic_order_cnt_type > 2) { + dev_err(dev, "Bad pic_order_cnt_type value %u\n", + ctx->pic_order_cnt_type); + return -EINVAL; + } + + if (ctx->num_ref_idx_l0_active_minus1 > 15) { + dev_err(dev, "Bad num_ref_idx_l0_active_minus1 value %u\n", + ctx->num_ref_idx_l0_active_minus1); + return -EINVAL; + } + + if (ctx->num_ref_idx_l1_active_minus1 > 15) { + dev_err(dev, "Bad num_ref_idx_l1_active_minus1 value %u\n", + ctx->num_ref_idx_l1_active_minus1); + return -EINVAL; + } + + if (!ctx->pic_width_in_mbs || ctx->pic_width_in_mbs > 127) { + dev_err(dev, "Bad pic_width_in_mbs value %u\n", + ctx->pic_width_in_mbs); + return -EINVAL; + } + + if (!ctx->pic_height_in_mbs || ctx->pic_height_in_mbs > 127) { + dev_err(dev, "Bad pic_height_in_mbs value %u\n", + ctx->pic_height_in_mbs); + return -EINVAL; + } + + return 0; +} + +static int tegra_vde_decode_begin(struct tegra_vde *vde, + struct tegra_vde_h264_decoder_ctx *ctx, + struct tegra_video_frame *dpb_frames, + dma_addr_t bitstream_data_addr, + size_t bitstream_data_size) +{ + struct device *dev = vde->dev; + unsigned int macroblocks_nb; + int err; + + err = mutex_lock_interruptible(&vde->lock); + if (err) + return err; + + err = pm_runtime_resume_and_get(dev); + if (err < 0) + goto unlock; + + /* + * We rely on the VDE registers reset value, otherwise VDE + * causes bus lockup. + */ + err = reset_control_assert(vde->rst_mc); + if (err) { + dev_err(dev, "DEC start: Failed to assert MC reset: %d\n", + err); + goto put_runtime_pm; + } + + err = reset_control_reset(vde->rst); + if (err) { + dev_err(dev, "DEC start: Failed to reset HW: %d\n", err); + goto put_runtime_pm; + } + + err = reset_control_deassert(vde->rst_mc); + if (err) { + dev_err(dev, "DEC start: Failed to deassert MC reset: %d\n", + err); + goto put_runtime_pm; + } + + macroblocks_nb = ctx->pic_width_in_mbs * ctx->pic_height_in_mbs; + + err = tegra_vde_setup_hw_context(vde, ctx, dpb_frames, + bitstream_data_addr, + bitstream_data_size, + macroblocks_nb); + if (err) + goto put_runtime_pm; + + tegra_vde_decode_frame(vde, macroblocks_nb); + + return 0; + +put_runtime_pm: + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + +unlock: + mutex_unlock(&vde->lock); + + return err; +} + +static void tegra_vde_decode_abort(struct tegra_vde *vde) +{ + struct device *dev = vde->dev; + int err; + + /* + * At first reset memory client to avoid resetting VDE HW in the + * middle of DMA which could result into memory corruption or hang + * the whole system. + */ + err = reset_control_assert(vde->rst_mc); + if (err) + dev_err(dev, "DEC end: Failed to assert MC reset: %d\n", err); + + err = reset_control_assert(vde->rst); + if (err) + dev_err(dev, "DEC end: Failed to assert HW reset: %d\n", err); + + pm_runtime_mark_last_busy(dev); + pm_runtime_put_autosuspend(dev); + + mutex_unlock(&vde->lock); +} + +static int tegra_vde_decode_end(struct tegra_vde *vde) +{ + unsigned int read_bytes, macroblocks_nb; + struct device *dev = vde->dev; + dma_addr_t bsev_ptr; + long timeout; + int ret; + + timeout = wait_for_completion_interruptible_timeout( + &vde->decode_completion, msecs_to_jiffies(1000)); + if (timeout == 0) { + bsev_ptr = tegra_vde_readl(vde, vde->bsev, 0x10); + macroblocks_nb = tegra_vde_readl(vde, vde->sxe, 0xC8) & 0x1FFF; + read_bytes = bsev_ptr ? bsev_ptr - vde->bitstream_data_addr : 0; + + dev_err(dev, "Decoding failed: read 0x%X bytes, %u macroblocks parsed\n", + read_bytes, macroblocks_nb); + + ret = -EIO; + } else if (timeout < 0) { + ret = timeout; + } else { + ret = 0; + } + + tegra_vde_decode_abort(vde); + + return ret; +} + +static struct vb2_buffer *get_ref_buf(struct tegra_ctx *ctx, + struct vb2_v4l2_buffer *dst, + unsigned int dpb_idx) +{ + const struct v4l2_h264_dpb_entry *dpb = ctx->h264.decode_params->dpb; + struct vb2_queue *cap_q = &ctx->fh.m2m_ctx->cap_q_ctx.q; + int buf_idx = -1; + + if (dpb[dpb_idx].flags & V4L2_H264_DPB_ENTRY_FLAG_ACTIVE) + buf_idx = vb2_find_timestamp(cap_q, + dpb[dpb_idx].reference_ts, 0); + + /* + * If a DPB entry is unused or invalid, address of current destination + * buffer is returned. + */ + if (buf_idx < 0) + return &dst->vb2_buf; + + return vb2_get_buffer(cap_q, buf_idx); +} + +static int tegra_vde_validate_vb_size(struct tegra_ctx *ctx, + struct vb2_buffer *vb, + unsigned int plane_id, + size_t min_size) +{ + u64 offset = vb->planes[plane_id].data_offset; + struct device *dev = ctx->vde->dev; + + if (offset + min_size > vb2_plane_size(vb, plane_id)) { + dev_err(dev, "Too small plane[%u] size %lu @0x%llX, should be at least %zu\n", + plane_id, vb2_plane_size(vb, plane_id), offset, min_size); + return -EINVAL; + } + + return 0; +} + +static int tegra_vde_h264_setup_frame(struct tegra_ctx *ctx, + struct tegra_vde_h264_decoder_ctx *h264, + struct v4l2_h264_reflist_builder *b, + struct vb2_buffer *vb, + unsigned int ref_id, + unsigned int id) +{ + struct v4l2_pix_format_mplane *pixfmt = &ctx->decoded_fmt.fmt.pix_mp; + struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); + struct tegra_ctx_h264 *h = &ctx->h264; + struct tegra_vde *vde = ctx->vde; + struct device *dev = vde->dev; + unsigned int cstride, lstride; + unsigned int flags = 0; + size_t lsize, csize; + int err, frame_num; + + lsize = h264->pic_width_in_mbs * 16 * h264->pic_height_in_mbs * 16; + csize = h264->pic_width_in_mbs * 8 * h264->pic_height_in_mbs * 8; + lstride = pixfmt->plane_fmt[0].bytesperline; + cstride = pixfmt->plane_fmt[1].bytesperline; + + err = tegra_vde_validate_vb_size(ctx, vb, 0, lsize); + if (err) + return err; + + err = tegra_vde_validate_vb_size(ctx, vb, 1, csize); + if (err) + return err; + + err = tegra_vde_validate_vb_size(ctx, vb, 2, csize); + if (err) + return err; + + if (!tb->aux || tb->aux->size < csize) { + dev_err(dev, "Too small aux size %zd, should be at least %zu\n", + tb->aux ? tb->aux->size : -1, csize); + return -EINVAL; + } + + if (id == 0) { + frame_num = h->decode_params->frame_num; + + if (h->decode_params->nal_ref_idc) + flags |= FLAG_REFERENCE; + } else { + frame_num = b->refs[ref_id].frame_num; + } + + if (tb->b_frame) + flags |= FLAG_B_FRAME; + + vde->frames[id].flags = flags; + vde->frames[id].y_addr = tb->dma_addr[0]; + vde->frames[id].cb_addr = tb->dma_addr[1]; + vde->frames[id].cr_addr = tb->dma_addr[2]; + vde->frames[id].aux_addr = tb->aux->dma_addr; + vde->frames[id].frame_num = frame_num & 0x7fffff; + vde->frames[id].luma_atoms_pitch = lstride / VDE_ATOM; + vde->frames[id].chroma_atoms_pitch = cstride / VDE_ATOM; + + return 0; +} + +static int tegra_vde_h264_setup_frames(struct tegra_ctx *ctx, + struct tegra_vde_h264_decoder_ctx *h264) +{ + struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + struct vb2_v4l2_buffer *dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); + const struct v4l2_h264_dpb_entry *dpb = ctx->h264.decode_params->dpb; + struct tegra_m2m_buffer *tb = vb_to_tegra_buf(&dst->vb2_buf); + struct tegra_ctx_h264 *h = &ctx->h264; + struct v4l2_h264_reflist_builder b; + struct h264_reflists reflists; + struct vb2_buffer *ref; + unsigned int i; + u8 *dpb_id; + int err; + + /* + * Tegra hardware requires information about frame's type, assuming + * that frame consists of the same type slices. Userspace must tag + * frame's type appropriately. + * + * Decoding of a non-uniform frames isn't supported by hardware and + * require software preprocessing that we don't implement. Decoding + * is expected to fail in this case. Such video streams are rare in + * practice, so not a big deal. + * + * If userspace doesn't tell us frame's type, then we will try decode + * as-is. + */ + v4l2_m2m_buf_copy_metadata(src, dst, true); + + if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BFRAME) + tb->b_frame = true; + else + tb->b_frame = false; + + err = tegra_vde_h264_setup_frame(ctx, h264, NULL, &dst->vb2_buf, 0, + h264->dpb_frames_nb++); + if (err) + return err; + + if (!(h->decode_params->flags & (V4L2_H264_DECODE_PARAM_FLAG_PFRAME | + V4L2_H264_DECODE_PARAM_FLAG_BFRAME))) + return 0; + + v4l2_h264_init_reflist_builder(&b, h->decode_params, h->sps, dpb); + + if (h->decode_params->flags & V4L2_H264_DECODE_PARAM_FLAG_BFRAME) { + v4l2_h264_build_b_ref_lists(&b, reflists.b0, reflists.b1); + dpb_id = reflists.b0; + } else { + v4l2_h264_build_p_ref_list(&b, reflists.p); + dpb_id = reflists.p; + } + + for (i = 0; i < b.num_valid; i++) { + ref = get_ref_buf(ctx, dst, dpb_id[i]); + + err = tegra_vde_h264_setup_frame(ctx, h264, &b, ref, dpb_id[i], + h264->dpb_frames_nb++); + if (err) + return err; + + if (b.refs[dpb_id[i]].pic_order_count < b.cur_pic_order_count) + h264->dpb_ref_frames_with_earlier_poc_nb++; + } + + return 0; +} + +static unsigned int to_tegra_vde_h264_level_idc(unsigned int level_idc) +{ + switch (level_idc) { + case 11: + return 2; + case 12: + return 3; + case 13: + return 4; + case 20: + return 5; + case 21: + return 6; + case 22: + return 7; + case 30: + return 8; + case 31: + return 9; + case 32: + return 10; + case 40: + return 11; + case 41: + return 12; + case 42: + return 13; + case 50: + return 14; + default: + break; + } + + return 15; +} + +static int tegra_vde_h264_setup_context(struct tegra_ctx *ctx, + struct tegra_vde_h264_decoder_ctx *h264) +{ + struct tegra_ctx_h264 *h = &ctx->h264; + struct tegra_vde *vde = ctx->vde; + struct device *dev = vde->dev; + int err; + + memset(h264, 0, sizeof(*h264)); + memset(vde->frames, 0, sizeof(vde->frames)); + + tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_DECODE_PARAMS); + tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_SPS); + tegra_vde_prepare_control_data(ctx, V4L2_CID_STATELESS_H264_PPS); + + /* CABAC unsupported by hardware, requires software preprocessing */ + if (h->pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) + return -EOPNOTSUPP; + + if (h->sps->profile_idc == 66) + h264->baseline_profile = 1; + + if (h->sps->flags & V4L2_H264_SPS_FLAG_DIRECT_8X8_INFERENCE) + h264->direct_8x8_inference_flag = 1; + + if (h->pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) + h264->constrained_intra_pred_flag = 1; + + if (h->pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) + h264->deblocking_filter_control_present_flag = 1; + + if (h->pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT) + h264->pic_order_present_flag = 1; + + h264->level_idc = to_tegra_vde_h264_level_idc(h->sps->level_idc); + h264->log2_max_pic_order_cnt_lsb = h->sps->log2_max_pic_order_cnt_lsb_minus4 + 4; + h264->log2_max_frame_num = h->sps->log2_max_frame_num_minus4 + 4; + h264->pic_order_cnt_type = h->sps->pic_order_cnt_type; + h264->pic_width_in_mbs = h->sps->pic_width_in_mbs_minus1 + 1; + h264->pic_height_in_mbs = h->sps->pic_height_in_map_units_minus1 + 1; + + h264->num_ref_idx_l0_active_minus1 = h->pps->num_ref_idx_l0_default_active_minus1; + h264->num_ref_idx_l1_active_minus1 = h->pps->num_ref_idx_l1_default_active_minus1; + h264->chroma_qp_index_offset = h->pps->chroma_qp_index_offset & 0x1f; + h264->pic_init_qp = h->pps->pic_init_qp_minus26 + 26; + + err = tegra_vde_h264_setup_frames(ctx, h264); + if (err) + return err; + + err = tegra_vde_validate_h264_ctx(dev, h264); + if (err) + return err; + + return 0; +} + +int tegra_vde_h264_decode_run(struct tegra_ctx *ctx) +{ + struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + struct tegra_m2m_buffer *bitstream = vb_to_tegra_buf(&src->vb2_buf); + size_t bitstream_size = vb2_get_plane_payload(&src->vb2_buf, 0); + struct tegra_vde_h264_decoder_ctx h264; + struct tegra_vde *vde = ctx->vde; + int err; + + err = tegra_vde_h264_setup_context(ctx, &h264); + if (err) + return err; + + err = tegra_vde_decode_begin(vde, &h264, vde->frames, + bitstream->dma_addr[0], + bitstream_size); + if (err) + return err; + + return 0; +} + +int tegra_vde_h264_decode_wait(struct tegra_ctx *ctx) +{ + return tegra_vde_decode_end(ctx->vde); +} diff --git a/drivers/staging/media/tegra-vde/iommu.c b/drivers/media/platform/tegra/vde/iommu.c index adf8dc7ee25c..5521ed3e465f 100644 --- a/drivers/staging/media/tegra-vde/iommu.c +++ b/drivers/media/platform/tegra/vde/iommu.c @@ -60,7 +60,7 @@ void tegra_vde_iommu_unmap(struct tegra_vde *vde, struct iova *iova) int tegra_vde_iommu_init(struct tegra_vde *vde) { - struct device *dev = vde->miscdev.parent; + struct device *dev = vde->dev; struct iova *iova; unsigned long order; unsigned long shift; diff --git a/drivers/staging/media/tegra-vde/trace.h b/drivers/media/platform/tegra/vde/trace.h index e5714107db58..77358ddfdb8f 100644 --- a/drivers/staging/media/tegra-vde/trace.h +++ b/drivers/media/platform/tegra/vde/trace.h @@ -90,6 +90,6 @@ TRACE_EVENT(vde_ref_l1, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH ../../drivers/staging/media/tegra-vde +#define TRACE_INCLUDE_PATH ../../drivers/media/platform/tegra/vde #define TRACE_INCLUDE_FILE trace #include <trace/define_trace.h> diff --git a/drivers/media/platform/tegra/vde/v4l2.c b/drivers/media/platform/tegra/vde/v4l2.c new file mode 100644 index 000000000000..bd8c207d5b54 --- /dev/null +++ b/drivers/media/platform/tegra/vde/v4l2.c @@ -0,0 +1,1018 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NVIDIA Tegra Video decoder driver + * + * Copyright (C) 2019-2022 Dmitry Osipenko <digetx@gmail.com> + * + * Based on Cedrus driver by Bootlin. + * Copyright (C) 2016 Florent Revest <florent.revest@free-electrons.com> + * Copyright (C) 2018 Paul Kocialkowski <paul.kocialkowski@bootlin.com> + * + * Based on Rockchip driver by Collabora. + * Copyright (C) 2019 Boris Brezillon <boris.brezillon@collabora.com> + */ + +#include <linux/err.h> +#include <linux/slab.h> + +#include "vde.h" + +static const struct v4l2_ctrl_config ctrl_cfgs[] = { + { .id = V4L2_CID_STATELESS_H264_DECODE_PARAMS, }, + { .id = V4L2_CID_STATELESS_H264_SPS, }, + { .id = V4L2_CID_STATELESS_H264_PPS, }, + { + .id = V4L2_CID_STATELESS_H264_DECODE_MODE, + .min = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, + .max = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, + .def = V4L2_STATELESS_H264_DECODE_MODE_FRAME_BASED, + }, + { + .id = V4L2_CID_STATELESS_H264_START_CODE, + .min = V4L2_STATELESS_H264_START_CODE_ANNEX_B, + .max = V4L2_STATELESS_H264_START_CODE_ANNEX_B, + .def = V4L2_STATELESS_H264_START_CODE_ANNEX_B, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_PROFILE, + .min = V4L2_MPEG_VIDEO_H264_PROFILE_BASELINE, + .max = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, + .def = V4L2_MPEG_VIDEO_H264_PROFILE_MAIN, + }, + { + .id = V4L2_CID_MPEG_VIDEO_H264_LEVEL, + .min = V4L2_MPEG_VIDEO_H264_LEVEL_1_0, + .max = V4L2_MPEG_VIDEO_H264_LEVEL_5_1, + }, +}; + +static inline struct tegra_ctx *fh_to_tegra_ctx(struct v4l2_fh *fh) +{ + return container_of(fh, struct tegra_ctx, fh); +} + +static void tegra_set_control_data(struct tegra_ctx *ctx, void *data, u32 id) +{ + switch (id) { + case V4L2_CID_STATELESS_H264_DECODE_PARAMS: + ctx->h264.decode_params = data; + break; + case V4L2_CID_STATELESS_H264_SPS: + ctx->h264.sps = data; + break; + case V4L2_CID_STATELESS_H264_PPS: + ctx->h264.pps = data; + break; + } +} + +void tegra_vde_prepare_control_data(struct tegra_ctx *ctx, u32 id) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(ctrl_cfgs); i++) { + if (ctx->ctrls[i]->id == id) { + tegra_set_control_data(ctx, ctx->ctrls[i]->p_cur.p, id); + return; + } + } + + tegra_set_control_data(ctx, NULL, id); +} + +static int tegra_queue_setup(struct vb2_queue *vq, + unsigned int *nbufs, + unsigned int *num_planes, + unsigned int sizes[], + struct device *alloc_devs[]) +{ + struct tegra_ctx *ctx = vb2_get_drv_priv(vq); + struct v4l2_format *f; + unsigned int i; + + if (V4L2_TYPE_IS_OUTPUT(vq->type)) + f = &ctx->coded_fmt; + else + f = &ctx->decoded_fmt; + + if (*num_planes) { + if (*num_planes != f->fmt.pix_mp.num_planes) + return -EINVAL; + + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) { + if (sizes[i] < f->fmt.pix_mp.plane_fmt[i].sizeimage) + return -EINVAL; + } + } else { + *num_planes = f->fmt.pix_mp.num_planes; + + for (i = 0; i < f->fmt.pix_mp.num_planes; i++) + sizes[i] = f->fmt.pix_mp.plane_fmt[i].sizeimage; + } + + return 0; +} + +static int tegra_buf_out_validate(struct vb2_buffer *vb) +{ + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + + vbuf->field = V4L2_FIELD_NONE; + return 0; +} + +static void __tegra_buf_cleanup(struct vb2_buffer *vb, unsigned int i) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct tegra_ctx *ctx = vb2_get_drv_priv(vq); + struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); + + while (i--) { + if (tb->a[i]) { + tegra_vde_dmabuf_cache_unmap(ctx->vde, tb->a[i], true); + tb->a[i] = NULL; + } + + if (tb->iova[i]) { + tegra_vde_iommu_unmap(ctx->vde, tb->iova[i]); + tb->iova[i] = NULL; + } + } + + if (tb->aux) { + tegra_vde_free_bo(tb->aux); + tb->aux = NULL; + } +} + +static int tegra_buf_init(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct tegra_ctx *ctx = vb2_get_drv_priv(vq); + struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); + struct tegra_vde *vde = ctx->vde; + enum dma_data_direction dma_dir; + struct sg_table *sgt; + unsigned int i; + int err; + + if (V4L2_TYPE_IS_CAPTURE(vq->type) && vb->num_planes > 1) { + /* + * Tegra decoder writes auxiliary data for I/P frames. + * This data is needed for decoding of B frames. + */ + err = tegra_vde_alloc_bo(vde, &tb->aux, DMA_FROM_DEVICE, + vb2_plane_size(vb, 1)); + if (err) + return err; + } + + if (V4L2_TYPE_IS_OUTPUT(vq->type)) + dma_dir = DMA_TO_DEVICE; + else + dma_dir = DMA_FROM_DEVICE; + + for (i = 0; i < vb->num_planes; i++) { + if (vq->memory == VB2_MEMORY_DMABUF) { + get_dma_buf(vb->planes[i].dbuf); + + err = tegra_vde_dmabuf_cache_map(vde, vb->planes[i].dbuf, + dma_dir, &tb->a[i], + &tb->dma_base[i]); + if (err) { + dma_buf_put(vb->planes[i].dbuf); + goto cleanup; + } + + continue; + } + + if (vde->domain) { + sgt = vb2_dma_sg_plane_desc(vb, i); + + err = tegra_vde_iommu_map(vde, sgt, &tb->iova[i], + vb2_plane_size(vb, i)); + if (err) + goto cleanup; + + tb->dma_base[i] = iova_dma_addr(&vde->iova, tb->iova[i]); + } else { + tb->dma_base[i] = vb2_dma_contig_plane_dma_addr(vb, i); + } + } + + return 0; + +cleanup: + __tegra_buf_cleanup(vb, i); + + return err; +} + +static void tegra_buf_cleanup(struct vb2_buffer *vb) +{ + __tegra_buf_cleanup(vb, vb->num_planes); +} + +static int tegra_buf_prepare(struct vb2_buffer *vb) +{ + struct vb2_queue *vq = vb->vb2_queue; + struct tegra_ctx *ctx = vb2_get_drv_priv(vq); + struct tegra_m2m_buffer *tb = vb_to_tegra_buf(vb); + size_t hw_align, hw_size, hw_payload, size, offset; + struct v4l2_pix_format_mplane *pixfmt; + unsigned int i; + void *vb_data; + + if (V4L2_TYPE_IS_OUTPUT(vq->type)) { + hw_align = BSEV_ALIGN; + pixfmt = &ctx->coded_fmt.fmt.pix_mp; + } else { + hw_align = FRAMEID_ALIGN; + pixfmt = &ctx->decoded_fmt.fmt.pix_mp; + } + + for (i = 0; i < vb->num_planes; i++) { + offset = vb->planes[i].data_offset; + + if (offset & (hw_align - 1)) + return -EINVAL; + + if (V4L2_TYPE_IS_CAPTURE(vq->type)) { + size = pixfmt->plane_fmt[i].sizeimage; + hw_payload = ALIGN(size, VDE_ATOM); + } else { + size = vb2_get_plane_payload(vb, i) - offset; + hw_payload = ALIGN(size + VDE_ATOM, SXE_BUFFER); + } + + hw_size = offset + hw_payload; + + if (vb2_plane_size(vb, i) < hw_size) + return -EINVAL; + + vb2_set_plane_payload(vb, i, hw_payload); + + if (V4L2_TYPE_IS_OUTPUT(vq->type)) { + vb_data = vb2_plane_vaddr(vb, i); + + /* + * Hardware requires zero-padding of coded data. + * Otherwise it will fail to parse the trailing + * data and abort the decoding. + */ + if (vb_data) + memset(vb_data + offset + size, 0, + hw_size - offset - size); + } + + tb->dma_addr[i] = tb->dma_base[i] + offset; + } + + switch (pixfmt->pixelformat) { + case V4L2_PIX_FMT_YVU420M: + swap(tb->dma_addr[1], tb->dma_addr[2]); + break; + } + + return 0; +} + +static void tegra_buf_queue(struct vb2_buffer *vb) +{ + struct tegra_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb); + + v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf); +} + +static void tegra_buf_request_complete(struct vb2_buffer *vb) +{ + struct tegra_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue); + + v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->hdl); +} + +static int tegra_start_streaming(struct vb2_queue *vq, unsigned int count) +{ + return 0; +} + +static void tegra_stop_streaming(struct vb2_queue *vq) +{ + struct tegra_ctx *ctx = vb2_get_drv_priv(vq); + + while (true) { + struct vb2_v4l2_buffer *vbuf; + + if (V4L2_TYPE_IS_OUTPUT(vq->type)) + vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx); + else + vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx); + + if (!vbuf) + break; + + v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req, &ctx->hdl); + v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR); + } +} + +static const struct vb2_ops tegra_qops = { + .queue_setup = tegra_queue_setup, + .buf_init = tegra_buf_init, + .buf_cleanup = tegra_buf_cleanup, + .buf_prepare = tegra_buf_prepare, + .buf_queue = tegra_buf_queue, + .buf_out_validate = tegra_buf_out_validate, + .buf_request_complete = tegra_buf_request_complete, + .start_streaming = tegra_start_streaming, + .stop_streaming = tegra_stop_streaming, + .wait_prepare = vb2_ops_wait_prepare, + .wait_finish = vb2_ops_wait_finish, +}; + +static int tegra_queue_init(void *priv, + struct vb2_queue *src_vq, + struct vb2_queue *dst_vq) +{ + struct tegra_ctx *ctx = priv; + struct tegra_vde *vde = ctx->vde; + const struct vb2_mem_ops *mem_ops; + unsigned long dma_attrs; + int err; + + /* + * TODO: Switch to use of vb2_dma_contig_memops uniformly once we + * will add IOMMU_DOMAIN support for video decoder to tegra-smmu + * driver. For now we need to stick with SG ops in order to be able + * to get SGT table easily. This is suboptimal since SG mappings are + * wasting CPU cache and we don't need that caching. + */ + if (vde->domain) + mem_ops = &vb2_dma_sg_memops; + else + mem_ops = &vb2_dma_contig_memops; + + dma_attrs = DMA_ATTR_WRITE_COMBINE; + + src_vq->buf_struct_size = sizeof(struct tegra_m2m_buffer); + src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + src_vq->io_modes = VB2_DMABUF | VB2_MMAP; + src_vq->supports_requests = true; + src_vq->requires_requests = true; + src_vq->lock = &vde->v4l2_lock; + src_vq->dma_attrs = dma_attrs; + src_vq->mem_ops = mem_ops; + src_vq->ops = &tegra_qops; + src_vq->drv_priv = ctx; + src_vq->dev = vde->dev; + + err = vb2_queue_init(src_vq); + if (err) { + v4l2_err(&vde->v4l2_dev, + "failed to initialize src queue: %d\n", err); + return err; + } + + /* + * We may need to zero the end of bitstream in kernel if userspace + * doesn't do that, hence kmap is needed for the coded data. It's not + * needed for framebuffers. + */ + dma_attrs |= DMA_ATTR_NO_KERNEL_MAPPING; + + dst_vq->buf_struct_size = sizeof(struct tegra_m2m_buffer); + dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY; + dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + dst_vq->io_modes = VB2_DMABUF | VB2_MMAP; + dst_vq->lock = &vde->v4l2_lock; + dst_vq->dma_attrs = dma_attrs; + dst_vq->mem_ops = mem_ops; + dst_vq->ops = &tegra_qops; + dst_vq->drv_priv = ctx; + dst_vq->dev = vde->dev; + + err = vb2_queue_init(dst_vq); + if (err) { + v4l2_err(&vde->v4l2_dev, + "failed to initialize dst queue: %d\n", err); + return err; + } + + return 0; +} + +static void tegra_reset_fmt(struct tegra_ctx *ctx, struct v4l2_format *f, + u32 fourcc) +{ + memset(f, 0, sizeof(*f)); + f->fmt.pix_mp.pixelformat = fourcc; + f->fmt.pix_mp.field = V4L2_FIELD_NONE; + f->fmt.pix_mp.xfer_func = V4L2_XFER_FUNC_DEFAULT; + f->fmt.pix_mp.ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT; + f->fmt.pix_mp.colorspace = V4L2_COLORSPACE_REC709; + f->fmt.pix_mp.quantization = V4L2_QUANTIZATION_DEFAULT; +} + +static void tegra_reset_coded_fmt(struct tegra_ctx *ctx) +{ + const struct tegra_vde_soc *soc = ctx->vde->soc; + struct v4l2_format *f = &ctx->coded_fmt; + + ctx->coded_fmt_desc = &soc->coded_fmts[0]; + tegra_reset_fmt(ctx, f, ctx->coded_fmt_desc->fourcc); + + f->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE; + f->fmt.pix_mp.width = ctx->coded_fmt_desc->frmsize.min_width; + f->fmt.pix_mp.height = ctx->coded_fmt_desc->frmsize.min_height; +} + +static void tegra_fill_pixfmt_mp(struct v4l2_pix_format_mplane *pixfmt, + u32 pixelformat, u32 width, u32 height) +{ + const struct v4l2_format_info *info = v4l2_format_info(pixelformat); + struct v4l2_plane_pix_format *plane; + unsigned int i; + + switch (pixelformat) { + case V4L2_PIX_FMT_YUV420M: + case V4L2_PIX_FMT_YVU420M: + pixfmt->width = width; + pixfmt->height = height; + pixfmt->pixelformat = pixelformat; + pixfmt->num_planes = info->mem_planes; + + for (i = 0; i < pixfmt->num_planes; i++) { + unsigned int hdiv = (i == 0) ? 1 : 2; + unsigned int vdiv = (i == 0) ? 1 : 2; + + /* + * VDE is connected to Graphics Memory using 128bit port, + * all memory accesses are made using 16B atoms. + * + * V4L requires Cb/Cr strides to be exactly half of the + * Y stride, hence we're aligning Y to 16B x 2. + */ + plane = &pixfmt->plane_fmt[i]; + plane->bytesperline = ALIGN(width, VDE_ATOM * 2) / hdiv; + plane->sizeimage = plane->bytesperline * height / vdiv; + } + + break; + } +} + +static void tegra_reset_decoded_fmt(struct tegra_ctx *ctx) +{ + struct v4l2_format *f = &ctx->decoded_fmt; + + tegra_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]); + f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE; + tegra_fill_pixfmt_mp(&f->fmt.pix_mp, + ctx->coded_fmt_desc->decoded_fmts[0], + ctx->coded_fmt.fmt.pix_mp.width, + ctx->coded_fmt.fmt.pix_mp.height); +} + +static void tegra_job_finish(struct tegra_ctx *ctx, + enum vb2_buffer_state result) +{ + v4l2_m2m_buf_done_and_job_finish(ctx->vde->m2m, ctx->fh.m2m_ctx, + result); +} + +static void tegra_decode_complete(struct work_struct *work) +{ + struct tegra_ctx *ctx = container_of(work, struct tegra_ctx, work); + int err; + + err = ctx->coded_fmt_desc->decode_wait(ctx); + if (err) + tegra_job_finish(ctx, VB2_BUF_STATE_ERROR); + else + tegra_job_finish(ctx, VB2_BUF_STATE_DONE); +} + +static int tegra_querycap(struct file *file, void *priv, + struct v4l2_capability *cap) +{ + strscpy(cap->bus_info, "platform:tegra-vde", sizeof(cap->bus_info)); + strscpy(cap->driver, "tegra-vde", sizeof(cap->driver)); + strscpy(cap->card, "tegra-vde", sizeof(cap->card)); + + return 0; +} + +static int tegra_enum_decoded_fmt(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); + + if (WARN_ON(!ctx->coded_fmt_desc)) + return -EINVAL; + + if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts) + return -EINVAL; + + f->pixelformat = ctx->coded_fmt_desc->decoded_fmts[f->index]; + + return 0; +} + +static int tegra_g_decoded_fmt(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); + + *f = ctx->decoded_fmt; + return 0; +} + +static int tegra_try_decoded_fmt(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; + struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); + const struct tegra_coded_fmt_desc *coded_desc; + unsigned int i; + + /* + * The codec context should point to a coded format desc, if the format + * on the coded end has not been set yet, it should point to the + * default value. + */ + coded_desc = ctx->coded_fmt_desc; + if (WARN_ON(!coded_desc)) + return -EINVAL; + + if (!coded_desc->num_decoded_fmts) + return -EINVAL; + + for (i = 0; i < coded_desc->num_decoded_fmts; i++) { + if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat) + break; + } + + if (i == coded_desc->num_decoded_fmts) + pix_mp->pixelformat = coded_desc->decoded_fmts[0]; + + /* always apply the frmsize constraint of the coded end */ + v4l2_apply_frmsize_constraints(&pix_mp->width, + &pix_mp->height, + &coded_desc->frmsize); + + tegra_fill_pixfmt_mp(pix_mp, pix_mp->pixelformat, + pix_mp->width, pix_mp->height); + pix_mp->field = V4L2_FIELD_NONE; + + return 0; +} + +static int tegra_s_decoded_fmt(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); + struct vb2_queue *vq; + int err; + + /* change not allowed if queue is busy */ + vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, + V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + if (vb2_is_busy(vq)) + return -EBUSY; + + err = tegra_try_decoded_fmt(file, priv, f); + if (err) + return err; + + ctx->decoded_fmt = *f; + + return 0; +} + +static int tegra_enum_coded_fmt(struct file *file, void *priv, + struct v4l2_fmtdesc *f) +{ + struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); + const struct tegra_vde_soc *soc = ctx->vde->soc; + + if (f->index >= soc->num_coded_fmts) + return -EINVAL; + + f->pixelformat = soc->coded_fmts[f->index].fourcc; + + return 0; +} + +static int tegra_g_coded_fmt(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); + + *f = ctx->coded_fmt; + return 0; +} + +static const struct tegra_coded_fmt_desc * +tegra_find_coded_fmt_desc(struct tegra_ctx *ctx, u32 fourcc) +{ + const struct tegra_vde_soc *soc = ctx->vde->soc; + unsigned int i; + + for (i = 0; i < soc->num_coded_fmts; i++) { + if (soc->coded_fmts[i].fourcc == fourcc) + return &soc->coded_fmts[i]; + } + + return NULL; +} + +static int tegra_try_coded_fmt(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct v4l2_pix_format_mplane *pix_mp = &f->fmt.pix_mp; + struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); + const struct tegra_vde_soc *soc = ctx->vde->soc; + int size = pix_mp->plane_fmt[0].sizeimage; + const struct tegra_coded_fmt_desc *desc; + + desc = tegra_find_coded_fmt_desc(ctx, pix_mp->pixelformat); + if (!desc) { + pix_mp->pixelformat = soc->coded_fmts[0].fourcc; + desc = &soc->coded_fmts[0]; + } + + v4l2_apply_frmsize_constraints(&pix_mp->width, + &pix_mp->height, + &desc->frmsize); + + pix_mp->plane_fmt[0].sizeimage = max(ALIGN(size, SXE_BUFFER), SZ_2M); + pix_mp->field = V4L2_FIELD_NONE; + pix_mp->num_planes = 1; + + return 0; +} + +static int tegra_s_coded_fmt(struct file *file, void *priv, + struct v4l2_format *f) +{ + struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); + struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx; + const struct tegra_coded_fmt_desc *desc; + struct vb2_queue *peer_vq, *vq; + struct v4l2_format *cap_fmt; + int err; + + /* + * In order to support dynamic resolution change, the decoder admits + * a resolution change, as long as the pixelformat remains. Can't be + * done if streaming. + */ + vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE); + if (vb2_is_streaming(vq) || + (vb2_is_busy(vq) && + f->fmt.pix_mp.pixelformat != ctx->coded_fmt.fmt.pix_mp.pixelformat)) + return -EBUSY; + + /* + * Since format change on the OUTPUT queue will reset the CAPTURE + * queue, we can't allow doing so when the CAPTURE queue has buffers + * allocated. + */ + peer_vq = v4l2_m2m_get_vq(m2m_ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE); + if (vb2_is_busy(peer_vq)) + return -EBUSY; + + err = tegra_try_coded_fmt(file, priv, f); + if (err) + return err; + + desc = tegra_find_coded_fmt_desc(ctx, f->fmt.pix_mp.pixelformat); + if (!desc) + return -EINVAL; + + ctx->coded_fmt_desc = desc; + ctx->coded_fmt = *f; + + /* + * Current decoded format might have become invalid with newly + * selected codec, so reset it to default just to be safe and + * keep internal driver state sane. User is mandated to set + * the decoded format again after we return, so we don't need + * anything smarter. + * + * Note that this will propagates any size changes to the decoded format. + */ + tegra_reset_decoded_fmt(ctx); + + /* propagate colorspace information to capture */ + cap_fmt = &ctx->decoded_fmt; + cap_fmt->fmt.pix_mp.xfer_func = f->fmt.pix_mp.xfer_func; + cap_fmt->fmt.pix_mp.ycbcr_enc = f->fmt.pix_mp.ycbcr_enc; + cap_fmt->fmt.pix_mp.colorspace = f->fmt.pix_mp.colorspace; + cap_fmt->fmt.pix_mp.quantization = f->fmt.pix_mp.quantization; + + return 0; +} + +static int tegra_enum_framesizes(struct file *file, void *priv, + struct v4l2_frmsizeenum *fsize) +{ + struct tegra_ctx *ctx = fh_to_tegra_ctx(priv); + const struct tegra_coded_fmt_desc *fmt; + + if (fsize->index) + return -EINVAL; + + fmt = tegra_find_coded_fmt_desc(ctx, fsize->pixel_format); + if (!fmt) + return -EINVAL; + + fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE; + fsize->stepwise = fmt->frmsize; + + return 0; +} + +static const struct v4l2_ioctl_ops tegra_v4l2_ioctl_ops = { + .vidioc_querycap = tegra_querycap, + .vidioc_enum_framesizes = tegra_enum_framesizes, + + .vidioc_try_fmt_vid_out_mplane = tegra_try_coded_fmt, + .vidioc_g_fmt_vid_out_mplane = tegra_g_coded_fmt, + .vidioc_s_fmt_vid_out_mplane = tegra_s_coded_fmt, + .vidioc_enum_fmt_vid_out = tegra_enum_coded_fmt, + + .vidioc_try_fmt_vid_cap_mplane = tegra_try_decoded_fmt, + .vidioc_g_fmt_vid_cap_mplane = tegra_g_decoded_fmt, + .vidioc_s_fmt_vid_cap_mplane = tegra_s_decoded_fmt, + .vidioc_enum_fmt_vid_cap = tegra_enum_decoded_fmt, + + .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs, + .vidioc_querybuf = v4l2_m2m_ioctl_querybuf, + .vidioc_qbuf = v4l2_m2m_ioctl_qbuf, + .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf, + .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf, + .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs, + .vidioc_expbuf = v4l2_m2m_ioctl_expbuf, + + .vidioc_streamon = v4l2_m2m_ioctl_streamon, + .vidioc_streamoff = v4l2_m2m_ioctl_streamoff, + + .vidioc_subscribe_event = v4l2_ctrl_subscribe_event, + .vidioc_unsubscribe_event = v4l2_event_unsubscribe, +}; + +static int tegra_init_ctrls(struct tegra_ctx *ctx) +{ + unsigned int i; + int err; + + err = v4l2_ctrl_handler_init(&ctx->hdl, ARRAY_SIZE(ctrl_cfgs)); + if (err) + return err; + + for (i = 0; i < ARRAY_SIZE(ctrl_cfgs); i++) { + ctx->ctrls[i] = v4l2_ctrl_new_custom(&ctx->hdl, &ctrl_cfgs[i], + NULL); + if (ctx->hdl.error) { + err = ctx->hdl.error; + goto free_ctrls; + } + } + + err = v4l2_ctrl_handler_setup(&ctx->hdl); + if (err) + goto free_ctrls; + + ctx->fh.ctrl_handler = &ctx->hdl; + + return 0; + +free_ctrls: + v4l2_ctrl_handler_free(&ctx->hdl); + + return err; +} + +static int tegra_init_m2m(struct tegra_ctx *ctx) +{ + ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(ctx->vde->m2m, + ctx, tegra_queue_init); + if (IS_ERR(ctx->fh.m2m_ctx)) + return PTR_ERR(ctx->fh.m2m_ctx); + + return 0; +} + +static int tegra_open(struct file *file) +{ + struct tegra_vde *vde = video_drvdata(file); + struct tegra_ctx *ctx; + int err; + + ctx = kzalloc(offsetof(struct tegra_ctx, ctrls[ARRAY_SIZE(ctrl_cfgs)]), + GFP_KERNEL); + if (!ctx) + return -ENOMEM; + + ctx->vde = vde; + v4l2_fh_init(&ctx->fh, video_devdata(file)); + INIT_WORK(&ctx->work, tegra_decode_complete); + + err = tegra_init_ctrls(ctx); + if (err) { + v4l2_err(&vde->v4l2_dev, "failed to add controls: %d\n", err); + goto free_ctx; + } + + err = tegra_init_m2m(ctx); + if (err) { + v4l2_err(&vde->v4l2_dev, "failed to initialize m2m: %d\n", err); + goto free_ctrls; + } + + file->private_data = &ctx->fh; + v4l2_fh_add(&ctx->fh); + + tegra_reset_coded_fmt(ctx); + tegra_try_coded_fmt(file, file->private_data, &ctx->coded_fmt); + + tegra_reset_decoded_fmt(ctx); + tegra_try_decoded_fmt(file, file->private_data, &ctx->decoded_fmt); + + return 0; + +free_ctrls: + v4l2_ctrl_handler_free(&ctx->hdl); +free_ctx: + kfree(ctx); + + return err; +} + +static int tegra_release(struct file *file) +{ + struct v4l2_fh *fh = file->private_data; + struct tegra_ctx *ctx = fh_to_tegra_ctx(fh); + struct tegra_vde *vde = ctx->vde; + + v4l2_fh_del(fh); + v4l2_m2m_ctx_release(fh->m2m_ctx); + v4l2_ctrl_handler_free(&ctx->hdl); + v4l2_fh_exit(fh); + kfree(ctx); + + tegra_vde_dmabuf_cache_unmap_sync(vde); + + return 0; +} + +static const struct v4l2_file_operations tegra_v4l2_fops = { + .owner = THIS_MODULE, + .open = tegra_open, + .poll = v4l2_m2m_fop_poll, + .mmap = v4l2_m2m_fop_mmap, + .release = tegra_release, + .unlocked_ioctl = video_ioctl2, +}; + +static void tegra_device_run(void *priv) +{ + struct tegra_ctx *ctx = priv; + struct vb2_v4l2_buffer *src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx); + struct media_request *src_req = src->vb2_buf.req_obj.req; + int err; + + v4l2_ctrl_request_setup(src_req, &ctx->hdl); + + err = ctx->coded_fmt_desc->decode_run(ctx); + + v4l2_ctrl_request_complete(src_req, &ctx->hdl); + + if (err) + tegra_job_finish(ctx, VB2_BUF_STATE_ERROR); + else + queue_work(ctx->vde->wq, &ctx->work); +} + +static const struct v4l2_m2m_ops tegra_v4l2_m2m_ops = { + .device_run = tegra_device_run, +}; + +static int tegra_request_validate(struct media_request *req) +{ + unsigned int count; + + count = vb2_request_buffer_cnt(req); + if (!count) + return -ENOENT; + else if (count > 1) + return -EINVAL; + + return vb2_request_validate(req); +} + +static const struct media_device_ops tegra_media_device_ops = { + .req_validate = tegra_request_validate, + .req_queue = v4l2_m2m_request_queue, +}; + +int tegra_vde_v4l2_init(struct tegra_vde *vde) +{ + struct device *dev = vde->dev; + int err; + + mutex_init(&vde->v4l2_lock); + media_device_init(&vde->mdev); + video_set_drvdata(&vde->vdev, vde); + + vde->vdev.lock = &vde->v4l2_lock, + vde->vdev.fops = &tegra_v4l2_fops, + vde->vdev.vfl_dir = VFL_DIR_M2M, + vde->vdev.release = video_device_release_empty, + vde->vdev.v4l2_dev = &vde->v4l2_dev; + vde->vdev.ioctl_ops = &tegra_v4l2_ioctl_ops, + vde->vdev.device_caps = V4L2_CAP_VIDEO_M2M_MPLANE | V4L2_CAP_STREAMING, + + vde->v4l2_dev.mdev = &vde->mdev; + vde->mdev.ops = &tegra_media_device_ops; + vde->mdev.dev = dev; + + strscpy(vde->mdev.model, "tegra-vde", sizeof(vde->mdev.model)); + strscpy(vde->vdev.name, "tegra-vde", sizeof(vde->vdev.name)); + strscpy(vde->mdev.bus_info, "platform:tegra-vde", + sizeof(vde->mdev.bus_info)); + + vde->wq = create_workqueue("tegra-vde"); + if (!vde->wq) + return -ENOMEM; + + err = media_device_register(&vde->mdev); + if (err) { + dev_err(dev, "failed to register media device: %d\n", err); + goto clean_up_media_device; + } + + err = v4l2_device_register(dev, &vde->v4l2_dev); + if (err) { + dev_err(dev, "failed to register v4l2 device: %d\n", err); + goto unreg_media_device; + } + + err = video_register_device(&vde->vdev, VFL_TYPE_VIDEO, -1); + if (err) { + dev_err(dev, "failed to register video device: %d\n", err); + goto unreg_v4l2; + } + + vde->m2m = v4l2_m2m_init(&tegra_v4l2_m2m_ops); + err = PTR_ERR_OR_ZERO(vde->m2m); + if (err) { + dev_err(dev, "failed to initialize m2m device: %d\n", err); + goto unreg_video_device; + } + + err = v4l2_m2m_register_media_controller(vde->m2m, &vde->vdev, + MEDIA_ENT_F_PROC_VIDEO_DECODER); + if (err) { + dev_err(dev, "failed to register media controller: %d\n", err); + goto release_m2m; + } + + v4l2_info(&vde->v4l2_dev, "v4l2 device registered as /dev/video%d\n", + vde->vdev.num); + + return 0; + +release_m2m: + v4l2_m2m_release(vde->m2m); +unreg_video_device: + video_unregister_device(&vde->vdev); +unreg_v4l2: + v4l2_device_unregister(&vde->v4l2_dev); +unreg_media_device: + media_device_unregister(&vde->mdev); +clean_up_media_device: + media_device_cleanup(&vde->mdev); + + destroy_workqueue(vde->wq); + + return err; +} + +void tegra_vde_v4l2_deinit(struct tegra_vde *vde) +{ + v4l2_m2m_unregister_media_controller(vde->m2m); + v4l2_m2m_release(vde->m2m); + + video_unregister_device(&vde->vdev); + v4l2_device_unregister(&vde->v4l2_dev); + + media_device_unregister(&vde->mdev); + media_device_cleanup(&vde->mdev); + + destroy_workqueue(vde->wq); +} diff --git a/drivers/media/platform/tegra/vde/vde.c b/drivers/media/platform/tegra/vde/vde.c new file mode 100644 index 000000000000..f3e863a94c5a --- /dev/null +++ b/drivers/media/platform/tegra/vde/vde.c @@ -0,0 +1,551 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * NVIDIA Tegra Video decoder driver + * + * Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com> + * + */ + +#include <linux/clk.h> +#include <linux/dma-buf.h> +#include <linux/genalloc.h> +#include <linux/interrupt.h> +#include <linux/list.h> +#include <linux/module.h> +#include <linux/of_device.h> +#include <linux/pm_runtime.h> +#include <linux/reset.h> +#include <linux/slab.h> +#include <linux/uaccess.h> + +#include <soc/tegra/common.h> +#include <soc/tegra/pmc.h> + +#include "vde.h" + +#define CREATE_TRACE_POINTS +#include "trace.h" + +void tegra_vde_writel(struct tegra_vde *vde, u32 value, + void __iomem *base, u32 offset) +{ + trace_vde_writel(vde, base, offset, value); + + writel_relaxed(value, base + offset); +} + +u32 tegra_vde_readl(struct tegra_vde *vde, void __iomem *base, u32 offset) +{ + u32 value = readl_relaxed(base + offset); + + trace_vde_readl(vde, base, offset, value); + + return value; +} + +void tegra_vde_set_bits(struct tegra_vde *vde, u32 mask, + void __iomem *base, u32 offset) +{ + u32 value = tegra_vde_readl(vde, base, offset); + + tegra_vde_writel(vde, value | mask, base, offset); +} + +int tegra_vde_alloc_bo(struct tegra_vde *vde, + struct tegra_vde_bo **ret_bo, + enum dma_data_direction dma_dir, + size_t size) +{ + struct device *dev = vde->dev; + struct tegra_vde_bo *bo; + int err; + + bo = kzalloc(sizeof(*bo), GFP_KERNEL); + if (!bo) + return -ENOMEM; + + bo->vde = vde; + bo->size = size; + bo->dma_dir = dma_dir; + bo->dma_attrs = DMA_ATTR_WRITE_COMBINE | + DMA_ATTR_NO_KERNEL_MAPPING; + + if (!vde->domain) + bo->dma_attrs |= DMA_ATTR_FORCE_CONTIGUOUS; + + bo->dma_cookie = dma_alloc_attrs(dev, bo->size, &bo->dma_handle, + GFP_KERNEL, bo->dma_attrs); + if (!bo->dma_cookie) { + dev_err(dev, "Failed to allocate DMA buffer of size: %zu\n", + bo->size); + err = -ENOMEM; + goto free_bo; + } + + err = dma_get_sgtable_attrs(dev, &bo->sgt, bo->dma_cookie, + bo->dma_handle, bo->size, bo->dma_attrs); + if (err) { + dev_err(dev, "Failed to get DMA buffer SG table: %d\n", err); + goto free_attrs; + } + + err = dma_map_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs); + if (err) { + dev_err(dev, "Failed to map DMA buffer SG table: %d\n", err); + goto free_table; + } + + if (vde->domain) { + err = tegra_vde_iommu_map(vde, &bo->sgt, &bo->iova, bo->size); + if (err) { + dev_err(dev, "Failed to map DMA buffer IOVA: %d\n", err); + goto unmap_sgtable; + } + + bo->dma_addr = iova_dma_addr(&vde->iova, bo->iova); + } else { + bo->dma_addr = sg_dma_address(bo->sgt.sgl); + } + + *ret_bo = bo; + + return 0; + +unmap_sgtable: + dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs); +free_table: + sg_free_table(&bo->sgt); +free_attrs: + dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle, + bo->dma_attrs); +free_bo: + kfree(bo); + + return err; +} + +void tegra_vde_free_bo(struct tegra_vde_bo *bo) +{ + struct tegra_vde *vde = bo->vde; + struct device *dev = vde->dev; + + if (vde->domain) + tegra_vde_iommu_unmap(vde, bo->iova); + + dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs); + + sg_free_table(&bo->sgt); + + dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle, + bo->dma_attrs); + kfree(bo); +} + +static irqreturn_t tegra_vde_isr(int irq, void *data) +{ + struct tegra_vde *vde = data; + + if (completion_done(&vde->decode_completion)) + return IRQ_NONE; + + tegra_vde_set_bits(vde, 0, vde->frameid, 0x208); + complete(&vde->decode_completion); + + return IRQ_HANDLED; +} + +static __maybe_unused int tegra_vde_runtime_suspend(struct device *dev) +{ + struct tegra_vde *vde = dev_get_drvdata(dev); + int err; + + if (!dev->pm_domain) { + err = tegra_powergate_power_off(TEGRA_POWERGATE_VDEC); + if (err) { + dev_err(dev, "Failed to power down HW: %d\n", err); + return err; + } + } + + clk_disable_unprepare(vde->clk); + reset_control_release(vde->rst); + reset_control_release(vde->rst_mc); + + return 0; +} + +static __maybe_unused int tegra_vde_runtime_resume(struct device *dev) +{ + struct tegra_vde *vde = dev_get_drvdata(dev); + int err; + + err = reset_control_acquire(vde->rst_mc); + if (err) { + dev_err(dev, "Failed to acquire mc reset: %d\n", err); + return err; + } + + err = reset_control_acquire(vde->rst); + if (err) { + dev_err(dev, "Failed to acquire reset: %d\n", err); + goto release_mc_reset; + } + + if (!dev->pm_domain) { + err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_VDEC, + vde->clk, vde->rst); + if (err) { + dev_err(dev, "Failed to power up HW : %d\n", err); + goto release_reset; + } + } else { + /* + * tegra_powergate_sequence_power_up() leaves clocks enabled, + * while GENPD not. + */ + err = clk_prepare_enable(vde->clk); + if (err) { + dev_err(dev, "Failed to enable clock: %d\n", err); + goto release_reset; + } + } + + return 0; + +release_reset: + reset_control_release(vde->rst); +release_mc_reset: + reset_control_release(vde->rst_mc); + + return err; +} + +static int tegra_vde_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct tegra_vde *vde; + int irq, err; + + vde = devm_kzalloc(dev, sizeof(*vde), GFP_KERNEL); + if (!vde) + return -ENOMEM; + + platform_set_drvdata(pdev, vde); + + vde->soc = of_device_get_match_data(&pdev->dev); + vde->dev = dev; + + vde->sxe = devm_platform_ioremap_resource_byname(pdev, "sxe"); + if (IS_ERR(vde->sxe)) + return PTR_ERR(vde->sxe); + + vde->bsev = devm_platform_ioremap_resource_byname(pdev, "bsev"); + if (IS_ERR(vde->bsev)) + return PTR_ERR(vde->bsev); + + vde->mbe = devm_platform_ioremap_resource_byname(pdev, "mbe"); + if (IS_ERR(vde->mbe)) + return PTR_ERR(vde->mbe); + + vde->ppe = devm_platform_ioremap_resource_byname(pdev, "ppe"); + if (IS_ERR(vde->ppe)) + return PTR_ERR(vde->ppe); + + vde->mce = devm_platform_ioremap_resource_byname(pdev, "mce"); + if (IS_ERR(vde->mce)) + return PTR_ERR(vde->mce); + + vde->tfe = devm_platform_ioremap_resource_byname(pdev, "tfe"); + if (IS_ERR(vde->tfe)) + return PTR_ERR(vde->tfe); + + vde->ppb = devm_platform_ioremap_resource_byname(pdev, "ppb"); + if (IS_ERR(vde->ppb)) + return PTR_ERR(vde->ppb); + + vde->vdma = devm_platform_ioremap_resource_byname(pdev, "vdma"); + if (IS_ERR(vde->vdma)) + return PTR_ERR(vde->vdma); + + vde->frameid = devm_platform_ioremap_resource_byname(pdev, "frameid"); + if (IS_ERR(vde->frameid)) + return PTR_ERR(vde->frameid); + + vde->clk = devm_clk_get(dev, NULL); + if (IS_ERR(vde->clk)) { + err = PTR_ERR(vde->clk); + dev_err(dev, "Could not get VDE clk %d\n", err); + return err; + } + + vde->rst = devm_reset_control_get_exclusive_released(dev, NULL); + if (IS_ERR(vde->rst)) { + err = PTR_ERR(vde->rst); + dev_err(dev, "Could not get VDE reset %d\n", err); + return err; + } + + vde->rst_mc = devm_reset_control_get_optional_exclusive_released(dev, "mc"); + if (IS_ERR(vde->rst_mc)) { + err = PTR_ERR(vde->rst_mc); + dev_err(dev, "Could not get MC reset %d\n", err); + return err; + } + + irq = platform_get_irq_byname(pdev, "sync-token"); + if (irq < 0) + return irq; + + err = devm_request_irq(dev, irq, tegra_vde_isr, 0, + dev_name(dev), vde); + if (err) { + dev_err(dev, "Could not request IRQ %d\n", err); + return err; + } + + err = devm_tegra_core_dev_init_opp_table_common(dev); + if (err) { + dev_err(dev, "Could initialize OPP table %d\n", err); + return err; + } + + vde->iram_pool = of_gen_pool_get(dev->of_node, "iram", 0); + if (!vde->iram_pool) { + dev_err(dev, "Could not get IRAM pool\n"); + return -EPROBE_DEFER; + } + + vde->iram = gen_pool_dma_alloc(vde->iram_pool, + gen_pool_size(vde->iram_pool), + &vde->iram_lists_addr); + if (!vde->iram) { + dev_err(dev, "Could not reserve IRAM\n"); + return -ENOMEM; + } + + INIT_LIST_HEAD(&vde->map_list); + mutex_init(&vde->map_lock); + mutex_init(&vde->lock); + init_completion(&vde->decode_completion); + + err = tegra_vde_iommu_init(vde); + if (err) { + dev_err(dev, "Failed to initialize IOMMU: %d\n", err); + goto err_gen_free; + } + + pm_runtime_enable(dev); + pm_runtime_use_autosuspend(dev); + pm_runtime_set_autosuspend_delay(dev, 300); + + /* + * VDE partition may be left ON after bootloader, hence let's + * power-cycle it in order to put hardware into a predictable lower + * power state. + */ + err = pm_runtime_resume_and_get(dev); + if (err) + goto err_pm_runtime; + + pm_runtime_put(dev); + + err = tegra_vde_alloc_bo(vde, &vde->secure_bo, DMA_FROM_DEVICE, 4096); + if (err) { + dev_err(dev, "Failed to allocate secure BO: %d\n", err); + goto err_pm_runtime; + } + + err = tegra_vde_v4l2_init(vde); + if (err) { + dev_err(dev, "Failed to initialize V4L2: %d\n", err); + goto err_free_secure_bo; + } + + return 0; + +err_free_secure_bo: + tegra_vde_free_bo(vde->secure_bo); +err_pm_runtime: + pm_runtime_dont_use_autosuspend(dev); + pm_runtime_disable(dev); + + tegra_vde_iommu_deinit(vde); + +err_gen_free: + gen_pool_free(vde->iram_pool, (unsigned long)vde->iram, + gen_pool_size(vde->iram_pool)); + + return err; +} + +static int tegra_vde_remove(struct platform_device *pdev) +{ + struct tegra_vde *vde = platform_get_drvdata(pdev); + struct device *dev = &pdev->dev; + + tegra_vde_v4l2_deinit(vde); + tegra_vde_free_bo(vde->secure_bo); + + /* + * As it increments RPM usage_count even on errors, we don't need to + * check the returned code here. + */ + pm_runtime_get_sync(dev); + + pm_runtime_dont_use_autosuspend(dev); + pm_runtime_disable(dev); + + /* + * Balance RPM state, the VDE power domain is left ON and hardware + * is clock-gated. It's safe to reboot machine now. + */ + pm_runtime_put_noidle(dev); + clk_disable_unprepare(vde->clk); + + tegra_vde_dmabuf_cache_unmap_all(vde); + tegra_vde_iommu_deinit(vde); + + gen_pool_free(vde->iram_pool, (unsigned long)vde->iram, + gen_pool_size(vde->iram_pool)); + + return 0; +} + +static void tegra_vde_shutdown(struct platform_device *pdev) +{ + /* + * On some devices bootloader isn't ready to a power-gated VDE on + * a warm-reboot, machine will hang in that case. + */ + pm_runtime_get_sync(&pdev->dev); +} + +static __maybe_unused int tegra_vde_pm_suspend(struct device *dev) +{ + struct tegra_vde *vde = dev_get_drvdata(dev); + int err; + + mutex_lock(&vde->lock); + + err = pm_runtime_force_suspend(dev); + if (err < 0) + return err; + + return 0; +} + +static __maybe_unused int tegra_vde_pm_resume(struct device *dev) +{ + struct tegra_vde *vde = dev_get_drvdata(dev); + int err; + + err = pm_runtime_force_resume(dev); + if (err < 0) + return err; + + mutex_unlock(&vde->lock); + + return 0; +} + +static const struct dev_pm_ops tegra_vde_pm_ops = { + SET_RUNTIME_PM_OPS(tegra_vde_runtime_suspend, + tegra_vde_runtime_resume, + NULL) + SET_SYSTEM_SLEEP_PM_OPS(tegra_vde_pm_suspend, + tegra_vde_pm_resume) +}; + +static const u32 tegra124_decoded_fmts[] = { + /* TBD: T124 supports only a non-standard Tegra tiled format */ +}; + +static const struct tegra_coded_fmt_desc tegra124_coded_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .frmsize = { + .min_width = 16, + .max_width = 1920, + .step_width = 16, + .min_height = 16, + .max_height = 2032, + .step_height = 16, + }, + .num_decoded_fmts = ARRAY_SIZE(tegra124_decoded_fmts), + .decoded_fmts = tegra124_decoded_fmts, + .decode_run = tegra_vde_h264_decode_run, + .decode_wait = tegra_vde_h264_decode_wait, + }, +}; + +static const u32 tegra20_decoded_fmts[] = { + V4L2_PIX_FMT_YUV420M, + V4L2_PIX_FMT_YVU420M, +}; + +static const struct tegra_coded_fmt_desc tegra20_coded_fmts[] = { + { + .fourcc = V4L2_PIX_FMT_H264_SLICE, + .frmsize = { + .min_width = 16, + .max_width = 1920, + .step_width = 16, + .min_height = 16, + .max_height = 2032, + .step_height = 16, + }, + .num_decoded_fmts = ARRAY_SIZE(tegra20_decoded_fmts), + .decoded_fmts = tegra20_decoded_fmts, + .decode_run = tegra_vde_h264_decode_run, + .decode_wait = tegra_vde_h264_decode_wait, + }, +}; + +static const struct tegra_vde_soc tegra124_vde_soc = { + .supports_ref_pic_marking = true, + .coded_fmts = tegra124_coded_fmts, + .num_coded_fmts = ARRAY_SIZE(tegra124_coded_fmts), +}; + +static const struct tegra_vde_soc tegra114_vde_soc = { + .supports_ref_pic_marking = true, + .coded_fmts = tegra20_coded_fmts, + .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts), +}; + +static const struct tegra_vde_soc tegra30_vde_soc = { + .supports_ref_pic_marking = false, + .coded_fmts = tegra20_coded_fmts, + .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts), +}; + +static const struct tegra_vde_soc tegra20_vde_soc = { + .supports_ref_pic_marking = false, + .coded_fmts = tegra20_coded_fmts, + .num_coded_fmts = ARRAY_SIZE(tegra20_coded_fmts), +}; + +static const struct of_device_id tegra_vde_of_match[] = { + { .compatible = "nvidia,tegra124-vde", .data = &tegra124_vde_soc }, + { .compatible = "nvidia,tegra114-vde", .data = &tegra114_vde_soc }, + { .compatible = "nvidia,tegra30-vde", .data = &tegra30_vde_soc }, + { .compatible = "nvidia,tegra20-vde", .data = &tegra20_vde_soc }, + { }, +}; +MODULE_DEVICE_TABLE(of, tegra_vde_of_match); + +static struct platform_driver tegra_vde_driver = { + .probe = tegra_vde_probe, + .remove = tegra_vde_remove, + .shutdown = tegra_vde_shutdown, + .driver = { + .name = "tegra-vde", + .of_match_table = tegra_vde_of_match, + .pm = &tegra_vde_pm_ops, + }, +}; +module_platform_driver(tegra_vde_driver); + +MODULE_DESCRIPTION("NVIDIA Tegra Video Decoder driver"); +MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>"); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/platform/tegra/vde/vde.h b/drivers/media/platform/tegra/vde/vde.h new file mode 100644 index 000000000000..0fbb1f3d2c88 --- /dev/null +++ b/drivers/media/platform/tegra/vde/vde.h @@ -0,0 +1,242 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * NVIDIA Tegra Video decoder driver + * + * Copyright (C) 2016-2019 GRATE-DRIVER project + */ + +#ifndef TEGRA_VDE_H +#define TEGRA_VDE_H + +#include <linux/completion.h> +#include <linux/dma-direction.h> +#include <linux/iova.h> +#include <linux/list.h> +#include <linux/mutex.h> +#include <linux/types.h> +#include <linux/workqueue.h> + +#include <media/media-device.h> +#include <media/videobuf2-dma-contig.h> +#include <media/videobuf2-dma-sg.h> +#include <media/v4l2-ctrls.h> +#include <media/v4l2-device.h> +#include <media/v4l2-event.h> +#include <media/v4l2-ioctl.h> +#include <media/v4l2-mem2mem.h> + +#define ICMDQUE_WR 0x00 +#define CMDQUE_CONTROL 0x08 +#define INTR_STATUS 0x18 +#define BSE_INT_ENB 0x40 +#define BSE_CONFIG 0x44 + +#define BSE_ICMDQUE_EMPTY BIT(3) +#define BSE_DMA_BUSY BIT(23) + +#define BSEV_ALIGN SZ_1 +#define FRAMEID_ALIGN SZ_256 +#define SXE_BUFFER SZ_32K +#define VDE_ATOM SZ_16 + +struct clk; +struct dma_buf; +struct gen_pool; +struct tegra_ctx; +struct iommu_group; +struct iommu_domain; +struct reset_control; +struct dma_buf_attachment; +struct tegra_vde_h264_frame; +struct tegra_vde_h264_decoder_ctx; + +struct tegra_video_frame { + struct dma_buf_attachment *y_dmabuf_attachment; + struct dma_buf_attachment *cb_dmabuf_attachment; + struct dma_buf_attachment *cr_dmabuf_attachment; + struct dma_buf_attachment *aux_dmabuf_attachment; + dma_addr_t y_addr; + dma_addr_t cb_addr; + dma_addr_t cr_addr; + dma_addr_t aux_addr; + u32 frame_num; + u32 flags; + u32 luma_atoms_pitch; + u32 chroma_atoms_pitch; +}; + +struct tegra_coded_fmt_desc { + u32 fourcc; + struct v4l2_frmsize_stepwise frmsize; + unsigned int num_decoded_fmts; + const u32 *decoded_fmts; + int (*decode_run)(struct tegra_ctx *ctx); + int (*decode_wait)(struct tegra_ctx *ctx); +}; + +struct tegra_vde_soc { + bool supports_ref_pic_marking; + const struct tegra_coded_fmt_desc *coded_fmts; + u32 num_coded_fmts; +}; + +struct tegra_vde_bo { + struct iova *iova; + struct sg_table sgt; + struct tegra_vde *vde; + enum dma_data_direction dma_dir; + unsigned long dma_attrs; + dma_addr_t dma_handle; + dma_addr_t dma_addr; + void *dma_cookie; + size_t size; +}; + +struct tegra_vde { + void __iomem *sxe; + void __iomem *bsev; + void __iomem *mbe; + void __iomem *ppe; + void __iomem *mce; + void __iomem *tfe; + void __iomem *ppb; + void __iomem *vdma; + void __iomem *frameid; + struct device *dev; + struct mutex lock; + struct mutex map_lock; + struct list_head map_list; + struct reset_control *rst; + struct reset_control *rst_mc; + struct gen_pool *iram_pool; + struct completion decode_completion; + struct clk *clk; + struct iommu_domain *domain; + struct iommu_group *group; + struct iova_domain iova; + struct iova *iova_resv_static_addresses; + struct iova *iova_resv_last_page; + const struct tegra_vde_soc *soc; + struct tegra_vde_bo *secure_bo; + dma_addr_t bitstream_data_addr; + dma_addr_t iram_lists_addr; + u32 *iram; + struct v4l2_device v4l2_dev; + struct v4l2_m2m_dev *m2m; + struct media_device mdev; + struct video_device vdev; + struct mutex v4l2_lock; + struct workqueue_struct *wq; + struct tegra_video_frame frames[V4L2_H264_NUM_DPB_ENTRIES + 1]; +}; + +int tegra_vde_alloc_bo(struct tegra_vde *vde, + struct tegra_vde_bo **ret_bo, + enum dma_data_direction dma_dir, + size_t size); +void tegra_vde_free_bo(struct tegra_vde_bo *bo); + +struct tegra_ctx_h264 { + const struct v4l2_ctrl_h264_decode_params *decode_params; + const struct v4l2_ctrl_h264_sps *sps; + const struct v4l2_ctrl_h264_pps *pps; +}; + +struct tegra_ctx { + struct tegra_vde *vde; + struct tegra_ctx_h264 h264; + struct work_struct work; + struct v4l2_fh fh; + struct v4l2_ctrl_handler hdl; + struct v4l2_format coded_fmt; + struct v4l2_format decoded_fmt; + const struct tegra_coded_fmt_desc *coded_fmt_desc; + struct v4l2_ctrl *ctrls[]; +}; + +struct tegra_m2m_buffer { + struct v4l2_m2m_buffer m2m; + struct dma_buf_attachment *a[VB2_MAX_PLANES]; + dma_addr_t dma_base[VB2_MAX_PLANES]; + dma_addr_t dma_addr[VB2_MAX_PLANES]; + struct iova *iova[VB2_MAX_PLANES]; + struct tegra_vde_bo *aux; + bool b_frame; +}; + +static inline struct tegra_m2m_buffer * +vb_to_tegra_buf(struct vb2_buffer *vb) +{ + struct v4l2_m2m_buffer *m2m = container_of(vb, struct v4l2_m2m_buffer, + vb.vb2_buf); + + return container_of(m2m, struct tegra_m2m_buffer, m2m); +} + +void tegra_vde_prepare_control_data(struct tegra_ctx *ctx, u32 id); + +void tegra_vde_writel(struct tegra_vde *vde, u32 value, void __iomem *base, + u32 offset); +u32 tegra_vde_readl(struct tegra_vde *vde, void __iomem *base, u32 offset); +void tegra_vde_set_bits(struct tegra_vde *vde, u32 mask, void __iomem *base, + u32 offset); + +int tegra_vde_h264_decode_run(struct tegra_ctx *ctx); +int tegra_vde_h264_decode_wait(struct tegra_ctx *ctx); + +int tegra_vde_iommu_init(struct tegra_vde *vde); +void tegra_vde_iommu_deinit(struct tegra_vde *vde); +int tegra_vde_iommu_map(struct tegra_vde *vde, + struct sg_table *sgt, + struct iova **iovap, + size_t size); +void tegra_vde_iommu_unmap(struct tegra_vde *vde, struct iova *iova); + +int tegra_vde_dmabuf_cache_map(struct tegra_vde *vde, + struct dma_buf *dmabuf, + enum dma_data_direction dma_dir, + struct dma_buf_attachment **ap, + dma_addr_t *addrp); +void tegra_vde_dmabuf_cache_unmap(struct tegra_vde *vde, + struct dma_buf_attachment *a, + bool release); +void tegra_vde_dmabuf_cache_unmap_sync(struct tegra_vde *vde); +void tegra_vde_dmabuf_cache_unmap_all(struct tegra_vde *vde); + +static __maybe_unused char const * +tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base) +{ + if (vde->sxe == base) + return "SXE"; + + if (vde->bsev == base) + return "BSEV"; + + if (vde->mbe == base) + return "MBE"; + + if (vde->ppe == base) + return "PPE"; + + if (vde->mce == base) + return "MCE"; + + if (vde->tfe == base) + return "TFE"; + + if (vde->ppb == base) + return "PPB"; + + if (vde->vdma == base) + return "VDMA"; + + if (vde->frameid == base) + return "FRAMEID"; + + return "???"; +} + +int tegra_vde_v4l2_init(struct tegra_vde *vde); +void tegra_vde_v4l2_deinit(struct tegra_vde *vde); + +#endif /* TEGRA_VDE_H */ diff --git a/drivers/media/test-drivers/vidtv/vidtv_s302m.c b/drivers/media/test-drivers/vidtv/vidtv_s302m.c index d79b65854627..4676083cee3b 100644 --- a/drivers/media/test-drivers/vidtv/vidtv_s302m.c +++ b/drivers/media/test-drivers/vidtv/vidtv_s302m.c @@ -455,6 +455,9 @@ struct vidtv_encoder e->name = kstrdup(args.name, GFP_KERNEL); e->encoder_buf = vzalloc(VIDTV_S302M_BUF_SZ); + if (!e->encoder_buf) + goto out_kfree_e; + e->encoder_buf_sz = VIDTV_S302M_BUF_SZ; e->encoder_buf_offset = 0; @@ -467,10 +470,8 @@ struct vidtv_encoder e->is_video_encoder = false; ctx = kzalloc(priv_sz, GFP_KERNEL); - if (!ctx) { - kfree(e); - return NULL; - } + if (!ctx) + goto out_kfree_buf; e->ctx = ctx; ctx->last_duration = 0; @@ -498,6 +499,14 @@ struct vidtv_encoder e->next = NULL; return e; + +out_kfree_buf: + kfree(e->encoder_buf); + +out_kfree_e: + kfree(e->name); + kfree(e); + return NULL; } void vidtv_s302m_encoder_destroy(struct vidtv_encoder *e) diff --git a/drivers/media/usb/em28xx/em28xx-cards.c b/drivers/media/usb/em28xx/em28xx-cards.c index f3b56c065ee1..ae25d2cbfdfe 100644 --- a/drivers/media/usb/em28xx/em28xx-cards.c +++ b/drivers/media/usb/em28xx/em28xx-cards.c @@ -4150,11 +4150,8 @@ static void em28xx_usb_disconnect(struct usb_interface *intf) em28xx_close_extension(dev); - if (dev->dev_next) { - em28xx_close_extension(dev->dev_next); + if (dev->dev_next) em28xx_release_resources(dev->dev_next); - } - em28xx_release_resources(dev); if (dev->dev_next) { diff --git a/drivers/media/usb/hdpvr/hdpvr-video.c b/drivers/media/usb/hdpvr/hdpvr-video.c index 563128d11731..60e57e0f1927 100644 --- a/drivers/media/usb/hdpvr/hdpvr-video.c +++ b/drivers/media/usb/hdpvr/hdpvr-video.c @@ -308,7 +308,6 @@ static int hdpvr_start_streaming(struct hdpvr_device *dev) dev->status = STATUS_STREAMING; - INIT_WORK(&dev->worker, hdpvr_transmit_buffers); schedule_work(&dev->worker); v4l2_dbg(MSG_BUFFER, hdpvr_debug, &dev->v4l2_dev, @@ -1165,6 +1164,9 @@ int hdpvr_register_videodev(struct hdpvr_device *dev, struct device *parent, bool ac3 = dev->flags & HDPVR_FLAG_AC3_CAP; int res; + // initialize dev->worker + INIT_WORK(&dev->worker, hdpvr_transmit_buffers); + dev->cur_std = V4L2_STD_525_60; dev->width = 720; dev->height = 480; diff --git a/drivers/media/usb/stk1160/stk1160-core.c b/drivers/media/usb/stk1160/stk1160-core.c index 4e1698f78818..ce717502ea4c 100644 --- a/drivers/media/usb/stk1160/stk1160-core.c +++ b/drivers/media/usb/stk1160/stk1160-core.c @@ -403,7 +403,7 @@ static void stk1160_disconnect(struct usb_interface *interface) /* Here is the only place where isoc get released */ stk1160_uninit_isoc(dev); - stk1160_clear_queue(dev); + stk1160_clear_queue(dev, VB2_BUF_STATE_ERROR); video_unregister_device(&dev->vdev); v4l2_device_disconnect(&dev->v4l2_dev); diff --git a/drivers/media/usb/stk1160/stk1160-v4l.c b/drivers/media/usb/stk1160/stk1160-v4l.c index 6a4eb616d516..a1f785a5ffd8 100644 --- a/drivers/media/usb/stk1160/stk1160-v4l.c +++ b/drivers/media/usb/stk1160/stk1160-v4l.c @@ -232,7 +232,11 @@ static int stk1160_start_streaming(struct stk1160 *dev) /* submit urbs and enables IRQ */ for (i = 0; i < dev->isoc_ctl.num_bufs; i++) { - rc = usb_submit_urb(dev->isoc_ctl.urb[i], GFP_KERNEL); + struct stk1160_urb *stk_urb = &dev->isoc_ctl.urb_ctl[i]; + + dma_sync_sgtable_for_device(stk1160_get_dmadev(dev), stk_urb->sgt, + DMA_FROM_DEVICE); + rc = usb_submit_urb(dev->isoc_ctl.urb_ctl[i].urb, GFP_KERNEL); if (rc) { stk1160_err("cannot submit urb[%d] (%d)\n", i, rc); goto out_uninit; @@ -258,7 +262,7 @@ out_uninit: stk1160_uninit_isoc(dev); out_stop_hw: usb_set_interface(dev->udev, 0, 0); - stk1160_clear_queue(dev); + stk1160_clear_queue(dev, VB2_BUF_STATE_QUEUED); mutex_unlock(&dev->v4l_lock); @@ -306,7 +310,7 @@ static int stk1160_stop_streaming(struct stk1160 *dev) stk1160_stop_hw(dev); - stk1160_clear_queue(dev); + stk1160_clear_queue(dev, VB2_BUF_STATE_ERROR); stk1160_dbg("streaming stopped\n"); @@ -745,7 +749,7 @@ static const struct video_device v4l_template = { /********************************************************************/ /* Must be called with both v4l_lock and vb_queue_lock hold */ -void stk1160_clear_queue(struct stk1160 *dev) +void stk1160_clear_queue(struct stk1160 *dev, enum vb2_buffer_state vb2_state) { struct stk1160_buffer *buf; unsigned long flags; @@ -756,7 +760,7 @@ void stk1160_clear_queue(struct stk1160 *dev) buf = list_first_entry(&dev->avail_bufs, struct stk1160_buffer, list); list_del(&buf->list); - vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + vb2_buffer_done(&buf->vb.vb2_buf, vb2_state); stk1160_dbg("buffer [%p/%d] aborted\n", buf, buf->vb.vb2_buf.index); } @@ -766,7 +770,7 @@ void stk1160_clear_queue(struct stk1160 *dev) buf = dev->isoc_ctl.buf; dev->isoc_ctl.buf = NULL; - vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR); + vb2_buffer_done(&buf->vb.vb2_buf, vb2_state); stk1160_dbg("buffer [%p/%d] aborted\n", buf, buf->vb.vb2_buf.index); } diff --git a/drivers/media/usb/stk1160/stk1160-video.c b/drivers/media/usb/stk1160/stk1160-video.c index 202b084f65a2..4e966f6bf608 100644 --- a/drivers/media/usb/stk1160/stk1160-video.c +++ b/drivers/media/usb/stk1160/stk1160-video.c @@ -295,7 +295,9 @@ static void stk1160_process_isoc(struct stk1160 *dev, struct urb *urb) static void stk1160_isoc_irq(struct urb *urb) { int i, rc; - struct stk1160 *dev = urb->context; + struct stk1160_urb *stk_urb = urb->context; + struct stk1160 *dev = stk_urb->dev; + struct device *dma_dev = stk1160_get_dmadev(dev); switch (urb->status) { case 0: @@ -310,6 +312,10 @@ static void stk1160_isoc_irq(struct urb *urb) return; } + invalidate_kernel_vmap_range(stk_urb->transfer_buffer, + urb->transfer_buffer_length); + dma_sync_sgtable_for_cpu(dma_dev, stk_urb->sgt, DMA_FROM_DEVICE); + stk1160_process_isoc(dev, urb); /* Reset urb buffers */ @@ -318,6 +324,7 @@ static void stk1160_isoc_irq(struct urb *urb) urb->iso_frame_desc[i].actual_length = 0; } + dma_sync_sgtable_for_device(dma_dev, stk_urb->sgt, DMA_FROM_DEVICE); rc = usb_submit_urb(urb, GFP_ATOMIC); if (rc) stk1160_err("urb re-submit failed (%d)\n", rc); @@ -347,49 +354,41 @@ void stk1160_cancel_isoc(struct stk1160 *dev) * We don't care for NULL pointer since * usb_kill_urb allows it. */ - usb_kill_urb(dev->isoc_ctl.urb[i]); + usb_kill_urb(dev->isoc_ctl.urb_ctl[i].urb); } stk1160_dbg("all urbs killed\n"); } +static void stk_free_urb(struct stk1160 *dev, struct stk1160_urb *stk_urb) +{ + struct device *dma_dev = stk1160_get_dmadev(dev); + + dma_vunmap_noncontiguous(dma_dev, stk_urb->transfer_buffer); + dma_free_noncontiguous(dma_dev, stk_urb->urb->transfer_buffer_length, + stk_urb->sgt, DMA_FROM_DEVICE); + usb_free_urb(stk_urb->urb); + + stk_urb->transfer_buffer = NULL; + stk_urb->sgt = NULL; + stk_urb->urb = NULL; + stk_urb->dev = NULL; + stk_urb->dma = 0; +} + /* * Releases urb and transfer buffers * Obviusly, associated urb must be killed before releasing it. */ void stk1160_free_isoc(struct stk1160 *dev) { - struct urb *urb; int i, num_bufs = dev->isoc_ctl.num_bufs; stk1160_dbg("freeing %d urb buffers...\n", num_bufs); - for (i = 0; i < num_bufs; i++) { - - urb = dev->isoc_ctl.urb[i]; - if (urb) { - - if (dev->isoc_ctl.transfer_buffer[i]) { -#ifndef CONFIG_DMA_NONCOHERENT - usb_free_coherent(dev->udev, - urb->transfer_buffer_length, - dev->isoc_ctl.transfer_buffer[i], - urb->transfer_dma); -#else - kfree(dev->isoc_ctl.transfer_buffer[i]); -#endif - } - usb_free_urb(urb); - dev->isoc_ctl.urb[i] = NULL; - } - dev->isoc_ctl.transfer_buffer[i] = NULL; - } + for (i = 0; i < num_bufs; i++) + stk_free_urb(dev, &dev->isoc_ctl.urb_ctl[i]); - kfree(dev->isoc_ctl.urb); - kfree(dev->isoc_ctl.transfer_buffer); - - dev->isoc_ctl.urb = NULL; - dev->isoc_ctl.transfer_buffer = NULL; dev->isoc_ctl.num_bufs = 0; stk1160_dbg("all urb buffers freed\n"); @@ -405,6 +404,41 @@ void stk1160_uninit_isoc(struct stk1160 *dev) stk1160_free_isoc(dev); } +static int stk1160_fill_urb(struct stk1160 *dev, struct stk1160_urb *stk_urb, + int sb_size, int max_packets) +{ + struct device *dma_dev = stk1160_get_dmadev(dev); + + stk_urb->urb = usb_alloc_urb(max_packets, GFP_KERNEL); + if (!stk_urb->urb) + return -ENOMEM; + stk_urb->sgt = dma_alloc_noncontiguous(dma_dev, sb_size, + DMA_FROM_DEVICE, GFP_KERNEL, 0); + + /* + * If the buffer allocation failed, we exit but return 0 since + * we allow the driver working with less buffers + */ + if (!stk_urb->sgt) + goto free_urb; + + stk_urb->transfer_buffer = dma_vmap_noncontiguous(dma_dev, sb_size, + stk_urb->sgt); + if (!stk_urb->transfer_buffer) + goto free_sgt; + + stk_urb->dma = stk_urb->sgt->sgl->dma_address; + stk_urb->dev = dev; + return 0; +free_sgt: + dma_free_noncontiguous(dma_dev, sb_size, stk_urb->sgt, DMA_FROM_DEVICE); + stk_urb->sgt = NULL; +free_urb: + usb_free_urb(stk_urb->urb); + stk_urb->urb = NULL; + + return 0; +} /* * Allocate URBs */ @@ -412,6 +446,7 @@ int stk1160_alloc_isoc(struct stk1160 *dev) { struct urb *urb; int i, j, k, sb_size, max_packets, num_bufs; + int ret; /* * It may be necessary to release isoc here, @@ -429,62 +464,39 @@ int stk1160_alloc_isoc(struct stk1160 *dev) dev->isoc_ctl.buf = NULL; dev->isoc_ctl.max_pkt_size = dev->max_pkt_size; - dev->isoc_ctl.urb = kcalloc(num_bufs, sizeof(void *), GFP_KERNEL); - if (!dev->isoc_ctl.urb) { - stk1160_err("out of memory for urb array\n"); - return -ENOMEM; - } - - dev->isoc_ctl.transfer_buffer = kcalloc(num_bufs, sizeof(void *), - GFP_KERNEL); - if (!dev->isoc_ctl.transfer_buffer) { - stk1160_err("out of memory for usb transfers\n"); - kfree(dev->isoc_ctl.urb); - return -ENOMEM; - } /* allocate urbs and transfer buffers */ for (i = 0; i < num_bufs; i++) { - urb = usb_alloc_urb(max_packets, GFP_KERNEL); - if (!urb) + ret = stk1160_fill_urb(dev, &dev->isoc_ctl.urb_ctl[i], + sb_size, max_packets); + if (ret) goto free_i_bufs; - dev->isoc_ctl.urb[i] = urb; - -#ifndef CONFIG_DMA_NONCOHERENT - dev->isoc_ctl.transfer_buffer[i] = usb_alloc_coherent(dev->udev, - sb_size, GFP_KERNEL, &urb->transfer_dma); -#else - dev->isoc_ctl.transfer_buffer[i] = kmalloc(sb_size, GFP_KERNEL); -#endif - if (!dev->isoc_ctl.transfer_buffer[i]) { - stk1160_err("cannot alloc %d bytes for tx[%d] buffer\n", - sb_size, i); + urb = dev->isoc_ctl.urb_ctl[i].urb; + + if (!urb) { /* Not enough transfer buffers, so just give up */ if (i < STK1160_MIN_BUFS) goto free_i_bufs; goto nomore_tx_bufs; } - memset(dev->isoc_ctl.transfer_buffer[i], 0, sb_size); + memset(dev->isoc_ctl.urb_ctl[i].transfer_buffer, 0, sb_size); /* * FIXME: Where can I get the endpoint? */ urb->dev = dev->udev; urb->pipe = usb_rcvisocpipe(dev->udev, STK1160_EP_VIDEO); - urb->transfer_buffer = dev->isoc_ctl.transfer_buffer[i]; + urb->transfer_buffer = dev->isoc_ctl.urb_ctl[i].transfer_buffer; urb->transfer_buffer_length = sb_size; urb->complete = stk1160_isoc_irq; - urb->context = dev; + urb->context = &dev->isoc_ctl.urb_ctl[i]; urb->interval = 1; urb->start_frame = 0; urb->number_of_packets = max_packets; -#ifndef CONFIG_DMA_NONCOHERENT urb->transfer_flags = URB_ISO_ASAP | URB_NO_TRANSFER_DMA_MAP; -#else - urb->transfer_flags = URB_ISO_ASAP; -#endif + urb->transfer_dma = dev->isoc_ctl.urb_ctl[i].dma; k = 0; for (j = 0; j < max_packets; j++) { @@ -508,18 +520,16 @@ nomore_tx_bufs: * enough to work fine, so we just free the extra urb, * store the allocated count and keep going, fingers crossed! */ - usb_free_urb(dev->isoc_ctl.urb[i]); - dev->isoc_ctl.urb[i] = NULL; - stk1160_warn("%d urbs allocated. Trying to continue...\n", i - 1); + stk1160_warn("%d urbs allocated. Trying to continue...\n", i); - dev->isoc_ctl.num_bufs = i - 1; + dev->isoc_ctl.num_bufs = i; return 0; free_i_bufs: /* Save the allocated buffers so far, so we can properly free them */ - dev->isoc_ctl.num_bufs = i+1; + dev->isoc_ctl.num_bufs = i; stk1160_free_isoc(dev); return -ENOMEM; } diff --git a/drivers/media/usb/stk1160/stk1160.h b/drivers/media/usb/stk1160/stk1160.h index a31ea1c80f25..7b498d14ed7a 100644 --- a/drivers/media/usb/stk1160/stk1160.h +++ b/drivers/media/usb/stk1160/stk1160.h @@ -16,6 +16,8 @@ #include <media/videobuf2-v4l2.h> #include <media/v4l2-device.h> #include <media/v4l2-ctrls.h> +#include <linux/usb.h> +#include <linux/usb/hcd.h> #define STK1160_VERSION "0.9.5" #define STK1160_VERSION_NUM 0x000905 @@ -84,6 +86,14 @@ struct stk1160_buffer { unsigned int pos; /* current pos inside buffer */ }; +struct stk1160_urb { + struct urb *urb; + char *transfer_buffer; + struct sg_table *sgt; + struct stk1160 *dev; + dma_addr_t dma; +}; + struct stk1160_isoc_ctl { /* max packet size of isoc transaction */ int max_pkt_size; @@ -91,11 +101,7 @@ struct stk1160_isoc_ctl { /* number of allocated urbs */ int num_bufs; - /* urb for isoc transfers */ - struct urb **urb; - - /* transfer buffers for isoc transfer */ - char **transfer_buffer; + struct stk1160_urb urb_ctl[STK1160_NUM_BUFS]; /* current buffer */ struct stk1160_buffer *buf; @@ -166,7 +172,7 @@ struct regval { int stk1160_vb2_setup(struct stk1160 *dev); int stk1160_video_register(struct stk1160 *dev); void stk1160_video_unregister(struct stk1160 *dev); -void stk1160_clear_queue(struct stk1160 *dev); +void stk1160_clear_queue(struct stk1160 *dev, enum vb2_buffer_state vb2_state); /* Provided by stk1160-video.c */ int stk1160_alloc_isoc(struct stk1160 *dev); @@ -189,3 +195,8 @@ void stk1160_select_input(struct stk1160 *dev); /* Provided by stk1160-ac97.c */ void stk1160_ac97_setup(struct stk1160 *dev); + +static inline struct device *stk1160_get_dmadev(struct stk1160 *dev) +{ + return bus_to_hcd(dev->udev->bus)->self.sysdev; +} diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig index b81cfa74edb7..1fd6a0c6e1d8 100644 --- a/drivers/staging/media/Kconfig +++ b/drivers/staging/media/Kconfig @@ -36,8 +36,6 @@ source "drivers/staging/media/rkvdec/Kconfig" source "drivers/staging/media/sunxi/Kconfig" -source "drivers/staging/media/tegra-vde/Kconfig" - source "drivers/staging/media/zoran/Kconfig" source "drivers/staging/media/tegra-video/Kconfig" diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile index 7e2c86e3695d..66d6f6d51c86 100644 --- a/drivers/staging/media/Makefile +++ b/drivers/staging/media/Makefile @@ -7,7 +7,6 @@ obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/ obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rkvdec/ obj-$(CONFIG_VIDEO_SUNXI) += sunxi/ obj-$(CONFIG_VIDEO_TEGRA) += tegra-video/ -obj-$(CONFIG_TEGRA_VDE) += tegra-vde/ obj-$(CONFIG_VIDEO_HANTRO) += hantro/ obj-$(CONFIG_VIDEO_IPU3_IMGU) += ipu3/ obj-$(CONFIG_VIDEO_ZORAN) += zoran/ diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index bc9bcb4eaf46..dc768884cb79 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -630,7 +630,9 @@ static const struct of_device_id of_hantro_match[] = { { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, #endif #ifdef CONFIG_VIDEO_HANTRO_IMX8M + { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, }, { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, + { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, #endif #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 @@ -905,6 +907,15 @@ static int hantro_probe(struct platform_device *pdev) match = of_match_node(of_hantro_match, pdev->dev.of_node); vpu->variant = match->data; + /* + * Support for nxp,imx8mq-vpu is kept for backwards compatibility + * but it's deprecated. Please update your DTS file to use + * nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead. + */ + if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu")) + dev_warn(&pdev->dev, "%s compatible is deprecated\n", + match->compatible); + INIT_DELAYED_WORK(&vpu->watchdog_work, hantro_watchdog); vpu->clocks = devm_kcalloc(&pdev->dev, vpu->variant->num_clocks, diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h index c1fd807bc090..ed018e293ba0 100644 --- a/drivers/staging/media/hantro/hantro_hw.h +++ b/drivers/staging/media/hantro/hantro_hw.h @@ -290,6 +290,8 @@ enum hantro_enc_fmt { ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, }; +extern const struct hantro_variant imx8mm_vpu_g1_variant; +extern const struct hantro_variant imx8mq_vpu_g1_variant; extern const struct hantro_variant imx8mq_vpu_g2_variant; extern const struct hantro_variant imx8mq_vpu_variant; extern const struct hantro_variant px30_vpu_variant; diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c index f5991b8e553a..9802508bade2 100644 --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c @@ -205,13 +205,6 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) imx8m_soft_reset(vpu, RESET_G1); } -static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx) -{ - struct hantro_dev *vpu = ctx->dev; - - imx8m_soft_reset(vpu, RESET_G2); -} - /* * Supported codec ops. */ @@ -237,17 +230,33 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { }, }; +static const struct hantro_codec_ops imx8mq_vpu_g1_codec_ops[] = { + [HANTRO_MODE_MPEG2_DEC] = { + .run = hantro_g1_mpeg2_dec_run, + .init = hantro_mpeg2_dec_init, + .exit = hantro_mpeg2_dec_exit, + }, + [HANTRO_MODE_VP8_DEC] = { + .run = hantro_g1_vp8_dec_run, + .init = hantro_vp8_dec_init, + .exit = hantro_vp8_dec_exit, + }, + [HANTRO_MODE_H264_DEC] = { + .run = hantro_g1_h264_dec_run, + .init = hantro_h264_dec_init, + .exit = hantro_h264_dec_exit, + }, +}; + static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { [HANTRO_MODE_HEVC_DEC] = { .run = hantro_g2_hevc_dec_run, - .reset = imx8m_vpu_g2_reset, .init = hantro_hevc_dec_init, .exit = hantro_hevc_dec_exit, }, [HANTRO_MODE_VP9_DEC] = { .run = hantro_g2_vp9_dec_run, .done = hantro_g2_vp9_dec_done, - .reset = imx8m_vpu_g2_reset, .init = hantro_vp9_dec_init, .exit = hantro_vp9_dec_exit, }, @@ -267,6 +276,8 @@ static const struct hantro_irq imx8mq_g2_irqs[] = { static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" }; +static const char * const imx8mq_g1_clk_names[] = { "g1" }; +static const char * const imx8mq_g2_clk_names[] = { "g2" }; const struct hantro_variant imx8mq_vpu_variant = { .dec_fmts = imx8m_vpu_dec_fmts, @@ -287,6 +298,21 @@ const struct hantro_variant imx8mq_vpu_variant = { .num_regs = ARRAY_SIZE(imx8mq_reg_names) }; +const struct hantro_variant imx8mq_vpu_g1_variant = { + .dec_fmts = imx8m_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), + .postproc_fmts = imx8m_vpu_postproc_fmts, + .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts), + .postproc_ops = &hantro_g1_postproc_ops, + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = imx8mq_vpu_g1_codec_ops, + .irqs = imx8mq_irqs, + .num_irqs = ARRAY_SIZE(imx8mq_irqs), + .clk_names = imx8mq_g1_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), +}; + const struct hantro_variant imx8mq_vpu_g2_variant = { .dec_offset = 0x0, .dec_fmts = imx8m_vpu_g2_dec_fmts, @@ -296,10 +322,20 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { .postproc_ops = &hantro_g2_postproc_ops, .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, .codec_ops = imx8mq_vpu_g2_codec_ops, - .init = imx8mq_vpu_hw_init, - .runtime_resume = imx8mq_runtime_resume, .irqs = imx8mq_g2_irqs, .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs), - .clk_names = imx8mq_clk_names, - .num_clocks = ARRAY_SIZE(imx8mq_clk_names), + .clk_names = imx8mq_g2_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names), +}; + +const struct hantro_variant imx8mm_vpu_g1_variant = { + .dec_fmts = imx8m_vpu_dec_fmts, + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | + HANTRO_H264_DECODER, + .codec_ops = imx8mq_vpu_g1_codec_ops, + .irqs = imx8mq_irqs, + .num_irqs = ARRAY_SIZE(imx8mq_irqs), + .clk_names = imx8mq_g1_clk_names, + .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), }; diff --git a/drivers/staging/media/imx/imx8mq-mipi-csi2.c b/drivers/staging/media/imx/imx8mq-mipi-csi2.c index 56ef3b3b2906..476ee8e14f19 100644 --- a/drivers/staging/media/imx/imx8mq-mipi-csi2.c +++ b/drivers/staging/media/imx/imx8mq-mipi-csi2.c @@ -693,11 +693,10 @@ err_parse: * Suspend/resume */ -static int imx8mq_mipi_csi_pm_suspend(struct device *dev) +static void imx8mq_mipi_csi_pm_suspend(struct device *dev) { struct v4l2_subdev *sd = dev_get_drvdata(dev); struct csi_state *state = mipi_sd_to_csi2_state(sd); - int ret = 0; mutex_lock(&state->lock); @@ -708,8 +707,6 @@ static int imx8mq_mipi_csi_pm_suspend(struct device *dev) } mutex_unlock(&state->lock); - - return ret ? -EAGAIN : 0; } static int imx8mq_mipi_csi_pm_resume(struct device *dev) @@ -742,15 +739,12 @@ static int __maybe_unused imx8mq_mipi_csi_suspend(struct device *dev) { struct v4l2_subdev *sd = dev_get_drvdata(dev); struct csi_state *state = mipi_sd_to_csi2_state(sd); - int ret; - ret = imx8mq_mipi_csi_pm_suspend(dev); - if (ret) - return ret; + imx8mq_mipi_csi_pm_suspend(dev); state->state |= ST_SUSPENDED; - return ret; + return 0; } static int __maybe_unused imx8mq_mipi_csi_resume(struct device *dev) @@ -770,9 +764,7 @@ static int __maybe_unused imx8mq_mipi_csi_runtime_suspend(struct device *dev) struct csi_state *state = mipi_sd_to_csi2_state(sd); int ret; - ret = imx8mq_mipi_csi_pm_suspend(dev); - if (ret) - return ret; + imx8mq_mipi_csi_pm_suspend(dev); ret = icc_set_bw(state->icc_path, 0, 0); if (ret) diff --git a/drivers/staging/media/tegra-vde/Kconfig b/drivers/staging/media/tegra-vde/Kconfig deleted file mode 100644 index 0dc78afd09e0..000000000000 --- a/drivers/staging/media/tegra-vde/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -config TEGRA_VDE - tristate "NVIDIA Tegra Video Decoder Engine driver" - depends on ARCH_TEGRA || COMPILE_TEST - select DMA_SHARED_BUFFER - select IOMMU_IOVA - select SRAM - help - Say Y here to enable support for the NVIDIA Tegra video decoder - driver. diff --git a/drivers/staging/media/tegra-vde/Makefile b/drivers/staging/media/tegra-vde/Makefile deleted file mode 100644 index 2827f7601de8..000000000000 --- a/drivers/staging/media/tegra-vde/Makefile +++ /dev/null @@ -1,3 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -tegra-vde-y := vde.o iommu.o dmabuf-cache.o -obj-$(CONFIG_TEGRA_VDE) += tegra-vde.o diff --git a/drivers/staging/media/tegra-vde/TODO b/drivers/staging/media/tegra-vde/TODO deleted file mode 100644 index 31aaa3e66d80..000000000000 --- a/drivers/staging/media/tegra-vde/TODO +++ /dev/null @@ -1,4 +0,0 @@ -TODO: - - Implement V4L2 API once it gains support for stateless decoders. - -Contact: Dmitry Osipenko <digetx@gmail.com> diff --git a/drivers/staging/media/tegra-vde/uapi.h b/drivers/staging/media/tegra-vde/uapi.h deleted file mode 100644 index ffb4983e5bb6..000000000000 --- a/drivers/staging/media/tegra-vde/uapi.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com> */ -#ifndef _UAPI_TEGRA_VDE_H_ -#define _UAPI_TEGRA_VDE_H_ - -#include <linux/types.h> -#include <asm/ioctl.h> - -#define FLAG_B_FRAME 0x1 -#define FLAG_REFERENCE 0x2 - -struct tegra_vde_h264_frame { - __s32 y_fd; - __s32 cb_fd; - __s32 cr_fd; - __s32 aux_fd; - __u32 y_offset; - __u32 cb_offset; - __u32 cr_offset; - __u32 aux_offset; - __u32 frame_num; - __u32 flags; - - // Must be zero'ed - __u32 reserved[6]; -}; - -struct tegra_vde_h264_decoder_ctx { - __s32 bitstream_data_fd; - __u32 bitstream_data_offset; - - __u64 dpb_frames_ptr; - __u32 dpb_frames_nb; - __u32 dpb_ref_frames_with_earlier_poc_nb; - - // SPS - __u32 baseline_profile; - __u32 level_idc; - __u32 log2_max_pic_order_cnt_lsb; - __u32 log2_max_frame_num; - __u32 pic_order_cnt_type; - __u32 direct_8x8_inference_flag; - __u32 pic_width_in_mbs; - __u32 pic_height_in_mbs; - - // PPS - __u32 pic_init_qp; - __u32 deblocking_filter_control_present_flag; - __u32 constrained_intra_pred_flag; - __u32 chroma_qp_index_offset; - __u32 pic_order_present_flag; - - // Slice header - __u32 num_ref_idx_l0_active_minus1; - __u32 num_ref_idx_l1_active_minus1; - - // Must be zero'ed - __u32 reserved[11]; -}; - -#define VDE_IOCTL_BASE ('v' + 0x20) - -#define VDE_IO(nr) _IO(VDE_IOCTL_BASE, nr) -#define VDE_IOR(nr, type) _IOR(VDE_IOCTL_BASE, nr, type) -#define VDE_IOW(nr, type) _IOW(VDE_IOCTL_BASE, nr, type) -#define VDE_IOWR(nr, type) _IOWR(VDE_IOCTL_BASE, nr, type) - -#define TEGRA_VDE_DECODE_H264 0x00 - -#define TEGRA_VDE_IOCTL_DECODE_H264 \ - VDE_IOW(TEGRA_VDE_DECODE_H264, struct tegra_vde_h264_decoder_ctx) - -#endif // _UAPI_TEGRA_VDE_H_ diff --git a/drivers/staging/media/tegra-vde/vde.c b/drivers/staging/media/tegra-vde/vde.c deleted file mode 100644 index a8f1a024c343..000000000000 --- a/drivers/staging/media/tegra-vde/vde.c +++ /dev/null @@ -1,1358 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * NVIDIA Tegra Video decoder driver - * - * Copyright (C) 2016-2017 Dmitry Osipenko <digetx@gmail.com> - * - */ - -#include <linux/clk.h> -#include <linux/dma-buf.h> -#include <linux/genalloc.h> -#include <linux/interrupt.h> -#include <linux/iopoll.h> -#include <linux/list.h> -#include <linux/miscdevice.h> -#include <linux/module.h> -#include <linux/of_device.h> -#include <linux/pm_runtime.h> -#include <linux/reset.h> -#include <linux/slab.h> -#include <linux/uaccess.h> - -#include <soc/tegra/common.h> -#include <soc/tegra/pmc.h> - -#include "uapi.h" -#include "vde.h" - -#define CREATE_TRACE_POINTS -#include "trace.h" - -#define ICMDQUE_WR 0x00 -#define CMDQUE_CONTROL 0x08 -#define INTR_STATUS 0x18 -#define BSE_INT_ENB 0x40 -#define BSE_CONFIG 0x44 - -#define BSE_ICMDQUE_EMPTY BIT(3) -#define BSE_DMA_BUSY BIT(23) - -struct video_frame { - struct dma_buf_attachment *y_dmabuf_attachment; - struct dma_buf_attachment *cb_dmabuf_attachment; - struct dma_buf_attachment *cr_dmabuf_attachment; - struct dma_buf_attachment *aux_dmabuf_attachment; - dma_addr_t y_addr; - dma_addr_t cb_addr; - dma_addr_t cr_addr; - dma_addr_t aux_addr; - u32 frame_num; - u32 flags; -}; - -static void tegra_vde_writel(struct tegra_vde *vde, - u32 value, void __iomem *base, u32 offset) -{ - trace_vde_writel(vde, base, offset, value); - - writel_relaxed(value, base + offset); -} - -static u32 tegra_vde_readl(struct tegra_vde *vde, - void __iomem *base, u32 offset) -{ - u32 value = readl_relaxed(base + offset); - - trace_vde_readl(vde, base, offset, value); - - return value; -} - -static void tegra_vde_set_bits(struct tegra_vde *vde, - u32 mask, void __iomem *base, u32 offset) -{ - u32 value = tegra_vde_readl(vde, base, offset); - - tegra_vde_writel(vde, value | mask, base, offset); -} - -static int tegra_vde_wait_mbe(struct tegra_vde *vde) -{ - u32 tmp; - - return readl_relaxed_poll_timeout(vde->mbe + 0x8C, tmp, - (tmp >= 0x10), 1, 100); -} - -static int tegra_vde_alloc_bo(struct tegra_vde *vde, - struct tegra_vde_bo **ret_bo, - enum dma_data_direction dma_dir, - size_t size) -{ - struct device *dev = vde->miscdev.parent; - struct tegra_vde_bo *bo; - int err; - - bo = kzalloc(sizeof(*bo), GFP_KERNEL); - if (!bo) - return -ENOMEM; - - bo->vde = vde; - bo->size = size; - bo->dma_dir = dma_dir; - bo->dma_attrs = DMA_ATTR_WRITE_COMBINE | - DMA_ATTR_NO_KERNEL_MAPPING; - - if (!vde->domain) - bo->dma_attrs |= DMA_ATTR_FORCE_CONTIGUOUS; - - bo->dma_cookie = dma_alloc_attrs(dev, bo->size, &bo->dma_handle, - GFP_KERNEL, bo->dma_attrs); - if (!bo->dma_cookie) { - dev_err(dev, "Failed to allocate DMA buffer of size: %zu\n", - bo->size); - err = -ENOMEM; - goto free_bo; - } - - err = dma_get_sgtable_attrs(dev, &bo->sgt, bo->dma_cookie, - bo->dma_handle, bo->size, bo->dma_attrs); - if (err) { - dev_err(dev, "Failed to get DMA buffer SG table: %d\n", err); - goto free_attrs; - } - - err = dma_map_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs); - if (err) { - dev_err(dev, "Failed to map DMA buffer SG table: %d\n", err); - goto free_table; - } - - if (vde->domain) { - err = tegra_vde_iommu_map(vde, &bo->sgt, &bo->iova, bo->size); - if (err) { - dev_err(dev, "Failed to map DMA buffer IOVA: %d\n", err); - goto unmap_sgtable; - } - - bo->dma_addr = iova_dma_addr(&vde->iova, bo->iova); - } else { - bo->dma_addr = sg_dma_address(bo->sgt.sgl); - } - - *ret_bo = bo; - - return 0; - -unmap_sgtable: - dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs); -free_table: - sg_free_table(&bo->sgt); -free_attrs: - dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle, - bo->dma_attrs); -free_bo: - kfree(bo); - - return err; -} - -static void tegra_vde_free_bo(struct tegra_vde_bo *bo) -{ - struct tegra_vde *vde = bo->vde; - struct device *dev = vde->miscdev.parent; - - if (vde->domain) - tegra_vde_iommu_unmap(vde, bo->iova); - - dma_unmap_sgtable(dev, &bo->sgt, bo->dma_dir, bo->dma_attrs); - - sg_free_table(&bo->sgt); - - dma_free_attrs(dev, bo->size, bo->dma_cookie, bo->dma_handle, - bo->dma_attrs); - kfree(bo); -} - -static int tegra_vde_setup_mbe_frame_idx(struct tegra_vde *vde, - unsigned int refs_nb, - bool setup_refs) -{ - u32 frame_idx_enb_mask = 0; - u32 value; - unsigned int frame_idx; - unsigned int idx; - int err; - - tegra_vde_writel(vde, 0xD0000000 | (0 << 23), vde->mbe, 0x80); - tegra_vde_writel(vde, 0xD0200000 | (0 << 23), vde->mbe, 0x80); - - err = tegra_vde_wait_mbe(vde); - if (err) - return err; - - if (!setup_refs) - return 0; - - for (idx = 0, frame_idx = 1; idx < refs_nb; idx++, frame_idx++) { - tegra_vde_writel(vde, 0xD0000000 | (frame_idx << 23), - vde->mbe, 0x80); - tegra_vde_writel(vde, 0xD0200000 | (frame_idx << 23), - vde->mbe, 0x80); - - frame_idx_enb_mask |= frame_idx << (6 * (idx % 4)); - - if (idx % 4 == 3 || idx == refs_nb - 1) { - value = 0xC0000000; - value |= (idx >> 2) << 24; - value |= frame_idx_enb_mask; - - tegra_vde_writel(vde, value, vde->mbe, 0x80); - - err = tegra_vde_wait_mbe(vde); - if (err) - return err; - - frame_idx_enb_mask = 0; - } - } - - return 0; -} - -static void tegra_vde_mbe_set_0xa_reg(struct tegra_vde *vde, int reg, u32 val) -{ - tegra_vde_writel(vde, 0xA0000000 | (reg << 24) | (val & 0xFFFF), - vde->mbe, 0x80); - tegra_vde_writel(vde, 0xA0000000 | ((reg + 1) << 24) | (val >> 16), - vde->mbe, 0x80); -} - -static int tegra_vde_wait_bsev(struct tegra_vde *vde, bool wait_dma) -{ - struct device *dev = vde->miscdev.parent; - u32 value; - int err; - - err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, - !(value & BIT(2)), 1, 100); - if (err) { - dev_err(dev, "BSEV unknown bit timeout\n"); - return err; - } - - err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, - (value & BSE_ICMDQUE_EMPTY), 1, 100); - if (err) { - dev_err(dev, "BSEV ICMDQUE flush timeout\n"); - return err; - } - - if (!wait_dma) - return 0; - - err = readl_relaxed_poll_timeout(vde->bsev + INTR_STATUS, value, - !(value & BSE_DMA_BUSY), 1, 100); - if (err) { - dev_err(dev, "BSEV DMA timeout\n"); - return err; - } - - return 0; -} - -static int tegra_vde_push_to_bsev_icmdqueue(struct tegra_vde *vde, - u32 value, bool wait_dma) -{ - tegra_vde_writel(vde, value, vde->bsev, ICMDQUE_WR); - - return tegra_vde_wait_bsev(vde, wait_dma); -} - -static void tegra_vde_setup_frameid(struct tegra_vde *vde, - struct video_frame *frame, - unsigned int frameid, - u32 mbs_width, u32 mbs_height) -{ - u32 y_addr = frame ? frame->y_addr : 0x6CDEAD00; - u32 cb_addr = frame ? frame->cb_addr : 0x6CDEAD00; - u32 cr_addr = frame ? frame->cr_addr : 0x6CDEAD00; - u32 value1 = frame ? ((mbs_width << 16) | mbs_height) : 0; - u32 value2 = frame ? ((((mbs_width + 1) >> 1) << 6) | 1) : 0; - - tegra_vde_writel(vde, y_addr >> 8, vde->frameid, 0x000 + frameid * 4); - tegra_vde_writel(vde, cb_addr >> 8, vde->frameid, 0x100 + frameid * 4); - tegra_vde_writel(vde, cr_addr >> 8, vde->frameid, 0x180 + frameid * 4); - tegra_vde_writel(vde, value1, vde->frameid, 0x080 + frameid * 4); - tegra_vde_writel(vde, value2, vde->frameid, 0x280 + frameid * 4); -} - -static void tegra_setup_frameidx(struct tegra_vde *vde, - struct video_frame *frames, - unsigned int frames_nb, - u32 mbs_width, u32 mbs_height) -{ - unsigned int idx; - - for (idx = 0; idx < frames_nb; idx++) - tegra_vde_setup_frameid(vde, &frames[idx], idx, - mbs_width, mbs_height); - - for (; idx < 17; idx++) - tegra_vde_setup_frameid(vde, NULL, idx, 0, 0); -} - -static void tegra_vde_setup_iram_entry(struct tegra_vde *vde, - unsigned int table, - unsigned int row, - u32 value1, u32 value2) -{ - u32 *iram_tables = vde->iram; - - trace_vde_setup_iram_entry(table, row, value1, value2); - - iram_tables[0x20 * table + row * 2] = value1; - iram_tables[0x20 * table + row * 2 + 1] = value2; -} - -static void tegra_vde_setup_iram_tables(struct tegra_vde *vde, - struct video_frame *dpb_frames, - unsigned int ref_frames_nb, - unsigned int with_earlier_poc_nb) -{ - struct video_frame *frame; - u32 value, aux_addr; - int with_later_poc_nb; - unsigned int i, k; - - trace_vde_ref_l0(dpb_frames[0].frame_num); - - for (i = 0; i < 16; i++) { - if (i < ref_frames_nb) { - frame = &dpb_frames[i + 1]; - - aux_addr = frame->aux_addr; - - value = (i + 1) << 26; - value |= !(frame->flags & FLAG_B_FRAME) << 25; - value |= 1 << 24; - value |= frame->frame_num; - } else { - aux_addr = 0x6ADEAD00; - value = 0x3f; - } - - tegra_vde_setup_iram_entry(vde, 0, i, value, aux_addr); - tegra_vde_setup_iram_entry(vde, 1, i, value, aux_addr); - tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); - tegra_vde_setup_iram_entry(vde, 3, i, value, aux_addr); - } - - if (!(dpb_frames[0].flags & FLAG_B_FRAME)) - return; - - if (with_earlier_poc_nb >= ref_frames_nb) - return; - - with_later_poc_nb = ref_frames_nb - with_earlier_poc_nb; - - trace_vde_ref_l1(with_later_poc_nb, with_earlier_poc_nb); - - for (i = 0, k = with_earlier_poc_nb; i < with_later_poc_nb; i++, k++) { - frame = &dpb_frames[k + 1]; - - aux_addr = frame->aux_addr; - - value = (k + 1) << 26; - value |= !(frame->flags & FLAG_B_FRAME) << 25; - value |= 1 << 24; - value |= frame->frame_num; - - tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); - } - - for (k = 0; i < ref_frames_nb; i++, k++) { - frame = &dpb_frames[k + 1]; - - aux_addr = frame->aux_addr; - - value = (k + 1) << 26; - value |= !(frame->flags & FLAG_B_FRAME) << 25; - value |= 1 << 24; - value |= frame->frame_num; - - tegra_vde_setup_iram_entry(vde, 2, i, value, aux_addr); - } -} - -static int tegra_vde_setup_hw_context(struct tegra_vde *vde, - struct tegra_vde_h264_decoder_ctx *ctx, - struct video_frame *dpb_frames, - dma_addr_t bitstream_data_addr, - size_t bitstream_data_size, - unsigned int macroblocks_nb) -{ - struct device *dev = vde->miscdev.parent; - u32 value; - int err; - - tegra_vde_set_bits(vde, 0x000A, vde->sxe, 0xF0); - tegra_vde_set_bits(vde, 0x000B, vde->bsev, CMDQUE_CONTROL); - tegra_vde_set_bits(vde, 0x8002, vde->mbe, 0x50); - tegra_vde_set_bits(vde, 0x000A, vde->mbe, 0xA0); - tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x14); - tegra_vde_set_bits(vde, 0x000A, vde->ppe, 0x28); - tegra_vde_set_bits(vde, 0x0A00, vde->mce, 0x08); - tegra_vde_set_bits(vde, 0x000A, vde->tfe, 0x00); - tegra_vde_set_bits(vde, 0x0005, vde->vdma, 0x04); - - tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x1C); - tegra_vde_writel(vde, 0x00000000, vde->vdma, 0x00); - tegra_vde_writel(vde, 0x00000007, vde->vdma, 0x04); - tegra_vde_writel(vde, 0x00000007, vde->frameid, 0x200); - tegra_vde_writel(vde, 0x00000005, vde->tfe, 0x04); - tegra_vde_writel(vde, 0x00000000, vde->mbe, 0x84); - tegra_vde_writel(vde, 0x00000010, vde->sxe, 0x08); - tegra_vde_writel(vde, 0x00000150, vde->sxe, 0x54); - tegra_vde_writel(vde, 0x0000054C, vde->sxe, 0x58); - tegra_vde_writel(vde, 0x00000E34, vde->sxe, 0x5C); - tegra_vde_writel(vde, 0x063C063C, vde->mce, 0x10); - tegra_vde_writel(vde, 0x0003FC00, vde->bsev, INTR_STATUS); - tegra_vde_writel(vde, 0x0000150D, vde->bsev, BSE_CONFIG); - tegra_vde_writel(vde, 0x00000100, vde->bsev, BSE_INT_ENB); - tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x98); - tegra_vde_writel(vde, 0x00000060, vde->bsev, 0x9C); - - memset(vde->iram + 128, 0, macroblocks_nb / 2); - - tegra_setup_frameidx(vde, dpb_frames, ctx->dpb_frames_nb, - ctx->pic_width_in_mbs, ctx->pic_height_in_mbs); - - tegra_vde_setup_iram_tables(vde, dpb_frames, - ctx->dpb_frames_nb - 1, - ctx->dpb_ref_frames_with_earlier_poc_nb); - - /* - * The IRAM mapping is write-combine, ensure that CPU buffers have - * been flushed at this point. - */ - wmb(); - - tegra_vde_writel(vde, 0x00000000, vde->bsev, 0x8C); - tegra_vde_writel(vde, bitstream_data_addr + bitstream_data_size, - vde->bsev, 0x54); - - value = ctx->pic_width_in_mbs << 11 | ctx->pic_height_in_mbs << 3; - - tegra_vde_writel(vde, value, vde->bsev, 0x88); - - err = tegra_vde_wait_bsev(vde, false); - if (err) - return err; - - err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x800003FC, false); - if (err) - return err; - - value = 0x01500000; - value |= ((vde->iram_lists_addr + 512) >> 2) & 0xFFFF; - - err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true); - if (err) - return err; - - err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x840F054C, false); - if (err) - return err; - - err = tegra_vde_push_to_bsev_icmdqueue(vde, 0x80000080, false); - if (err) - return err; - - value = 0x0E340000 | ((vde->iram_lists_addr >> 2) & 0xFFFF); - - err = tegra_vde_push_to_bsev_icmdqueue(vde, value, true); - if (err) - return err; - - value = 0x00800005; - value |= ctx->pic_width_in_mbs << 11; - value |= ctx->pic_height_in_mbs << 3; - - tegra_vde_writel(vde, value, vde->sxe, 0x10); - - value = !ctx->baseline_profile << 17; - value |= ctx->level_idc << 13; - value |= ctx->log2_max_pic_order_cnt_lsb << 7; - value |= ctx->pic_order_cnt_type << 5; - value |= ctx->log2_max_frame_num; - - tegra_vde_writel(vde, value, vde->sxe, 0x40); - - value = ctx->pic_init_qp << 25; - value |= !!(ctx->deblocking_filter_control_present_flag) << 2; - value |= !!ctx->pic_order_present_flag; - - tegra_vde_writel(vde, value, vde->sxe, 0x44); - - value = ctx->chroma_qp_index_offset; - value |= ctx->num_ref_idx_l0_active_minus1 << 5; - value |= ctx->num_ref_idx_l1_active_minus1 << 10; - value |= !!ctx->constrained_intra_pred_flag << 15; - - tegra_vde_writel(vde, value, vde->sxe, 0x48); - - value = 0x0C000000; - value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 24; - - tegra_vde_writel(vde, value, vde->sxe, 0x4C); - - value = 0x03800000; - value |= bitstream_data_size & GENMASK(19, 15); - - tegra_vde_writel(vde, value, vde->sxe, 0x68); - - tegra_vde_writel(vde, bitstream_data_addr, vde->sxe, 0x6C); - - if (vde->soc->supports_ref_pic_marking) - tegra_vde_writel(vde, vde->secure_bo->dma_addr, vde->sxe, 0x7c); - - value = 0x10000005; - value |= ctx->pic_width_in_mbs << 11; - value |= ctx->pic_height_in_mbs << 3; - - tegra_vde_writel(vde, value, vde->mbe, 0x80); - - value = 0x26800000; - value |= ctx->level_idc << 4; - value |= !ctx->baseline_profile << 1; - value |= !!ctx->direct_8x8_inference_flag; - - tegra_vde_writel(vde, value, vde->mbe, 0x80); - - tegra_vde_writel(vde, 0xF4000001, vde->mbe, 0x80); - tegra_vde_writel(vde, 0x20000000, vde->mbe, 0x80); - tegra_vde_writel(vde, 0xF4000101, vde->mbe, 0x80); - - value = 0x20000000; - value |= ctx->chroma_qp_index_offset << 8; - - tegra_vde_writel(vde, value, vde->mbe, 0x80); - - err = tegra_vde_setup_mbe_frame_idx(vde, - ctx->dpb_frames_nb - 1, - ctx->pic_order_cnt_type == 0); - if (err) { - dev_err(dev, "MBE frames setup failed %d\n", err); - return err; - } - - tegra_vde_mbe_set_0xa_reg(vde, 0, 0x000009FC); - tegra_vde_mbe_set_0xa_reg(vde, 2, 0x61DEAD00); - tegra_vde_mbe_set_0xa_reg(vde, 4, 0x62DEAD00); - tegra_vde_mbe_set_0xa_reg(vde, 6, 0x63DEAD00); - tegra_vde_mbe_set_0xa_reg(vde, 8, dpb_frames[0].aux_addr); - - value = 0xFC000000; - value |= !!(dpb_frames[0].flags & FLAG_B_FRAME) << 2; - - if (!ctx->baseline_profile) - value |= !!(dpb_frames[0].flags & FLAG_REFERENCE) << 1; - - tegra_vde_writel(vde, value, vde->mbe, 0x80); - - err = tegra_vde_wait_mbe(vde); - if (err) { - dev_err(dev, "MBE programming failed %d\n", err); - return err; - } - - return 0; -} - -static void tegra_vde_decode_frame(struct tegra_vde *vde, - unsigned int macroblocks_nb) -{ - reinit_completion(&vde->decode_completion); - - tegra_vde_writel(vde, 0x00000001, vde->bsev, 0x8C); - tegra_vde_writel(vde, 0x20000000 | (macroblocks_nb - 1), - vde->sxe, 0x00); -} - -static int tegra_vde_attach_dmabuf(struct tegra_vde *vde, - int fd, - unsigned long offset, - size_t min_size, - size_t align_size, - struct dma_buf_attachment **a, - dma_addr_t *addrp, - size_t *size, - enum dma_data_direction dma_dir) -{ - struct device *dev = vde->miscdev.parent; - struct dma_buf *dmabuf; - int err; - - dmabuf = dma_buf_get(fd); - if (IS_ERR(dmabuf)) { - dev_err(dev, "Invalid dmabuf FD\n"); - return PTR_ERR(dmabuf); - } - - if (dmabuf->size & (align_size - 1)) { - dev_err(dev, "Unaligned dmabuf 0x%zX, should be aligned to 0x%zX\n", - dmabuf->size, align_size); - return -EINVAL; - } - - if ((u64)offset + min_size > dmabuf->size) { - dev_err(dev, "Too small dmabuf size %zu @0x%lX, should be at least %zu\n", - dmabuf->size, offset, min_size); - return -EINVAL; - } - - err = tegra_vde_dmabuf_cache_map(vde, dmabuf, dma_dir, a, addrp); - if (err) - goto err_put; - - *addrp = *addrp + offset; - - if (size) - *size = dmabuf->size - offset; - - return 0; - -err_put: - dma_buf_put(dmabuf); - - return err; -} - -static int tegra_vde_attach_dmabufs_to_frame(struct tegra_vde *vde, - struct video_frame *frame, - struct tegra_vde_h264_frame *src, - enum dma_data_direction dma_dir, - bool baseline_profile, - size_t lsize, size_t csize) -{ - int err; - - err = tegra_vde_attach_dmabuf(vde, src->y_fd, - src->y_offset, lsize, SZ_256, - &frame->y_dmabuf_attachment, - &frame->y_addr, - NULL, dma_dir); - if (err) - return err; - - err = tegra_vde_attach_dmabuf(vde, src->cb_fd, - src->cb_offset, csize, SZ_256, - &frame->cb_dmabuf_attachment, - &frame->cb_addr, - NULL, dma_dir); - if (err) - goto err_release_y; - - err = tegra_vde_attach_dmabuf(vde, src->cr_fd, - src->cr_offset, csize, SZ_256, - &frame->cr_dmabuf_attachment, - &frame->cr_addr, - NULL, dma_dir); - if (err) - goto err_release_cb; - - if (baseline_profile) { - frame->aux_addr = 0x64DEAD00; - return 0; - } - - err = tegra_vde_attach_dmabuf(vde, src->aux_fd, - src->aux_offset, csize, SZ_256, - &frame->aux_dmabuf_attachment, - &frame->aux_addr, - NULL, dma_dir); - if (err) - goto err_release_cr; - - return 0; - -err_release_cr: - tegra_vde_dmabuf_cache_unmap(vde, frame->cr_dmabuf_attachment, true); -err_release_cb: - tegra_vde_dmabuf_cache_unmap(vde, frame->cb_dmabuf_attachment, true); -err_release_y: - tegra_vde_dmabuf_cache_unmap(vde, frame->y_dmabuf_attachment, true); - - return err; -} - -static void tegra_vde_release_frame_dmabufs(struct tegra_vde *vde, - struct video_frame *frame, - enum dma_data_direction dma_dir, - bool baseline_profile, - bool release) -{ - if (!baseline_profile) - tegra_vde_dmabuf_cache_unmap(vde, frame->aux_dmabuf_attachment, - release); - - tegra_vde_dmabuf_cache_unmap(vde, frame->cr_dmabuf_attachment, release); - tegra_vde_dmabuf_cache_unmap(vde, frame->cb_dmabuf_attachment, release); - tegra_vde_dmabuf_cache_unmap(vde, frame->y_dmabuf_attachment, release); -} - -static int tegra_vde_validate_frame(struct device *dev, - struct tegra_vde_h264_frame *frame) -{ - if (frame->frame_num > 0x7FFFFF) { - dev_err(dev, "Bad frame_num %u\n", frame->frame_num); - return -EINVAL; - } - - return 0; -} - -static int tegra_vde_validate_h264_ctx(struct device *dev, - struct tegra_vde_h264_decoder_ctx *ctx) -{ - if (ctx->dpb_frames_nb == 0 || ctx->dpb_frames_nb > 17) { - dev_err(dev, "Bad DPB size %u\n", ctx->dpb_frames_nb); - return -EINVAL; - } - - if (ctx->level_idc > 15) { - dev_err(dev, "Bad level value %u\n", ctx->level_idc); - return -EINVAL; - } - - if (ctx->pic_init_qp > 52) { - dev_err(dev, "Bad pic_init_qp value %u\n", ctx->pic_init_qp); - return -EINVAL; - } - - if (ctx->log2_max_pic_order_cnt_lsb > 16) { - dev_err(dev, "Bad log2_max_pic_order_cnt_lsb value %u\n", - ctx->log2_max_pic_order_cnt_lsb); - return -EINVAL; - } - - if (ctx->log2_max_frame_num > 16) { - dev_err(dev, "Bad log2_max_frame_num value %u\n", - ctx->log2_max_frame_num); - return -EINVAL; - } - - if (ctx->chroma_qp_index_offset > 31) { - dev_err(dev, "Bad chroma_qp_index_offset value %u\n", - ctx->chroma_qp_index_offset); - return -EINVAL; - } - - if (ctx->pic_order_cnt_type > 2) { - dev_err(dev, "Bad pic_order_cnt_type value %u\n", - ctx->pic_order_cnt_type); - return -EINVAL; - } - - if (ctx->num_ref_idx_l0_active_minus1 > 15) { - dev_err(dev, "Bad num_ref_idx_l0_active_minus1 value %u\n", - ctx->num_ref_idx_l0_active_minus1); - return -EINVAL; - } - - if (ctx->num_ref_idx_l1_active_minus1 > 15) { - dev_err(dev, "Bad num_ref_idx_l1_active_minus1 value %u\n", - ctx->num_ref_idx_l1_active_minus1); - return -EINVAL; - } - - if (!ctx->pic_width_in_mbs || ctx->pic_width_in_mbs > 127) { - dev_err(dev, "Bad pic_width_in_mbs value %u\n", - ctx->pic_width_in_mbs); - return -EINVAL; - } - - if (!ctx->pic_height_in_mbs || ctx->pic_height_in_mbs > 127) { - dev_err(dev, "Bad pic_height_in_mbs value %u\n", - ctx->pic_height_in_mbs); - return -EINVAL; - } - - return 0; -} - -static int tegra_vde_ioctl_decode_h264(struct tegra_vde *vde, - unsigned long vaddr) -{ - struct device *dev = vde->miscdev.parent; - struct tegra_vde_h264_decoder_ctx ctx; - struct tegra_vde_h264_frame *frames; - struct tegra_vde_h264_frame __user *frames_user; - struct video_frame *dpb_frames; - struct dma_buf_attachment *bitstream_data_dmabuf_attachment; - enum dma_data_direction dma_dir; - dma_addr_t bitstream_data_addr; - dma_addr_t bsev_ptr; - size_t lsize, csize; - size_t bitstream_data_size; - unsigned int macroblocks_nb; - unsigned int read_bytes; - unsigned int cstride; - unsigned int i; - long timeout; - int ret, err; - - if (copy_from_user(&ctx, (void __user *)vaddr, sizeof(ctx))) - return -EFAULT; - - ret = tegra_vde_validate_h264_ctx(dev, &ctx); - if (ret) - return ret; - - ret = tegra_vde_attach_dmabuf(vde, ctx.bitstream_data_fd, - ctx.bitstream_data_offset, - SZ_16K, SZ_16K, - &bitstream_data_dmabuf_attachment, - &bitstream_data_addr, - &bitstream_data_size, - DMA_TO_DEVICE); - if (ret) - return ret; - - frames = kmalloc_array(ctx.dpb_frames_nb, sizeof(*frames), GFP_KERNEL); - if (!frames) { - ret = -ENOMEM; - goto release_bitstream_dmabuf; - } - - dpb_frames = kcalloc(ctx.dpb_frames_nb, sizeof(*dpb_frames), - GFP_KERNEL); - if (!dpb_frames) { - ret = -ENOMEM; - goto free_frames; - } - - macroblocks_nb = ctx.pic_width_in_mbs * ctx.pic_height_in_mbs; - frames_user = u64_to_user_ptr(ctx.dpb_frames_ptr); - - if (copy_from_user(frames, frames_user, - ctx.dpb_frames_nb * sizeof(*frames))) { - ret = -EFAULT; - goto free_dpb_frames; - } - - cstride = ALIGN(ctx.pic_width_in_mbs * 8, 16); - csize = cstride * ctx.pic_height_in_mbs * 8; - lsize = macroblocks_nb * 256; - - for (i = 0; i < ctx.dpb_frames_nb; i++) { - ret = tegra_vde_validate_frame(dev, &frames[i]); - if (ret) - goto release_dpb_frames; - - dpb_frames[i].flags = frames[i].flags; - dpb_frames[i].frame_num = frames[i].frame_num; - - dma_dir = (i == 0) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; - - ret = tegra_vde_attach_dmabufs_to_frame(vde, &dpb_frames[i], - &frames[i], dma_dir, - ctx.baseline_profile, - lsize, csize); - if (ret) - goto release_dpb_frames; - } - - ret = mutex_lock_interruptible(&vde->lock); - if (ret) - goto release_dpb_frames; - - ret = pm_runtime_resume_and_get(dev); - if (ret < 0) - goto unlock; - - /* - * We rely on the VDE registers reset value, otherwise VDE - * causes bus lockup. - */ - ret = reset_control_assert(vde->rst_mc); - if (ret) { - dev_err(dev, "DEC start: Failed to assert MC reset: %d\n", - ret); - goto put_runtime_pm; - } - - ret = reset_control_reset(vde->rst); - if (ret) { - dev_err(dev, "DEC start: Failed to reset HW: %d\n", ret); - goto put_runtime_pm; - } - - ret = reset_control_deassert(vde->rst_mc); - if (ret) { - dev_err(dev, "DEC start: Failed to deassert MC reset: %d\n", - ret); - goto put_runtime_pm; - } - - ret = tegra_vde_setup_hw_context(vde, &ctx, dpb_frames, - bitstream_data_addr, - bitstream_data_size, - macroblocks_nb); - if (ret) - goto put_runtime_pm; - - tegra_vde_decode_frame(vde, macroblocks_nb); - - timeout = wait_for_completion_interruptible_timeout( - &vde->decode_completion, msecs_to_jiffies(1000)); - if (timeout == 0) { - bsev_ptr = tegra_vde_readl(vde, vde->bsev, 0x10); - macroblocks_nb = tegra_vde_readl(vde, vde->sxe, 0xC8) & 0x1FFF; - read_bytes = bsev_ptr ? bsev_ptr - bitstream_data_addr : 0; - - dev_err(dev, "Decoding failed: read 0x%X bytes, %u macroblocks parsed\n", - read_bytes, macroblocks_nb); - - ret = -EIO; - } else if (timeout < 0) { - ret = timeout; - } - - /* - * At first reset memory client to avoid resetting VDE HW in the - * middle of DMA which could result into memory corruption or hang - * the whole system. - */ - err = reset_control_assert(vde->rst_mc); - if (err) - dev_err(dev, "DEC end: Failed to assert MC reset: %d\n", err); - - err = reset_control_assert(vde->rst); - if (err) - dev_err(dev, "DEC end: Failed to assert HW reset: %d\n", err); - -put_runtime_pm: - pm_runtime_mark_last_busy(dev); - pm_runtime_put_autosuspend(dev); - -unlock: - mutex_unlock(&vde->lock); - -release_dpb_frames: - while (i--) { - dma_dir = (i == 0) ? DMA_FROM_DEVICE : DMA_TO_DEVICE; - - tegra_vde_release_frame_dmabufs(vde, &dpb_frames[i], dma_dir, - ctx.baseline_profile, ret != 0); - } - -free_dpb_frames: - kfree(dpb_frames); - -free_frames: - kfree(frames); - -release_bitstream_dmabuf: - tegra_vde_dmabuf_cache_unmap(vde, bitstream_data_dmabuf_attachment, - ret != 0); - - return ret; -} - -static long tegra_vde_unlocked_ioctl(struct file *filp, - unsigned int cmd, unsigned long arg) -{ - struct miscdevice *miscdev = filp->private_data; - struct tegra_vde *vde = container_of(miscdev, struct tegra_vde, - miscdev); - - switch (cmd) { - case TEGRA_VDE_IOCTL_DECODE_H264: - return tegra_vde_ioctl_decode_h264(vde, arg); - } - - dev_err(miscdev->parent, "Invalid IOCTL command %u\n", cmd); - - return -ENOTTY; -} - -static int tegra_vde_release_file(struct inode *inode, struct file *filp) -{ - struct miscdevice *miscdev = filp->private_data; - struct tegra_vde *vde = container_of(miscdev, struct tegra_vde, - miscdev); - - tegra_vde_dmabuf_cache_unmap_sync(vde); - - return 0; -} - -static const struct file_operations tegra_vde_fops = { - .owner = THIS_MODULE, - .unlocked_ioctl = tegra_vde_unlocked_ioctl, - .release = tegra_vde_release_file, -}; - -static irqreturn_t tegra_vde_isr(int irq, void *data) -{ - struct tegra_vde *vde = data; - - if (completion_done(&vde->decode_completion)) - return IRQ_NONE; - - tegra_vde_set_bits(vde, 0, vde->frameid, 0x208); - complete(&vde->decode_completion); - - return IRQ_HANDLED; -} - -static __maybe_unused int tegra_vde_runtime_suspend(struct device *dev) -{ - struct tegra_vde *vde = dev_get_drvdata(dev); - int err; - - if (!dev->pm_domain) { - err = tegra_powergate_power_off(TEGRA_POWERGATE_VDEC); - if (err) { - dev_err(dev, "Failed to power down HW: %d\n", err); - return err; - } - } - - clk_disable_unprepare(vde->clk); - reset_control_release(vde->rst); - reset_control_release(vde->rst_mc); - - return 0; -} - -static __maybe_unused int tegra_vde_runtime_resume(struct device *dev) -{ - struct tegra_vde *vde = dev_get_drvdata(dev); - int err; - - err = reset_control_acquire(vde->rst_mc); - if (err) { - dev_err(dev, "Failed to acquire mc reset: %d\n", err); - return err; - } - - err = reset_control_acquire(vde->rst); - if (err) { - dev_err(dev, "Failed to acquire reset: %d\n", err); - goto release_mc_reset; - } - - if (!dev->pm_domain) { - err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_VDEC, - vde->clk, vde->rst); - if (err) { - dev_err(dev, "Failed to power up HW : %d\n", err); - goto release_reset; - } - } else { - /* - * tegra_powergate_sequence_power_up() leaves clocks enabled, - * while GENPD not. - */ - err = clk_prepare_enable(vde->clk); - if (err) { - dev_err(dev, "Failed to enable clock: %d\n", err); - goto release_reset; - } - } - - return 0; - -release_reset: - reset_control_release(vde->rst); -release_mc_reset: - reset_control_release(vde->rst_mc); - - return err; -} - -static int tegra_vde_probe(struct platform_device *pdev) -{ - struct device *dev = &pdev->dev; - struct tegra_vde *vde; - int irq, err; - - vde = devm_kzalloc(dev, sizeof(*vde), GFP_KERNEL); - if (!vde) - return -ENOMEM; - - platform_set_drvdata(pdev, vde); - - vde->soc = of_device_get_match_data(&pdev->dev); - - vde->sxe = devm_platform_ioremap_resource_byname(pdev, "sxe"); - if (IS_ERR(vde->sxe)) - return PTR_ERR(vde->sxe); - - vde->bsev = devm_platform_ioremap_resource_byname(pdev, "bsev"); - if (IS_ERR(vde->bsev)) - return PTR_ERR(vde->bsev); - - vde->mbe = devm_platform_ioremap_resource_byname(pdev, "mbe"); - if (IS_ERR(vde->mbe)) - return PTR_ERR(vde->mbe); - - vde->ppe = devm_platform_ioremap_resource_byname(pdev, "ppe"); - if (IS_ERR(vde->ppe)) - return PTR_ERR(vde->ppe); - - vde->mce = devm_platform_ioremap_resource_byname(pdev, "mce"); - if (IS_ERR(vde->mce)) - return PTR_ERR(vde->mce); - - vde->tfe = devm_platform_ioremap_resource_byname(pdev, "tfe"); - if (IS_ERR(vde->tfe)) - return PTR_ERR(vde->tfe); - - vde->ppb = devm_platform_ioremap_resource_byname(pdev, "ppb"); - if (IS_ERR(vde->ppb)) - return PTR_ERR(vde->ppb); - - vde->vdma = devm_platform_ioremap_resource_byname(pdev, "vdma"); - if (IS_ERR(vde->vdma)) - return PTR_ERR(vde->vdma); - - vde->frameid = devm_platform_ioremap_resource_byname(pdev, "frameid"); - if (IS_ERR(vde->frameid)) - return PTR_ERR(vde->frameid); - - vde->clk = devm_clk_get(dev, NULL); - if (IS_ERR(vde->clk)) { - err = PTR_ERR(vde->clk); - dev_err(dev, "Could not get VDE clk %d\n", err); - return err; - } - - vde->rst = devm_reset_control_get_exclusive_released(dev, NULL); - if (IS_ERR(vde->rst)) { - err = PTR_ERR(vde->rst); - dev_err(dev, "Could not get VDE reset %d\n", err); - return err; - } - - vde->rst_mc = devm_reset_control_get_optional_exclusive_released(dev, "mc"); - if (IS_ERR(vde->rst_mc)) { - err = PTR_ERR(vde->rst_mc); - dev_err(dev, "Could not get MC reset %d\n", err); - return err; - } - - irq = platform_get_irq_byname(pdev, "sync-token"); - if (irq < 0) - return irq; - - err = devm_request_irq(dev, irq, tegra_vde_isr, 0, - dev_name(dev), vde); - if (err) { - dev_err(dev, "Could not request IRQ %d\n", err); - return err; - } - - err = devm_tegra_core_dev_init_opp_table_common(dev); - if (err) { - dev_err(dev, "Could initialize OPP table %d\n", err); - return err; - } - - vde->iram_pool = of_gen_pool_get(dev->of_node, "iram", 0); - if (!vde->iram_pool) { - dev_err(dev, "Could not get IRAM pool\n"); - return -EPROBE_DEFER; - } - - vde->iram = gen_pool_dma_alloc(vde->iram_pool, - gen_pool_size(vde->iram_pool), - &vde->iram_lists_addr); - if (!vde->iram) { - dev_err(dev, "Could not reserve IRAM\n"); - return -ENOMEM; - } - - INIT_LIST_HEAD(&vde->map_list); - mutex_init(&vde->map_lock); - mutex_init(&vde->lock); - init_completion(&vde->decode_completion); - - vde->miscdev.minor = MISC_DYNAMIC_MINOR; - vde->miscdev.name = "tegra_vde"; - vde->miscdev.fops = &tegra_vde_fops; - vde->miscdev.parent = dev; - - err = tegra_vde_iommu_init(vde); - if (err) { - dev_err(dev, "Failed to initialize IOMMU: %d\n", err); - goto err_gen_free; - } - - pm_runtime_enable(dev); - pm_runtime_use_autosuspend(dev); - pm_runtime_set_autosuspend_delay(dev, 300); - - /* - * VDE partition may be left ON after bootloader, hence let's - * power-cycle it in order to put hardware into a predictable lower - * power state. - */ - err = pm_runtime_resume_and_get(dev); - if (err) - goto err_pm_runtime; - - pm_runtime_put(dev); - - err = tegra_vde_alloc_bo(vde, &vde->secure_bo, DMA_FROM_DEVICE, 4096); - if (err) { - dev_err(dev, "Failed to allocate secure BO: %d\n", err); - goto err_pm_runtime; - } - - err = misc_register(&vde->miscdev); - if (err) { - dev_err(dev, "Failed to register misc device: %d\n", err); - goto err_free_secure_bo; - } - - return 0; - -err_free_secure_bo: - tegra_vde_free_bo(vde->secure_bo); -err_pm_runtime: - pm_runtime_dont_use_autosuspend(dev); - pm_runtime_disable(dev); - - tegra_vde_iommu_deinit(vde); - -err_gen_free: - gen_pool_free(vde->iram_pool, (unsigned long)vde->iram, - gen_pool_size(vde->iram_pool)); - - return err; -} - -static int tegra_vde_remove(struct platform_device *pdev) -{ - struct tegra_vde *vde = platform_get_drvdata(pdev); - struct device *dev = &pdev->dev; - - misc_deregister(&vde->miscdev); - - tegra_vde_free_bo(vde->secure_bo); - - /* - * As it increments RPM usage_count even on errors, we don't need to - * check the returned code here. - */ - pm_runtime_get_sync(dev); - - pm_runtime_dont_use_autosuspend(dev); - pm_runtime_disable(dev); - - /* - * Balance RPM state, the VDE power domain is left ON and hardware - * is clock-gated. It's safe to reboot machine now. - */ - pm_runtime_put_noidle(dev); - clk_disable_unprepare(vde->clk); - - tegra_vde_dmabuf_cache_unmap_all(vde); - tegra_vde_iommu_deinit(vde); - - gen_pool_free(vde->iram_pool, (unsigned long)vde->iram, - gen_pool_size(vde->iram_pool)); - - return 0; -} - -static void tegra_vde_shutdown(struct platform_device *pdev) -{ - /* - * On some devices bootloader isn't ready to a power-gated VDE on - * a warm-reboot, machine will hang in that case. - */ - pm_runtime_get_sync(&pdev->dev); -} - -static __maybe_unused int tegra_vde_pm_suspend(struct device *dev) -{ - struct tegra_vde *vde = dev_get_drvdata(dev); - int err; - - mutex_lock(&vde->lock); - - err = pm_runtime_force_suspend(dev); - if (err < 0) - return err; - - return 0; -} - -static __maybe_unused int tegra_vde_pm_resume(struct device *dev) -{ - struct tegra_vde *vde = dev_get_drvdata(dev); - int err; - - err = pm_runtime_force_resume(dev); - if (err < 0) - return err; - - mutex_unlock(&vde->lock); - - return 0; -} - -static const struct dev_pm_ops tegra_vde_pm_ops = { - SET_RUNTIME_PM_OPS(tegra_vde_runtime_suspend, - tegra_vde_runtime_resume, - NULL) - SET_SYSTEM_SLEEP_PM_OPS(tegra_vde_pm_suspend, - tegra_vde_pm_resume) -}; - -static const struct tegra_vde_soc tegra124_vde_soc = { - .supports_ref_pic_marking = true, -}; - -static const struct tegra_vde_soc tegra114_vde_soc = { - .supports_ref_pic_marking = true, -}; - -static const struct tegra_vde_soc tegra30_vde_soc = { - .supports_ref_pic_marking = false, -}; - -static const struct tegra_vde_soc tegra20_vde_soc = { - .supports_ref_pic_marking = false, -}; - -static const struct of_device_id tegra_vde_of_match[] = { - { .compatible = "nvidia,tegra124-vde", .data = &tegra124_vde_soc }, - { .compatible = "nvidia,tegra114-vde", .data = &tegra114_vde_soc }, - { .compatible = "nvidia,tegra30-vde", .data = &tegra30_vde_soc }, - { .compatible = "nvidia,tegra20-vde", .data = &tegra20_vde_soc }, - { }, -}; -MODULE_DEVICE_TABLE(of, tegra_vde_of_match); - -static struct platform_driver tegra_vde_driver = { - .probe = tegra_vde_probe, - .remove = tegra_vde_remove, - .shutdown = tegra_vde_shutdown, - .driver = { - .name = "tegra-vde", - .of_match_table = tegra_vde_of_match, - .pm = &tegra_vde_pm_ops, - }, -}; -module_platform_driver(tegra_vde_driver); - -MODULE_DESCRIPTION("NVIDIA Tegra Video Decoder driver"); -MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>"); -MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/tegra-vde/vde.h b/drivers/staging/media/tegra-vde/vde.h deleted file mode 100644 index bbd42b8d9991..000000000000 --- a/drivers/staging/media/tegra-vde/vde.h +++ /dev/null @@ -1,125 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * NVIDIA Tegra Video decoder driver - * - * Copyright (C) 2016-2019 GRATE-DRIVER project - */ - -#ifndef TEGRA_VDE_H -#define TEGRA_VDE_H - -#include <linux/completion.h> -#include <linux/dma-direction.h> -#include <linux/iova.h> -#include <linux/list.h> -#include <linux/miscdevice.h> -#include <linux/mutex.h> -#include <linux/types.h> - -struct clk; -struct dma_buf; -struct gen_pool; -struct iommu_group; -struct iommu_domain; -struct reset_control; -struct dma_buf_attachment; - -struct tegra_vde_soc { - bool supports_ref_pic_marking; -}; - -struct tegra_vde_bo { - struct iova *iova; - struct sg_table sgt; - struct tegra_vde *vde; - enum dma_data_direction dma_dir; - unsigned long dma_attrs; - dma_addr_t dma_handle; - dma_addr_t dma_addr; - void *dma_cookie; - size_t size; -}; - -struct tegra_vde { - void __iomem *sxe; - void __iomem *bsev; - void __iomem *mbe; - void __iomem *ppe; - void __iomem *mce; - void __iomem *tfe; - void __iomem *ppb; - void __iomem *vdma; - void __iomem *frameid; - struct mutex lock; - struct mutex map_lock; - struct list_head map_list; - struct miscdevice miscdev; - struct reset_control *rst; - struct reset_control *rst_mc; - struct gen_pool *iram_pool; - struct completion decode_completion; - struct clk *clk; - struct iommu_domain *domain; - struct iommu_group *group; - struct iova_domain iova; - struct iova *iova_resv_static_addresses; - struct iova *iova_resv_last_page; - const struct tegra_vde_soc *soc; - struct tegra_vde_bo *secure_bo; - dma_addr_t iram_lists_addr; - u32 *iram; -}; - -int tegra_vde_iommu_init(struct tegra_vde *vde); -void tegra_vde_iommu_deinit(struct tegra_vde *vde); -int tegra_vde_iommu_map(struct tegra_vde *vde, - struct sg_table *sgt, - struct iova **iovap, - size_t size); -void tegra_vde_iommu_unmap(struct tegra_vde *vde, struct iova *iova); - -int tegra_vde_dmabuf_cache_map(struct tegra_vde *vde, - struct dma_buf *dmabuf, - enum dma_data_direction dma_dir, - struct dma_buf_attachment **ap, - dma_addr_t *addrp); -void tegra_vde_dmabuf_cache_unmap(struct tegra_vde *vde, - struct dma_buf_attachment *a, - bool release); -void tegra_vde_dmabuf_cache_unmap_sync(struct tegra_vde *vde); -void tegra_vde_dmabuf_cache_unmap_all(struct tegra_vde *vde); - -static __maybe_unused char const * -tegra_vde_reg_base_name(struct tegra_vde *vde, void __iomem *base) -{ - if (vde->sxe == base) - return "SXE"; - - if (vde->bsev == base) - return "BSEV"; - - if (vde->mbe == base) - return "MBE"; - - if (vde->ppe == base) - return "PPE"; - - if (vde->mce == base) - return "MCE"; - - if (vde->tfe == base) - return "TFE"; - - if (vde->ppb == base) - return "PPB"; - - if (vde->vdma == base) - return "VDMA"; - - if (vde->frameid == base) - return "FRAMEID"; - - return "???"; -} - -#endif /* TEGRA_VDE_H */ diff --git a/include/uapi/linux/v4l2-controls.h b/include/uapi/linux/v4l2-controls.h index c8e0f84d204d..e3d48d571062 100644 --- a/include/uapi/linux/v4l2-controls.h +++ b/include/uapi/linux/v4l2-controls.h @@ -1563,6 +1563,8 @@ struct v4l2_h264_dpb_entry { #define V4L2_H264_DECODE_PARAM_FLAG_IDR_PIC 0x01 #define V4L2_H264_DECODE_PARAM_FLAG_FIELD_PIC 0x02 #define V4L2_H264_DECODE_PARAM_FLAG_BOTTOM_FIELD 0x04 +#define V4L2_H264_DECODE_PARAM_FLAG_PFRAME 0x08 +#define V4L2_H264_DECODE_PARAM_FLAG_BFRAME 0x10 #define V4L2_CID_STATELESS_H264_DECODE_PARAMS (V4L2_CID_CODEC_STATELESS_BASE + 7) /** |