diff options
Diffstat (limited to 'Documentation/devicetree/bindings/i2c')
14 files changed, 374 insertions, 178 deletions
diff --git a/Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml b/Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml new file mode 100644 index 000000000000..e58465d1b0c8 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/arm,i2c-versatile.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/arm,i2c-versatile.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: I2C Controller on ARM Ltd development platforms + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + const: arm,versatile-i2c + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +... + diff --git a/Documentation/devicetree/bindings/i2c/i2c-efm32.txt b/Documentation/devicetree/bindings/i2c/i2c-efm32.txt deleted file mode 100644 index 3b30e54ae3c7..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-efm32.txt +++ /dev/null @@ -1,33 +0,0 @@ -* Energymicro efm32 i2c controller - -Required properties : - - - reg : Offset and length of the register set for the device - - compatible : should be "energymicro,efm32-i2c" - - interrupts : the interrupt number - - clocks : reference to the module clock - -Recommended properties : - - - clock-frequency : maximal I2C bus clock frequency in Hz. - - energymicro,location : Decides the location of the USART I/O pins. - Allowed range : [0 .. 6] - -Example: - i2c0: i2c@4000a000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "energymicro,efm32-i2c"; - reg = <0x4000a000 0x400>; - interrupts = <9>; - clocks = <&cmu clk_HFPERCLKI2C0>; - clock-frequency = <100000>; - energymicro,location = <3>; - - eeprom@50 { - compatible = "microchip,24c02"; - reg = <0x50>; - pagesize = <16>; - }; - }; - diff --git a/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt b/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt deleted file mode 100644 index 72065b0ff680..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-nomadik.txt +++ /dev/null @@ -1,23 +0,0 @@ -I2C for Nomadik based systems - -Required (non-standard) properties: - - Nil - -Recommended (non-standard) properties: - - clock-frequency : Maximum bus clock frequency for the device - -Optional (non-standard) properties: - - Nil - -Example : - -i2c@80004000 { - compatible = "stericsson,db8500-i2c", "st,nomadik-i2c"; - reg = <0x80004000 0x1000>; - interrupts = <0 21 0x4>; - #address-cells = <1>; - #size-cells = <0>; - v-i2c-supply = <&db8500_vape_reg>; - - clock-frequency = <400000>; -}; diff --git a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt b/Documentation/devicetree/bindings/i2c/i2c-ocores.txt deleted file mode 100644 index a37c9455b244..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-ocores.txt +++ /dev/null @@ -1,78 +0,0 @@ -Device tree configuration for i2c-ocores - -Required properties: -- compatible : "opencores,i2c-ocores" - "aeroflexgaisler,i2cmst" - "sifive,fu540-c000-i2c", "sifive,i2c0" - For Opencore based I2C IP block reimplemented in - FU540-C000 SoC. - "sifive,fu740-c000-i2c", "sifive,i2c0" - For Opencore based I2C IP block reimplemented in - FU740-C000 SoC. - Please refer to sifive-blocks-ip-versioning.txt for - additional details. -- reg : bus address start and address range size of device -- clocks : handle to the controller clock; see the note below. - Mutually exclusive with opencores,ip-clock-frequency -- opencores,ip-clock-frequency: frequency of the controller clock in Hz; - see the note below. Mutually exclusive with clocks -- #address-cells : should be <1> -- #size-cells : should be <0> - -Optional properties: -- interrupts : interrupt number. -- clock-frequency : frequency of bus clock in Hz; see the note below. - Defaults to 100 KHz when the property is not specified -- reg-shift : device register offsets are shifted by this value -- reg-io-width : io register width in bytes (1, 2 or 4) -- regstep : deprecated, use reg-shift above - -Note -clock-frequency property is meant to control the bus frequency for i2c bus -drivers, but it was incorrectly used to specify i2c controller input clock -frequency. So the following rules are set to fix this situation: -- if clock-frequency is present and neither opencores,ip-clock-frequency nor - clocks are, then clock-frequency specifies i2c controller clock frequency. - This is to keep backwards compatibility with setups using old DTB. i2c bus - frequency is fixed at 100 KHz. -- if clocks is present it specifies i2c controller clock. clock-frequency - property specifies i2c bus frequency. -- if opencores,ip-clock-frequency is present it specifies i2c controller - clock frequency. clock-frequency property specifies i2c bus frequency. - -Examples: - - i2c0: ocores@a0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "opencores,i2c-ocores"; - reg = <0xa0000000 0x8>; - interrupts = <10>; - opencores,ip-clock-frequency = <20000000>; - - reg-shift = <0>; /* 8 bit registers */ - reg-io-width = <1>; /* 8 bit read/write */ - - dummy@60 { - compatible = "dummy"; - reg = <0x60>; - }; - }; -or - i2c0: ocores@a0000000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "opencores,i2c-ocores"; - reg = <0xa0000000 0x8>; - interrupts = <10>; - clocks = <&osc>; - clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ - - reg-shift = <0>; /* 8 bit registers */ - reg-io-width = <1>; /* 8 bit read/write */ - - dummy@60 { - compatible = "dummy"; - reg = <0x60>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt index 924ad8c03464..166865e48849 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt +++ b/Documentation/devicetree/bindings/i2c/i2c-qcom-cci.txt @@ -7,6 +7,7 @@ PROPERTIES: Value type: <string> Definition: must be one of: "qcom,msm8916-cci" + "qcom,msm8974-cci" "qcom,msm8996-cci" "qcom,sdm845-cci" "qcom,sm8250-cci" @@ -43,9 +44,9 @@ PROPERTIES: SUBNODES: -The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996, -sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0" and -"i2c-bus@1". +The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8974, +msm8996, sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0" +and "i2c-bus@1". PROPERTIES: diff --git a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml index 5339dd4fc370..ee9f8b91d2e2 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml @@ -37,6 +37,8 @@ properties: - rockchip,rk3308-i2c - rockchip,rk3328-i2c - rockchip,rk3568-i2c + - rockchip,rk3588-i2c + - rockchip,rv1126-i2c - const: rockchip,rk3399-i2c reg: diff --git a/Documentation/devicetree/bindings/i2c/i2c-versatile.txt b/Documentation/devicetree/bindings/i2c/i2c-versatile.txt deleted file mode 100644 index 361d31c51b6f..000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-versatile.txt +++ /dev/null @@ -1,10 +0,0 @@ -i2c Controller on ARM Versatile platform: - -Required properties: -- compatible : Must be "arm,versatile-i2c"; -- reg -- #address-cells = <1>; -- #size-cells = <0>; - -Optional properties: -- Child nodes conforming to i2c bus binding diff --git a/Documentation/devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt b/Documentation/devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt deleted file mode 100644 index 5dc5d2e2573d..000000000000 --- a/Documentation/devicetree/bindings/i2c/ibm,p8-occ-hwmon.txt +++ /dev/null @@ -1,25 +0,0 @@ -Device-tree bindings for I2C-based On-Chip Controller hwmon device ------------------------------------------------------------------- - -Required properties: - - compatible = "ibm,p8-occ-hwmon"; - - reg = <I2C address>; : I2C bus address - -Examples: - - i2c-bus@100 { - #address-cells = <1>; - #size-cells = <0>; - clock-frequency = <100000>; - < more properties > - - occ-hwmon@1 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x50>; - }; - - occ-hwmon@2 { - compatible = "ibm,p8-occ-hwmon"; - reg = <0x51>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml index f771c09aabfc..0ec033e48830 100644 --- a/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/marvell,mv64xxx-i2c.yaml @@ -21,10 +21,18 @@ properties: - enum: - allwinner,sun8i-a23-i2c - allwinner,sun8i-a83t-i2c + - allwinner,sun8i-v536-i2c - allwinner,sun50i-a64-i2c - - allwinner,sun50i-a100-i2c - allwinner,sun50i-h6-i2c + - const: allwinner,sun6i-a31-i2c + - description: Allwinner SoCs with offload support + items: + - enum: + - allwinner,sun20i-d1-i2c + - allwinner,sun50i-a100-i2c - allwinner,sun50i-h616-i2c + - allwinner,sun50i-r329-i2c + - const: allwinner,sun8i-v536-i2c - const: allwinner,sun6i-a31-i2c - const: marvell,mv64xxx-i2c - const: marvell,mv78230-i2c diff --git a/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml b/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml index 128444942aec..09d2591e1fa3 100644 --- a/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nuvoton,npcm7xx-i2c.yaml @@ -7,17 +7,18 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: nuvoton NPCM7XX I2C Controller Device Tree Bindings description: | - The NPCM750x includes sixteen I2C bus controllers. All Controllers support - both master and slave mode. Each controller can switch between master and slave - at run time (i.e. IPMB mode). Each controller has two 16 byte HW FIFO for TX and - RX. + I2C bus controllers of the NPCM series support both master and + slave mode. Each controller can switch between master and slave at run time + (i.e. IPMB mode). HW FIFO for TX and RX are supported. maintainers: - Tali Perry <tali.perry1@gmail.com> properties: compatible: - const: nuvoton,npcm750-i2c + enum: + - nuvoton,npcm750-i2c + - nuvoton,npcm845-i2c reg: maxItems: 1 @@ -36,6 +37,10 @@ properties: default: 100000 enum: [100000, 400000, 1000000] + nuvoton,sys-mgr: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of system manager register node. + required: - compatible - reg @@ -44,6 +49,15 @@ required: allOf: - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + contains: + const: nuvoton,npcm845-i2c + + then: + required: + - nuvoton,sys-mgr unevaluatedProperties: false @@ -57,6 +71,7 @@ examples: clock-frequency = <100000>; interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; compatible = "nuvoton,npcm750-i2c"; + nuvoton,sys-mgr = <&gcr>; }; ... diff --git a/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml b/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml new file mode 100644 index 000000000000..85d9efb743ee --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenCores I2C controller + +maintainers: + - Peter Korsgaard <peter@korsgaard.com> + - Andrew Lunn <andrew@lunn.ch> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC + - sifive,fu540-c000-i2c # Opencore based IP block FU540-C000 SoC + - const: sifive,i2c0 + - enum: + - opencores,i2c-ocores + - aeroflexgaisler,i2cmst + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: | + clock-frequency property is meant to control the bus frequency for i2c bus + drivers, but it was incorrectly used to specify i2c controller input clock + frequency. So the following rules are set to fix this situation: + - if clock-frequency is present and neither opencores,ip-clock-frequency nor + clocks are, then clock-frequency specifies i2c controller clock frequency. + This is to keep backwards compatibility with setups using old DTB. i2c bus + frequency is fixed at 100 KHz. + - if clocks is present it specifies i2c controller clock. clock-frequency + property specifies i2c bus frequency. + - if opencores,ip-clock-frequency is present it specifies i2c controller + clock frequency. clock-frequency property specifies i2c bus frequency. + default: 100000 + + reg-io-width: + description: | + io register width in bytes + enum: [1, 2, 4] + + reg-shift: + description: | + device register offsets are shifted by this value + default: 0 + + regstep: + description: | + deprecated, use reg-shift above + deprecated: true + + opencores,ip-clock-frequency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Frequency of the controller clock in Hz. Mutually exclusive with clocks. + See the note above. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + +oneOf: + - required: + - opencores,ip-clock-frequency + - required: + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c@a0000000 { + compatible = "opencores,i2c-ocores"; + reg = <0xa0000000 0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <10>; + opencores,ip-clock-frequency = <20000000>; + + reg-shift = <0>; /* 8 bit registers */ + reg-io-width = <1>; /* 8 bit read/write */ + }; + + i2c@b0000000 { + compatible = "opencores,i2c-ocores"; + reg = <0xa0000000 0x8>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <10>; + clocks = <&osc>; + clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ + + reg-shift = <0>; /* 8 bit registers */ + reg-io-width = <1>; /* 8 bit read/write */ + }; +... diff --git a/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml b/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml new file mode 100644 index 000000000000..c46378efc123 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/renesas,rzv2m.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M I2C Bus Interface + +maintainers: + - Phil Edworthy <phil.edworthy@renesas.com> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +properties: + compatible: + items: + - enum: + - renesas,i2c-r9a09g011 # RZ/V2M + - const: renesas,rzv2m-i2c + + reg: + maxItems: 1 + + interrupts: + items: + - description: Data transmission/reception interrupt + - description: Status interrupt + + interrupt-names: + items: + - const: tia + - const: tis + + clock-frequency: + default: 100000 + enum: [ 100000, 400000 ] + description: + Desired I2C bus clock frequency in Hz. + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - power-domains + - resets + - '#address-cells' + - '#size-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a09g011-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + i2c0: i2c@a4030000 { + compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; + reg = <0xa4030000 0x80>; + interrupts = <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "tia", "tis"; + clocks = <&cpg CPG_MOD R9A09G011_IIC_PCLK0>; + resets = <&cpg R9A09G011_IIC_GPA_PRESETN>; + power-domains = <&cpg>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml new file mode 100644 index 000000000000..42c5974ec7b0 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/st,nomadik-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST Microelectronics Nomadik I2C Bindings + +description: The Nomadik I2C host controller began its life in the ST + Microelectronics STn8800 SoC, and was then inherited into STn8810 and + STn8815. It was part of the prototype STn8500 which then became ST-Ericsson + DB8500 after the merge of these two companies wireless divisions. + +maintainers: + - Linus Walleij <linus.walleij@linaro.org> + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - st,nomadik-i2c + required: + - compatible + +properties: + compatible: + oneOf: + # The variant found in STn8815 + - items: + - const: st,nomadik-i2c + - const: arm,primecell + # The variant found in DB8500 + - items: + - const: stericsson,db8500-i2c + - const: st,nomadik-i2c + - const: arm,primecell + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + oneOf: + # Clock name in STn8815 + - items: + - const: mclk + - const: apb_pclk + # Clock name in DB8500 + - items: + - const: i2cclk + - const: apb_pclk + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + clock-frequency: + minimum: 1 + maximum: 400000 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h> + #include <dt-bindings/arm/ux500_pm_domains.h> + i2c@80004000 { + compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell"; + reg = <0x80004000 0x1000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + clock-frequency = <400000>; + clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>; + clock-names = "i2cclk", "apb_pclk"; + power-domains = <&pm_domains DOMAIN_VAPE>; + resets = <&prcc_reset DB8500_PRCC_3 DB8500_PRCC_3_RESET_I2C0>; + }; + + i2c@101f8000 { + compatible = "st,nomadik-i2c", "arm,primecell"; + reg = <0x101f8000 0x1000>; + interrupt-parent = <&vica>; + interrupts = <20>; + clock-frequency = <100000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&i2c0clk>, <&pclki2c0>; + clock-names = "mclk", "apb_pclk"; + }; + +... diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index dccbb18b6dc0..a41588763786 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -17,6 +17,7 @@ allOf: contains: enum: - st,stm32f7-i2c + - st,stm32mp13-i2c - st,stm32mp15-i2c then: properties: @@ -45,6 +46,7 @@ properties: enum: - st,stm32f4-i2c - st,stm32f7-i2c + - st,stm32mp13-i2c - st,stm32mp15-i2c reg: |