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* Merge branch 'imx/soc' into imx/dtShawn Guo2015-01-1314-20/+193
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| * ARM: imx: clk-vf610: Add clock for SNVSSanchayan Maity2015-01-132-1/+4
| | | | | | | | | | | | | | Add support for clock gating of the SNVS peripheral. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: clk-vf610: Add clock for UART4 and UART5Bhuvanchandra DV2015-01-131-0/+2
| | | | | | | | | | | | | | | | | | Add support for clock gating of UART4 and UART5. We use these UART's in a (not yet mainlined) device tree. Signed-off-by: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: drop CPUIDLE_FLAG_TIME_VALID from cpuidle-imx6sxShawn Guo2015-01-061-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As the result of commit b82b6cca4880 ("cpuidle: Invert CPUIDLE_FLAG_TIME_VALID logic"), the flag gets removed and hence we see the compile error below. CC arch/arm/mach-imx/cpuidle-imx6sx.o arch/arm/mach-imx/cpuidle-imx6sx.c:69:13: error: ‘CPUIDLE_FLAG_TIME_VALID’ undeclared here (not in a function) Since the behavior of the original flag has been the default, we can simply drop the flag now. Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: support arm power off in cpuidle for i.mx6sxAnson Huang2015-01-057-8/+144
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces an independent cpuidle driver for i.MX6SX, and supports arm power off in idle, totally 3 levels of cpuidle are supported as below: 1. ARM WFI; 2. SOC in WAIT mode; 3. SOC in WAIT mode + ARM power off. ARM power off can save at least 5mW power. This patch also replaces imx6q_enable_rbc with imx6_enable_rbc. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: remove unnecessary setting for DSMAnson Huang2015-01-051-1/+0
| | | | | | | | | | | | | | | | | | | | Now we support DSM in OCRAM for all i.MX6 SoCs, the resume entry point is set in asm code of suspend-imx6.S, so no need to set the resume entry point for SRC in pre-suspend flow. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: correct the hardware clock gate setting for shared nodesAnson Huang2015-01-051-4/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For those clk gates which hold share count, since its is_enabled callback is only checking the share count rather than reading the hardware register setting, in the late phase of kernel bootup, the clk_disable_unused action will NOT handle the scenario of share_count is 0 but the hardware setting is enabled, actually, U-Boot normally enables all clk gates, then those shared clk gates will be always enabled until they are used by some modules. So the problem would be: when kernel boot up, the usecount cat from clk tree is 0, but the clk gates actually is enabled in hardware register, it will confuse user and bring unnecessary power consumption. This patch adds .disable_unused callback and using hardware register check for .is_enabled callback of shared nodes to handle such scenario in late phase of kernel boot up, then the hardware status will match the clk tree info. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM: imx: pllv3: add shift for frequency multiplierStefan Agner2015-01-053-5/+10
| | | | | | | | | | | | | | | | | | | | | | Add shift capabilties for the frequency multiplier (DIV_SELECT) to support Vybrid's USB PLL oddity. The PLL3 and PLL7 are the only PLL control registers which have the DIV_SELECT bit shifted by one. Be aware, there are known documentation errors in the reference manual too. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
| * ARM vf610: add compatibilty strings of supported Vybrid SoC'sStefan Agner2015-01-052-1/+16
| | | | | | | | | | | | | | | | | | | | The Vybrid SoC family (in the kernel known as vf610) is a familiy of multiple similar SoC's. The VF5xx series comes without secondary Cortex-M4 core, while the second number VFx1x indicates the presence of a L2 cache controller. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: imx6dl-udoo: Add board support based off imx6q-udooRobert Nelson2015-01-064-123/+154
| | | | | | | | | | | | | | | | | | For more information about the Udoo boards: http://www.udoo.org/ Signed-off-by: Robert Nelson <robertcnelson@gmail.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: imx6sx: add i.mx6sx sabreauto board supportAnson Huang2015-01-052-0/+147
| | | | | | | | | | | | | | | | Add basic i.MX6SoloX Sabre Auto board support, currently only debug UART and uSDHC are supported on this board. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: imx6sx-sdb: Add QSPI supportFabio Estevam2015-01-051-0/+39
| | | | | | | | | | | | | | imx6sx-sdb has two s25fl128s quad spi flash. Add support for them. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: imx6qdl: Remove OCRAM clock from VPU nodeFabio Estevam2015-01-051-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | According to Documentation/devicetree/bindings/media/coda.txt: - clock-names : Should be "ahb", "per" The OCRAM clock is already provided inside the ocram node, so remove the OCRAM clock from the VPU node. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: imx: apf51dev: add gpio-backlight supportGwenhael Goavec-Merou2015-01-051-0/+14
| | | | | | | | | | Signed-off-by: Gwenhael Goavec-Merou <gwenhael.goavec-merou@armadeus.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: i.MX53: dts: add sahara moduleSteffen Trumtrar2015-01-051-0/+9
| | | | | | | | | | | | | | The i.MX53 has a SAHARA v4 core. Add it to the dtsi. Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: imx6dl: correct cpufreq volt/freq tableAnson Huang2015-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently the cpufreq volt/freq table we used is for LDO enable mode, according to latest datasheet Rev. 3, 03/2014, the volt/freq table is as below: LDO enabled(min value): 996MHz: VDDARM: 1.225V, VDDSOC: 1.150V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 1.050V, VDDSOC: 1.150V; LDO bypassed(min value): 996MHz: VDDARM: 1.250V, VDDSOC: 1.150V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 1.050V, VDDSOC: 1.150V; Adding 25mV to cover board IR drop, for LDO enabled mode of 996MHz, VDDARM should be 1.250V, so this patch updates it. Signed-off-by: Anson Huang <b20788@freescale.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: imx6q: update cpufreq volt/freq tableAnson Huang2015-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to latest i.MX6Q datasheet Rev. 3, 02/2014, the latest cpufreq volt/freq table is as below: LDO enabled/bypassed(min value): 996MHz: VDDARM: 1.225V, VDDSOC: 1.150V; 792MHz: VDDARM: 1.150V, VDDSOC: 1.150V; 396MHz: VDDARM: 0.925V, VDDSOC: 1.150V; the 792MHz setpoint's VDDARM min voltage is updated from 1.125V to 1.150V, adding 25mV to cover board IR drop, 1.175V is the right voltage we should use. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: sabrelite: add i2c3Eric Nelson2015-01-051-0/+14
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: sabrelite: add hdmiEric Nelson2015-01-051-0/+5
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: sabrelite: add i2c2Eric Nelson2015-01-051-0/+14
| | | | | | | | | | Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: vf610: add system reset controller and syscon-rebootStefan Agner2015-01-052-0/+16
| | | | | | | | | | | | | | | | | | Add the system reset controller (SRC) module and use syscon-reboot to register a restart handler which restarts the SoC using the SRC SW_RST bit. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: imx: Update VPU compatible stringsFabio Estevam2015-01-052-2/+2
| | | | | | | | | | | | | | | | Update the VPU compatible strings to also use "cnm,coda<model>". Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: vf-colibri: add CLKOUT pin to pinctrl of FEC1Stefan Agner2015-01-051-0/+1
| | | | | | | | | | | | | | | | | | | | On the Colibri module, the RMII clock for the Ethernet PHY is generated by the SoC. This patch adds that missing pin to the pinctrl of FEC1. Because the boot loader initializes this pin, ethernet worked even without this pin so far. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | ARM: dts: vf610: enable watchdog for Cortex-A5 dt'sStefan Agner2015-01-052-1/+6
| | | | | | | | | | | | | | | | | | | | During restructuring of the device tree files the watchdog was changed to be disabled by default. However, since the watchdog instance is dedicated to the Cortex-A5, enable the peripheral by default in the base device tree vf500.dtsi. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* | apf27dev: add max5821 to the dtsPhilippe Reynes2015-01-051-0/+21
|/ | | | | Signed-off-by: Philippe Reynes <tremyfr@gmail.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
* Linux 3.19-rc1v3.19-rc1Linus Torvalds2014-12-211-2/+2
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* Merge tag 'for-linus' of ↵Linus Torvalds2014-12-2110-25/+103
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linux Pull ACCESS_ONCE cleanup preparation from Christian Borntraeger: "kernel: Provide READ_ONCE and ASSIGN_ONCE As discussed on LKML http://marc.info/?i=54611D86.4040306%40de.ibm.com ACCESS_ONCE might fail with specific compilers for non-scalar accesses. Here is a set of patches to tackle that problem. The first patch introduce READ_ONCE and ASSIGN_ONCE. If the data structure is larger than the machine word size memcpy is used and a warning is emitted. The next patches fix up several in-tree users of ACCESS_ONCE on non-scalar types. This does not yet contain a patch that forces ACCESS_ONCE to work only on scalar types. This is targetted for the next merge window as Linux next already contains new offenders regarding ACCESS_ONCE vs. non-scalar types" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/borntraeger/linux: s390/kvm: REPLACE barrier fixup with READ_ONCE arm/spinlock: Replace ACCESS_ONCE with READ_ONCE arm64/spinlock: Replace ACCESS_ONCE READ_ONCE mips/gup: Replace ACCESS_ONCE with READ_ONCE x86/gup: Replace ACCESS_ONCE with READ_ONCE x86/spinlock: Replace ACCESS_ONCE with READ_ONCE mm: replace ACCESS_ONCE with READ_ONCE or barriers kernel: Provide READ_ONCE and ASSIGN_ONCE
| * s390/kvm: REPLACE barrier fixup with READ_ONCEChristian Borntraeger2014-12-181-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Commit 1365039d0cb3 ("KVM: s390: Fix ipte locking") replace ACCESS_ONCE with barriers. Lets use READ_ONCE instead. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * arm/spinlock: Replace ACCESS_ONCE with READ_ONCEChristian Borntraeger2014-12-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Change the spinlock code to replace ACCESS_ONCE with READ_ONCE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * arm64/spinlock: Replace ACCESS_ONCE READ_ONCEChristian Borntraeger2014-12-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Change the spinlock code to replace ACCESS_ONCE with READ_ONCE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * mips/gup: Replace ACCESS_ONCE with READ_ONCEChristian Borntraeger2014-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Change the gup code to replace ACCESS_ONCE with READ_ONCE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * x86/gup: Replace ACCESS_ONCE with READ_ONCEChristian Borntraeger2014-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Change the gup code to replace ACCESS_ONCE with READ_ONCE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * x86/spinlock: Replace ACCESS_ONCE with READ_ONCEChristian Borntraeger2014-12-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Change the spinlock code to replace ACCESS_ONCE with READ_ONCE. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * mm: replace ACCESS_ONCE with READ_ONCE or barriersChristian Borntraeger2014-12-183-3/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Let's change the code to access the page table elements with READ_ONCE that does implicit scalar accesses for the gup code. mm_find_pmd is tricky, because m68k and sparc(32bit) define pmd_t as array of longs. This code requires just that the pmd_present and pmd_trans_huge check are done on the same value, so a barrier is sufficent. A similar case is in handle_pte_fault. On ppc44x the word size is 32 bit, but a pte is 64 bit. A barrier is ok as well. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Cc: linux-mm@kvack.org Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
| * kernel: Provide READ_ONCE and ASSIGN_ONCEChristian Borntraeger2014-12-181-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ACCESS_ONCE does not work reliably on non-scalar types. For example gcc 4.6 and 4.7 might remove the volatile tag for such accesses during the SRA (scalar replacement of aggregates) step https://gcc.gnu.org/bugzilla/show_bug.cgi?id=58145) Let's provide READ_ONCE/ASSIGN_ONCE that will do all accesses via scalar types as suggested by Linus Torvalds. Accesses larger than the machines word size cannot be guaranteed to be atomic. These macros will use memcpy and emit a build warning. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
* | Merge tag 'clk-for-linus-3.19' of ↵Linus Torvalds2014-12-2194-690/+6663
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clk framework updates from Mike Turquette: "This is much later than usual due to several last minute bugs that had to be addressed. As usual the majority of changes are new drivers and modifications to existing drivers. The core recieved many fixes along with the groundwork for several large changes coming in the future which will better parition clock providers from clock consumers" * tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits) clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated ARM: OMAP3: clock: fix boot breakage in legacy mode ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs clk: Really fix deadlock with mmap_sem clk: mmp: fix sparse non static symbol warning clk: Change clk_ops->determine_rate to return a clk_hw as the best parent clk: change clk_debugfs_add_file to take a struct clk_hw clk: Don't expose __clk_get_accuracy clk: Don't try to use a struct clk* after it could have been freed clk: Remove unused function __clk_get_prepare_count clk: samsung: Fix double add of syscore ops after driver rebind clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi clk: samsung: exynos4415: Fix build with PM_SLEEP disabled clk: samsung: remove unnecessary inclusion of header files from clk.h clk: samsung: remove unnecessary CONFIG_OF from clk.c clk: samsung: Spelling s/bwtween/between/ clk: rockchip: Add support for the mmc clock phases using the framework clk: rockchip: add bindings for the mmc clocks clk: rockchip: rk3288 export i2s0_clkout for use in DT clk: rockchip: use clock ID for DMC (memory controller) on rk3288 ...
| * | clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to ↵Krzysztof Kozlowski2014-12-171-1/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | domain being gated Audio subsystem clocks are located in separate block. On Exynos 5420 if clock for this block (from main clock domain) 'mau_epll' is gated then any read or write to audss registers will block. This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit after introducing runtime PM to pl330 DMA driver. After that commit the 'mau_epll' was gated, because the "amba" clock was disabled and there were no more users of mau_epll. The system hang on one of steps: 1. Disabling unused clocks from audss block. 2. During audss GPIO setup (just before probing i2s0 because samsung_pinmux_setup() tried to access memory from audss block which was gated. Add a workaround for this by enabling the 'mau_epll' clock in probe. Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | ARM: OMAP3: clock: fix boot breakage in legacy modeTero Kristo2014-12-161-9/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new usage of determine_rate and set_rate_and_parent calls for OMAP DPLLs assumes the DPLLs must have two parents defined, even if it is the same clock. Legacy clock data did not fullfill this requirement and caused a boot crash. Fixed by adding the missing parent information to the DPLL clocks. Signed-off-by: Tero Kristo <t-kristo@ti.com> Fixes: 2e1a7b014f ("ARM: OMAP3+: DPLL: use determine_rate() and...") Cc: Paul Walmsley <paul@pwsan.com> Acked-by: Tony Lindgren <tony@atomide.com> Tested-by: Kevin Hilman <khilman@linaro.org> Reported-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIsTero Kristo2014-12-163-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While the change for determine_rate clock operation was merged, the OMAP counterpart using these calls was overlooked for some reason, and caused boot failures on at least OMAP4 platforms. Fixed by updating the DPLL API calls to use the new parameters. Signed-off-by: Tero Kristo <t-kristo@ti.com> Fixes: 646cafc6aa ("clk: Change clk_ops->determine_rate") Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com> Acked-by: Tony Lindgren <tony@atomide.com> Acked-by: Paul Walmsley <paul@pwsan.com> Tested-by: Kevin Hilman <khilman@linaro.org> Reported-by: Kevin Hilman <khilman@linaro.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | Merge tag 'for-v3.19/omap-a' of ↵Michael Turquette2014-12-169-63/+238
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into tmp Some OMAP clock/hwmod patches for v3.19. Most of the patches are clock-related. The DPLL implementation is changed to better align to the common clock framework. There is also a patch that removes a few lines from the hwmod code - this patch should have no functional effect. Basic build, boot, and PM test logs for these patches can be found here: http://www.pwsan.com/omap/testlogs/omap-a-for-v3.19/20141113094101/
| * | | clk: Really fix deadlock with mmap_semStephen Boyd2014-12-161-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6314b6796e3c (clk: Don't hold prepare_lock across debugfs creation, 2014-09-04) forgot to update one place where we hold the prepare_lock while creating debugfs directories. This means we still have the chance of a deadlock that the commit was trying to fix. Actually fix it by moving the debugfs creation outside the prepare_lock. Cc: <stable@vger.kernel.org> # 3.18 Reported-by: Russell King <rmk+kernel@arm.linux.org.uk> Fixes: 6314b6796e3c "clk: Don't hold prepare_lock across debugfs creation" Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Michael Turquette <mturquette@linaro.org> [mturquette@linaro.org: removed lockdep_assert]
| * | | Merge tag 'for-v3.19-exynos-clk-2' of git://linuxtv.org/snawrocki/samsung ↵Michael Turquette2014-12-115-10/+12
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into clk-next - exynos4415 and exynos audio subsystem clk driver (build with PM_SLEEP disabled, resource release) fixes - minor cleanups in drivers/clk/samsung/clk.c (spelling, includes) - modification of the exynos4 HDMI PHY clock definition to model dependency of "sclk_hdmiphy" on the "hdmi" clock
| | * | | clk: samsung: Fix double add of syscore ops after driver rebindKrzysztof Kozlowski2014-12-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During driver unbind the syscore ops were not unregistered which lead to double add on syscore list: $ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/unbind $ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/bind [ 1463.044061] ------------[ cut here ]------------ [ 1463.047255] WARNING: CPU: 0 PID: 1 at lib/list_debug.c:36 __list_add+0x8c/0xc0() [ 1463.054613] list_add double add: new=c06e52c0, prev=c06e52c0, next=c06d5f84. [ 1463.061625] Modules linked in: [ 1463.064623] CPU: 0 PID: 1 Comm: bash Tainted: G W 3.18.0-rc5-next-20141121-00005-ga8fab06eab42-dirty #1022 [ 1463.075338] [<c0014e2c>] (unwind_backtrace) from [<c0011d80>] (show_stack+0x10/0x14) [ 1463.083046] [<c0011d80>] (show_stack) from [<c048bb70>] (dump_stack+0x70/0xbc) [ 1463.090236] [<c048bb70>] (dump_stack) from [<c00233d4>] (warn_slowpath_common+0x74/0xb0) [ 1463.098295] [<c00233d4>] (warn_slowpath_common) from [<c00234a4>] (warn_slowpath_fmt+0x30/0x40) [ 1463.106962] [<c00234a4>] (warn_slowpath_fmt) from [<c020fe80>] (__list_add+0x8c/0xc0) [ 1463.114760] [<c020fe80>] (__list_add) from [<c0282094>] (register_syscore_ops+0x30/0x3c) [ 1463.122819] [<c0282094>] (register_syscore_ops) from [<c0392f20>] (exynos_audss_clk_probe+0x36c/0x460) [ 1463.132091] [<c0392f20>] (exynos_audss_clk_probe) from [<c0283084>] (platform_drv_probe+0x48/0xa4) [ 1463.141013] [<c0283084>] (platform_drv_probe) from [<c0281a14>] (driver_probe_device+0x13c/0x37c) [ 1463.149852] [<c0281a14>] (driver_probe_device) from [<c0280560>] (bind_store+0x90/0xe0) [ 1463.157822] [<c0280560>] (bind_store) from [<c027fd10>] (drv_attr_store+0x20/0x2c) [ 1463.165363] [<c027fd10>] (drv_attr_store) from [<c0143898>] (sysfs_kf_write+0x4c/0x50) [ 1463.173252] [<c0143898>] (sysfs_kf_write) from [<c0142c80>] (kernfs_fop_write+0xbc/0x198) [ 1463.181395] [<c0142c80>] (kernfs_fop_write) from [<c00e2be0>] (vfs_write+0xa0/0x1a8) [ 1463.189104] [<c00e2be0>] (vfs_write) from [<c00e2f00>] (SyS_write+0x40/0x8c) [ 1463.196122] [<c00e2f00>] (SyS_write) from [<c000f2a0>] (ret_fast_syscall+0x0/0x48) [ 1463.203655] ---[ end trace 08f6710c9bc8d8f3 ]--- [ 1463.208244] exynos-audss-clk 3810000.audss-clock-controller: setup completed Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Fixes: 1241ef94ccc3 ("clk: samsung: register audio subsystem clocks using common clock framework") Cc: <stable@vger.kernel.org> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | | clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmiAndrzej Hajda2014-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock. The patch models this dependency using parent/child hirerarchy. The patch fixes issue with system hangs during mixer device access, mixer uses sclk_hdmiphy descendant clock. Signed-off-by: Andrzej Hajda <a.hajda@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | | clk: samsung: exynos4415: Fix build with PM_SLEEP disabledKrzysztof Kozlowski2014-12-021-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following build errors when PM_SLEEP is disabled (e.g. by disabling SUSPEND and HIBERNATION): drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_init’: drivers/clk/samsung/clk-exynos4415.c:982:2: error: ‘exynos4415_ctx’ undeclared (first use in this function) drivers/clk/samsung/clk-exynos4415.c:982:2: note: each undeclared identifier is reported only once for each function it appears in drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_dmc_init’: drivers/clk/samsung/clk-exynos4415.c:1123:2: error: ‘exynos4415_dmc_ctx’ undeclared (first use in this function) make[3]: *** [drivers/clk/samsung/clk-exynos4415.o] Error 1 Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | | clk: samsung: remove unnecessary inclusion of header files from clk.hPankaj Dubey2014-12-022-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let's remove unnecessary include of header files from clk.h and add required one in clk.c Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> [s.nawrocki@samsung.com: dropped removal of '#include <linux/syscore_ops.h>'] Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | | clk: samsung: remove unnecessary CONFIG_OF from clk.cPankaj Dubey2014-12-021-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unnecessary CONFIG_OF from samsung/clk.c. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| | * | | clk: samsung: Spelling s/bwtween/between/Pankaj Dubey2014-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a typo in comment section of "struct samsung_clk_provider". Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
| * | | | clk: mmp: fix sparse non static symbol warningWei Yongjun2014-12-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes the following sparse warnings: drivers/clk/mmp/clk-frac.c:113:6: warning: symbol 'clk_factor_init' was not declared. Should it be static? Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Michael Turquette <mturquette@linaro.org>
| * | | | clk: Change clk_ops->determine_rate to return a clk_hw as the best parentTomeu Vizoso2014-12-0414-49/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is in preparation for clock providers to not have to deal with struct clk. Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com> Reviewed-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Michael Turquette <mturquette@linaro.org>
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