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2013-01-26drm/i915: SWF screatch registers need an offset on VLVVille Syrjälä1-13/+13
2013-01-26drm/i915: Include display_mmio_offset in sequencer index/data registersVille Syrjälä1-2/+8
2013-01-26drm/i915: Pass VLV_DISPLAY_BASE + reg to intel_{hdmi, dp}_init on VLVVille Syrjälä1-8/+8
2013-01-26drm/i915: VLV doesn't have SDVOVille Syrjälä1-7/+2
2013-01-26drm/i915: Always use adpa_regVille Syrjälä1-14/+15
2013-01-26drm/i915: PLL registers need an offset on VLVVille Syrjälä1-4/+4
2013-01-24drm/i915: Set display_mmio_offset for VLVVille Syrjälä1-0/+2
2013-01-24drm/i915: GPIO/GMBUS registers need an offset on VLVVille Syrjälä1-0/+2
2013-01-24drm/i915: DPIO registers are VLV only and need an offsetVille Syrjälä1-4/+6
2013-01-24drm/i915: Spell out VLV_DISPLAY_BASE for interrupt registersVille Syrjälä1-5/+5
2013-01-24drm/i915: Make VLV_GUNIT_CLOCK_GATE register value more readableVille Syrjälä1-1/+1
2013-01-24drm/i915: FB_BLC_SELF_VLV is VLV only and needs an offsetVille Syrjälä1-1/+1
2013-01-24drm/i915: Pipe palette registers need an offset on VLVVille Syrjälä1-2/+2
2013-01-24drm/i915: Pipe timing registers need an offset on VLVVille Syrjälä1-18/+18
2013-01-24drm/i915: PORT_HOTPLUG registers need an offset on VLVVille Syrjälä1-2/+2
2013-01-24drm/i915: Panel fitter registers need an offset on VLVVille Syrjälä1-3/+3
2013-01-24drm/i915: DPFLIPSTAT and DPINVGTT registers are VLV only and need an offsetVille Syrjälä1-2/+2
2013-01-24drm/i915: DSPFW registers need an offset on VLVVille Syrjälä1-3/+3
2013-01-24drm/i915: VLV_DDL is VLV only and needs an offsetVille Syrjälä1-2/+2
2013-01-24drm/i915: Cursor registers need an offset on VLVVille Syrjälä1-6/+6
2013-01-24drm/i915: Pipe registers need an offset on VLVVille Syrjälä1-10/+10
2013-01-24drm/i915: Primary plane registers need an offset on VLVVille Syrjälä1-18/+18
2013-01-24drm/i915: PIPE M/N registers need an offset on VLVVille Syrjälä1-16/+16
2013-01-24drm/i915: VLV_VIDEO_DIP_CTL is for VLV onlyVille Syrjälä1-6/+6
2013-01-24drm/i915: Per-pipe PP registers are for VLV onlyVille Syrjälä1-11/+11
2013-01-24drm/i915: AUD_VID_DID needs an offset on VLVVille Syrjälä1-1/+1
2013-01-24drm/i915: Add display_display_mmio_offset to intel_device_infoVille Syrjälä1-0/+1
2013-01-24drm/i915: Convert intel_dp to enum portVille Syrjälä1-4/+5
2013-01-24drm/i915: Convert intel_hdmi to enum portVille Syrjälä1-12/+15
2013-01-24drm/i915: don't save/restore DSPARB on gen5+Paulo Zanoni1-2/+4
2013-01-23drm/i915: fixup sbi_read/write lockingDaniel Vetter1-0/+4
2013-01-22drm/i915: HDMI/DP - ELD info refresh support for HaswellWang Xingchao3-0/+26
2013-01-22drm/i915: use gem_set_seqno() on hardware initMika Kuoppala2-4/+4
2013-01-22drm/i915: add quirk to invert brightness on Packard Bell NCL20Jani Nikula1-0/+3
2013-01-22drm/i915: add quirk to invert brightness on eMachines e725Jani Nikula1-0/+3
2013-01-22drm/i915: add quirk to invert brightness on eMachines G725Jani Nikula1-0/+3
2013-01-21drm/i915: clarify concurrent hang detect/gpu reset consistencyDaniel Vetter1-2/+13
2013-01-21drm/i915: create a race-free reset detectionDaniel Vetter3-12/+65
2013-01-20drm/i915: Only apply the mb() when flushing the GTT domain during a finishChris Wilson1-3/+3
2013-01-20drm/i915: Only insert the mb() before updating the fence parameterChris Wilson1-10/+30
2013-01-20drm/i915: clear up wedged transitionsDaniel Vetter5-44/+74
2013-01-20drm/i915: fix reset handling in the throttle ioctlDaniel Vetter1-2/+7
2013-01-20drm/i915: move wedged to the other gpu error handling stuffDaniel Vetter6-35/+30
2013-01-20drm/i915: extract hangcheck/reset/error_state state into substructDaniel Vetter7-61/+73
2013-01-20drm/i915: move dev_priv->mm out of lineDaniel Vetter1-100/+102
2013-01-20agp/intel: Add gma_bus_addrBen Widawsky2-4/+3
2013-01-20drm/i915: Needs_dmar, notBen Widawsky3-35/+22
2013-01-20drm/i915: Remove scratch page from sharedBen Widawsky4-15/+15
2013-01-20drm/i915: Cut out the infamous ILK w/a from AGP layerBen Widawsky4-32/+23
2013-01-20drm/i915: Provide the quantization range in the AVI infoframeVille Syrjälä3-2/+29
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