| Commit message (Collapse) | Author | Age | Files | Lines |
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Add i2c mux to 8 slots of server board and add the io expanders and
eeprom for the slots.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20241003074251.3818101-2-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Remove IO expanders on I2C bus 13 according to schematic change.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20241001083021.3462426-1-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Add following GPIO line names so that userspace can control them
- PCH related GPIOs
- FPGA related GPIOs
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Eddie James <eajames@linux.ibm.com>
Link: https://patch.msgid.link/20241001191756.234096-4-ninad@linux.ibm.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Enable serial GPIO0. Set number of GPIO lines to 128 and bus frequency
to 1MHz.
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Eddie James <eajames@linux.ibm.com>
Link: https://patch.msgid.link/20241001191756.234096-3-ninad@linux.ibm.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Bump up i2c8 and i2c15 bus frequency so that PCIe slot and FPGA runs
faster
Signed-off-by: Ninad Palsule <ninad@linux.ibm.com>
Reviewed-by: Eddie James <eajames@linux.ibm.com>
Link: https://patch.msgid.link/20241001191756.234096-2-ninad@linux.ibm.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Remove the space in the compatible string of adm1272 to match the
pattern of compatible.
Fixes: 2b8d94f4b4a4 ("ARM: dts: aspeed: yosemite4: add Facebook Yosemite 4 BMC")
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Fixes: 2b8d94f4b4a4765d ("ARM: dts: aspeed: yosemite4: add Facebook Yosemite 4 BMC")
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://patch.msgid.link/20240927085213.331127-1-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Add I2C mux for Management Board to separate the I2C bus 35 for
updating CPLD firmware and I2C bus 34 for the other devices.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240926033534.4174707-1-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Update NIC1 FRU EEPROM address to 0x52 based on EVT changes.
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Link: https://patch.msgid.link/20240926-catalina-evt-dvt-system-modify-v2-3-a861daeba059@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Enable mac2 in advance for DVT HW schematic.
- EVT system:
- eth0 (mac2): no NCSI
- eth1 (mac3): with NCSI
- DVT system:
- eth0 (mac2): with NCSI
- eth1 (mac3): with NCSI
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Link: https://patch.msgid.link/20240926-catalina-evt-dvt-system-modify-v2-2-a861daeba059@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Due to EVT hardware changes, move HDD board i2c mux bus from i2c30 to i2c5.
Signed-off-by: Potin Lai <potin.lai@quantatw.com>
Link: https://patch.msgid.link/20240926-catalina-evt-dvt-system-modify-v2-1-a861daeba059@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Revise flash layout to 128MB since we are using 1GB flash memory in our
project.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240924094430.272074-3-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Revise quad mode to dual mode to keep the write protect feature for the
SPI flash because the WP pin is the same pin with IO2 pin in quad mode.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240924094430.272074-2-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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The Minerva platform has 16 compute blades and 6 network blades, each with
an EEPROM that can be operated by the CMM. This commit adds support for
each FRU.
Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com>
Link: https://patch.msgid.link/20240924140215.2484170-4-yangchen.openbmc@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Change the i2c mux channel to match the correct fan board location.
Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com>
Link: https://patch.msgid.link/20240924140215.2484170-3-yangchen.openbmc@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Modify the SGPIO line names sent from the CMM CPLD in the DVT version and
map the blade and FCB numbers to match the silkscreen labels on the rack as
follows:
1. Change the compute blade numbering from 0-15 to 1-16.
2. Change the network blade numbering from 0-5 to 1-6.
3. Update the FCB numbering from TOP0/1, MID0/1, and BOT0/1 to FCB1-6.
4. Revise the SGPIO line name for DVT changed.
Signed-off-by: Yang Chen <yangchen.openbmc@gmail.com>
Link: https://patch.msgid.link/20240924140215.2484170-2-yangchen.openbmc@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Enable spi-gpio setting for TPM device in yosemite4.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240920080227.711691-1-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Revise adc128d818 adc mode on Spider Board according to schematic.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://patch.msgid.link/20240920085007.1076174-1-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Add the `i2c-mux-idle-disconnect` property to all i2c-mux nodes to
ensure proper behavior when switching between multiple I2C buses.
This avoids potential confusion caused by device addresses appearing on
multiple buses when they are not actively selected.
Signed-off-by: Potin Lai <potin.lai.pt@gmail.com>
Link: https://patch.msgid.link/20240920-catalina-i2c-mux-fix-2-v1-1-66cce7c54188@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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We use CPLD to emulate gpio pca9506 I/O expander on each server
boards.
Therefore, add pca9506 to probe driver for the CPLD I/O expander.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240910054751.2943217-3-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Revise to use adm1281 for HSC according to the hardware design change.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240910054751.2943217-2-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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This patch enables the PECI interface and configures the LPC Snoop for
ports 0x80 and 0x81 in the ASPEED BMC for IBM System1.
Signed-off-by: Manojkiran Eda <manojkiran.eda@gmail.com>
Link: https://patch.msgid.link/20240918-dts-aspeed-system1-peci-snoop-v2-1-2d4d17403670@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Enable interrupt setting and add GPIO line name for pca9555 for the I/O
expanders on Medusa board.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240918101742.1346788-1-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Blueridge LED names to include the "led-" prefix as is proper.
Rainier should match for ease of application design. In addition,
the gpio line name ought to match.
Signed-off-by: Eddie James <eajames@linux.ibm.com>
Link: https://patch.msgid.link/20240917162100.1386130-1-eajames@linux.ibm.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Add below gpio line names to io expanders for more platform features.
- ext-vref-sel
- presence-hdd-bp5-n
- presence-hdd-bp6-n
- bmc-ocp0-en-n
- bmc-ocp1-en-n
- bmc-riser-en-n
- gpi0, gpi1
Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
Link: https://patch.msgid.link/20240905063521.319416-3-chanh@os.amperecomputing.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Add the MAX31790 nodes as i2c fan controllers.
Signed-off-by: Chanh Nguyen <chanh@os.amperecomputing.com>
Link: https://patch.msgid.link/20240905063521.319416-2-chanh@os.amperecomputing.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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power-card-enable
power-fault-n
power-hsc-good
power-chassis-good
asic0-card-type-detection0-n
asic0-card-type-detection1-n
asic0-card-type-detection2-n
presence-cmm
uart-switch-button
uart-switch-lsb
uart-switch-msb
reset-control-cmos-clear
Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
Link: https://patch.msgid.link/20240909080459.3457853-3-peteryin.openbmc@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Add "nxp,pcf8563" device and the slave address is 0x51.
Signed-off-by: Peter Yin <peteryin.openbmc@gmail.com>
Link: https://patch.msgid.link/20240909080459.3457853-2-peteryin.openbmc@gmail.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Enable Yosemite4 adc15 config for monitoring P3V_BAT_SCALED.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240910022236.1564291-1-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Enable watchdog2 setting for yosemite4 system.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://patch.msgid.link/20240910080951.3568594-1-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Change eeprom on Medusa Board to AT24C128 according to hardware change.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240910084109.3585923-1-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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Remove two temperature sensors on Medusa Board according to hardware
change.
Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
Link: https://patch.msgid.link/20240910085701.3595248-1-Delphine_CC_Chiu@wiwynn.com
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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at24.yaml defines the node name for at24 EEPROMs as 'eeprom'.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20240910215929.823913-1-robh@kernel.org
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
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https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/dt
Qualcomm Arm32 DeviceTree updates for v6.14
Describe the interconnect paths for PCIe EP controllers on SDX55 and
SDX65. Disable USB U1/U2 entry to improve USB stability on the same.
* tag 'qcom-arm32-for-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
ARM: dts: qcom: sdx55: Disable USB U1/U2 entry
ARM: dts: qcom: sdx65: Disable USB U1/U2 entry
ARM: dts: qcom: sdx55: Add CPU PCIe EP interconnect path
ARM: dts: qcom: sdx65: Add PCIe EP interconnect path
Link: https://lore.kernel.org/r/20250111171126.369502-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:
1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.
2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.
3. On targets like SDX75, intermittent disconnects were observed
with certain cables due to impedence variations.
Disabling these intermittent power states enhances device stability
without affecting power usage.
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241231080932.3149448-3-quic_prashk@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Disable U1 and U2 power-saving states to improve stability of USB.
These low-power link states, designed to reduce power consumption
during idle periods, can cause issues in latency-sensitive or high
throughput use cases. Over the years, some of the issues seen are
as follows:
1. In device mode of operation, when UVC is active, enabling U1/U2
is sometimes causing packets drops due to delay in entry/exit of
intermittent these low power states. These packet drops are often
reflected as missed isochronous transfers, as the controller wasn't
able to send packet in that microframe interval and hence glitches
are seen on the final transmitted video output.
2. On older targets like SM8150/SM8250/SM8350, there have been
throughput issues seen during tethering use cases.
3. On targets like SDX75, intermittent disconnects were observed
with certain cables due to impedence variations.
Disabling these intermittent power states enhances device stability
without affecting power usage.
Signed-off-by: Prashanth K <quic_prashk@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241231080932.3149448-2-quic_prashk@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add cpu-pcie interconnect path for PCIe EP to sdx55 platform.
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/1689751218-24492-4-git-send-email-quic_krichai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Add pcie-mem & cpu-pcie interconnect path ifor PCIe EP to sdx65 platform.
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com>
Link: https://lore.kernel.org/r/1689751218-24492-3-git-send-email-quic_krichai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into soc/dt
ARM: tegra: Device tree fixes for v6.14-rc1
This contains a fix that makes sure the power to the USB ports is
maintained during boot. This helps with booting from USB storage.
* tag 'tegra-for-6.14-arm-dt' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: nyan: Maintain power to USB ports on boot
Link: https://lore.kernel.org/r/20250110185355.4143505-2-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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USB ports are turned on by the firmware as it looks for disks to boot,
ensure that they aren't power cycled before the xHCI driver comes up.
This enables USB devices to be ready for use faster and reduces wear
and risk of data loss on storage devices. A particularly annoying case
was booting from a mechanical disk, which takes time to spin up again.
Vendor kernel also kept these ports powered, and by the same means.
Signed-off-by: Michal Pecio <michal.pecio@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM-based SoCs Device Tree updates
for 6.14, please pull the following:
- Rob removes some unused and undocumented properties pertaining to the
SPI flash controller on Broadcom boards
- Linus adds a number of BCM6846 peripherals: HWRNG, watchdog, GPIO,
MDIO, LED controller, DMA and then proceeds with adding support for
the GEnexsis XG6846B PON router
- Rosen sets the MAC address NVMEM reference on the Meraki MR26 platform
* tag 'arm-soc/for-6.14/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: meraki-mr26: set mac address for gmac0
ARM: dts: broadcom: Add Genexis XG6846B DTS file
dt-bindings: arm: bcmbca: Add Genexis XG6846B
dt-bindings: vendor-prefixes: Add Genexis
ARM: dts: bcm6846: Add ARM PL081 DMA block
ARM: dts: bcm6846: Add LED controller
ARM: dts: bcm6846: Add MDIO control block
ARM: dts: bcm6846: Add GPIO blocks
ARM: dts: bcm6846: Enable watchdog
ARM: dts: bcm6846: Add iproc rng
arm: dts: broadcom: Remove unused and undocumented properties
Link: https://lore.kernel.org/r/20250109224756.3632025-1-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Currently this needs to be done in userspace.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
Link: https://lore.kernel.org/r/20241021015147.172700-1-rosenp@gmail.com
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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This adds a device tree for the Genexis XG6846B router.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-9-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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The ARM PL081 DMA controller can be found in the BCM6846
memory map, and it turns out to work.
The block may be used as DMA engine for some of the
peripherals (maybe the EMMC controller found in the same
group of peripherals?) but it can always be used as a
memcpy engine, which is a generic "blitter".
I tested it with the dmatest module, and it copies
lots of data very fast and fires hundreds of thousands
of interrupts so it works just fine.
Add it to the BCM6846 DTSI file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-6-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Add the BCMBCA LED controller to the BCM6846 DTSI.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-5-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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This adds the MDIO block found in the BCM6846. Use the new
"brcm,bcm6846-mdio" compatible (merged to the networking tree)
for this block.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-4-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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The BCM6846 has the same simplistic GPIOs as some other
Broadcom SoCs: plain memory-mapped registers with up to
8 blocks of 32 GPIOs each totalling 256 GPIOs.
Users of the SoC can selectively enable the GPIO blocks
actually used with a certain design.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-3-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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The BCM6846 has a BCM7038-compatible watchdog timer, just
add it to the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-2-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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The bcm6846 has a standard iproc 200 RNG which is already
fully supported by bindings, so just add it to the DTS file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241019-genexis-xg6846b-base-v3-1-8375a0e1f89f@linaro.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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Remove properties which are both unused in the kernel and undocumented.
Most likely they are leftovers from downstream.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241115193904.3624350-1-robh@kernel.org
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
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https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into soc/dt
Microchip AT91 device tree updates for v6.14 #2
This update includes:
- device tree files for the SAMA7D65 SoC and its evaluation board
* tag 'at91-dt-6.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: dts: microchip: add support for sama7d65_curiosity board
ARM: dts: microchip: add sama7d65 SoC DT
Link: https://lore.kernel.org/r/20250109164317.1154613-1-claudiu.beznea@tuxon.dev
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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