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* MIPS: lantiq: add missing GPHY clock aliases for ar10 and grx390Aleksander Jan Bajkowski2020-08-171-2/+8
| | | | | | | | | | | | | | | | | | | | | | Add missing GPHY clock aliases for ar10 (xrx300) and grx390 (xrx330). PMU in ar10 and grx390 differs from vr9. Ar10 has 3 and grx390 has 4 built-in GPHY compared to vr9 which has 2. Corespondings PMU bit: GPHY0 -> bit 29 GPHY1 -> bit 30 GPHY2 -> bit 31 GPHY3 -> bit 26 Tested on D-Link DWR-966 with OpenWRT. Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Cc: linux-mips@vger.kernel.org Cc: john@phrozen.org Cc: hauke@hauke-m.de Cc: tsbogend@alpha.franken.de Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* MIPS: lantiq: xway: sysctrl: fix the GPHY clock alias namesMartin Blumenstingl2020-06-151-4/+4
| | | | | | | | | | | | The dt-bindings for the GSWIP describe that the node should be named "switch". Use the same name in sysctrl.c so the GSWIP driver can actually find the "gphy0" and "gphy1" clocks. Fixes: 14fceff4771e51 ("net: dsa: Add Lantiq / Intel DSA driver for vrx200") Cc: stable@vger.kernel.org Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
* remove ioremap_nocache and devm_ioremap_nocacheChristoph Hellwig2020-01-061-3/+3
| | | | | | | | ioremap has provided non-cached semantics by default since the Linux 2.6 days, so remove the additional ioremap_nocache interface. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Arnd Bergmann <arnd@arndb.de>
* MIPS: lantiq: update the clock alias' for the mainline PCIe PHY driverMartin Blumenstingl2019-08-241-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | The mainline PCIe PHY driver has it's own devicetree node. Update the clock alias so the mainline driver finds the clocks. The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300 and GRX390. The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and GRX390. The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390. Lantiq's board support package (called "UGW") names these registers "PDI". Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Paul Burton <paul.burton@mips.com> Cc: linux-mips@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: john@phrozen.org Cc: kishon@ti.com Cc: ralf@linux-mips.org Cc: robh+dt@kernel.org Cc: linux-kernel@vger.kernel.org Cc: hauke@hauke-m.de Cc: mark.rutland@arm.com Cc: ms@dev.tdt.de
* treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner2019-06-191-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* net: dsa: Add Lantiq / Intel DSA driver for vrx200Hauke Mehrtens2018-09-131-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | This adds the DSA driver for the GSWIP Switch found in the VRX200 SoC. This switch is integrated in the DSL SoC, this SoC uses a GSWIP version 2.1, there are other SoCs using different versions of this IP block, but this driver was only tested with the version found in the VRX200. Currently only the basic features are implemented which will forward all packages to the CPU and let the CPU do the forwarding. The hardware also support Layer 2 offloading which is not yet implemented in this driver. The GPHY FW loaded is now done by this driver and not any more by the separate driver in drivers/soc/lantiq/gphy.c, I will remove this driver is a separate patch. to make use of the GPHY this switch driver is needed anyway. Other SoCs have more embedded GPHYs so this driver should support a variable number of GPHYs. After the firmware was loaded the GPHY can be probed on the MDIO bus and it behaves like an external GPHY, without the firmware it can not be probed on the MDIO bus. The clock names in the sysctrl.c file have to be changed because the clocks are now used by a different driver. This should be cleaned up and a real common clock driver should provide the clocks instead. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: David S. Miller <davem@davemloft.net>
* net: lantiq: Add Lantiq / Intel VRX200 Ethernet driverHauke Mehrtens2018-09-131-3/+3
| | | | | | | | | | | | | | | | | | This drives the PMAC between the GSWIP Switch and the CPU in the VRX200 SoC. This is currently only the very basic version of the Ethernet driver. When the DMA channel is activated we receive some packets which were send to the SoC while it was still in U-Boot, these packets have the wrong header. Resetting the IP cores did not work so we read out the extra packets at the beginning and discard them. This also adapts the clock code in sysctrl.c to use the default name of the device node so that the driver gets the correct clock. sysctrl.c should be replaced with a proper common clock driver later. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: David S. Miller <davem@davemloft.net>
* MIPS: lantiq: Enable AHB Bus for USBMathias Kresin2018-03-211-3/+3
| | | | | | | | | | | | | | | | | On Danube and AR9 the USB core is connected though a AHB bus to the main system cross bar, hence we need to enable the gating clock of the AHB Bus as well to make the USB controller work. Fixes: dea54fbad332 ("phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module") Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.14+ Patchwork: https://patchwork.linux-mips.org/patch/18814/ Signed-off-by: James Hogan <jhogan@kernel.org>
* MIPS: lantiq: Fix Danube USB clockMathias Kresin2018-03-211-1/+1
| | | | | | | | | | | | | | | | | | | | On Danube the USB0 controller registers are at 1e101000 and the USB0 PHY register is at 1f203018 similar to all other lantiq SoCs. Activate the USB controller gating clock thorough the USB controller driver and not the PHY. This fixes a problem introduced in a previous commit. Fixes: dea54fbad332 ("phy: Add an USB PHY driver for the Lantiq SoCs using the RCU module") Signed-off-by: Mathias Kresin <dev@kresin.me> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.14+ Patchwork: https://patchwork.linux-mips.org/patch/18816/ Signed-off-by: James Hogan <jhogan@kernel.org>
* MIPS: Lantiq: Fix ASC0/ASC1 clocksMartin Schiller2017-11-071-4/+2
| | | | | | | | | | | | | | | | | | ASC1 is available on every Lantiq SoC (also AmazonSE) and should be enabled like the other generic xway clocks instead of ASC0, which is only available for AR9 and Danube. Signed-off-by: Martin Schiller <ms@dev.tdt.de> Acked-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: John Crispin <john@phrozen.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Felix Fietkau <nbd@nbd.name> Cc: Martin Schiller <ms@dev.tdt.de> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16145/ [jhogan@kernel.org: Drop braces] Signed-off-by: James Hogan <jhogan@kernel.org>
* phy: Add an USB PHY driver for the Lantiq SoCs using the RCU moduleHauke Mehrtens2017-09-041-18/+18
| | | | | | | | | | | | | | | | | | | | | | This driver starts the DWC2 core(s) built into the XWAY SoCs and provides the PHY interfaces for each core. The phy instances can be passed to the dwc2 driver, which already supports the generic phy interface. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Rob Herring <robh@kernel.org> Cc: martin.blumenstingl@googlemail.com Cc: john@phrozen.org Cc: andy.shevchenko@gmail.com Cc: p.zabel@pengutronix.de Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17127/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: Add a GPHY driver which uses the RCU syscon-mfdMartin Blumenstingl2017-09-041-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Compared to the old xrx200_phy_fw driver the new version has multiple enhancements. The name of the firmware files does not have to be added to all .dts files anymore - one now configures the GPHY mode (FE or GE) instead. Each GPHY can now also boot separate firmware (thus mixing of GE and FE GPHYs is now possible). The new implementation is based on the RCU syscon-mfd and uses the reeset_controller framework instead of raw RCU register reads/writes. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Cc: john@phrozen.org Cc: p.zabel@pengutronix.de Cc: kishon@ti.com Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17128/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: Convert the fpi bus driver to a platform_driverHauke Mehrtens2017-09-041-41/+0
| | | | | | | | | | | | | | | | | | | | | | | | Instead of hacking the configuration of the FPI bus into the arch code add an own bus driver for this internal bus. The FPI bus is the main bus of the SoC. This bus driver makes sure the bus is configured correctly before the child drivers are getting initialized. This driver will probably also be used on different SoCs later. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Cc: john@phrozen.org Cc: p.zabel@pengutronix.de Cc: kishon@ti.com Cc: mark.rutland@arm.com Cc: linux-mips@linux-mips.org Cc: linux-mtd@lists.infradead.org Cc: linux-watchdog@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-spi@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/17122/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: fix missing xbar kernel panicHauke Mehrtens2017-03-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Commit 08b3c894e565 ("MIPS: lantiq: Disable xbar fpi burst mode") accidentally requested the resources from the pmu address region instead of the xbar registers region, but the check for the return value of request_mem_region() was wrong. Commit 98ea51cb0c8c ("MIPS: Lantiq: Fix another request_mem_region() return code check") fixed the check of the return value of request_mem_region() which made the kernel panics. This patch now makes use of the correct memory region for the cross bar. Fixes: 08b3c894e565 ("MIPS: lantiq: Disable xbar fpi burst mode") Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Cc: John Crispin <john@phrozen.org> Cc: james.hogan@imgtec.com Cc: arnd@arndb.de Cc: sergei.shtylyov@cogentembedded.com Cc: john@phrozen.org Cc: <stable@vger.kernel.org> # 4.4.x- Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/15751 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Keep ethernet enabled during bootFelix Fietkau2017-02-171-4/+4
| | | | | | | | | | | | | | | | | | | Disabling ethernet during reboot (only to enable it again when the ethernet driver attaches) can put the chip into a faulty state where it corrupts the header of all incoming packets. This happens if packets arrive during the time window where the core is disabled, and it can be easily reproduced by rebooting while sending a flood ping to the broadcast address. Fixes: 95135bfa7ead ("MIPS: Lantiq: Deactivate most of the devices by default") Signed-off-by: Felix Fietkau <nbd@nbd.name> Acked-by: John Crispin <john@phrozen.org> Cc: hauke.mehrtens@lantiq.com Cc: linux-mips@linux-mips.org Cc: <stable@vger.kernel.org> # 4.4.x- Patchwork: https://patchwork.linux-mips.org/patch/15078/ Signed-off-by: James Hogan <james.hogan@imgtec.com>
* MIPS: Lantiq: Fix another request_mem_region() return code checkArnd Bergmann2017-01-251-2/+2
| | | | | | | | | | | | | | | | | Hauke already fixed a couple of them, but one instance remains that checks for a negative integer when it should check for a NULL pointer: arch/mips/lantiq/xway/sysctrl.c: In function 'ltq_soc_init': arch/mips/lantiq/xway/sysctrl.c:473:19: error: ordered comparison of pointer with integer zero [-Werror=extra] Fixes: 6e807852676a ("MIPS: Lantiq: Fix check for return value of request_mem_region()") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/15043/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Change my email addressJohn Crispin2016-05-131-1/+1
| | | | | | | | | The old address is no longer valid. Use the my new one instead. Signed-off-by: John Crispin <john@phrozen.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13201/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: Disable xbar fpi burst modeJohn Crispin2015-11-111-0/+41
| | | | | | | Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11458/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Fix check for return value of request_mem_region()Hauke Mehrtens2015-11-111-6/+6
| | | | | | | | | | | | request_mem_region() returns a pointer and not an integer with an error value. A check for "< 0" on a pointer will cause problems, replace it with not null checks instead. This was found with sparse. Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11395/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add misc clocksHauke Mehrtens2015-11-111-1/+3
| | | | | | | | Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11393/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add 1e103100.deu clockHauke Mehrtens2015-11-111-0/+6
| | | | | | | | Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11392/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add clock for mei driverHauke Mehrtens2015-11-111-0/+6
| | | | | | | | Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11391/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add pmu bits for ar10 and grx390Hauke Mehrtens2015-11-111-1/+56
| | | | | | | | Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11388/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add PMU bits for USB and SDIO devicesHauke Mehrtens2015-11-111-1/+23
| | | | | | | | | | This adds the PUM bits for USB and SDIO devices Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11387/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Deactivate most of the devices by defaultHauke Mehrtens2015-11-111-21/+28
| | | | | | | | | | | | | When the SoC starts up most of the devices should be deactivated by the PMU, they should be activated when they get used by their drivers. Some devices should not get deactivate at startup like the serial, register them in a special way. Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11386/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add support for setting PMU register on AR10 and GRX390Hauke Mehrtens2015-11-111-11/+73
| | | | | | | | | | This adds support for setting the PMU register on the AR10 and GRX390. Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11382/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: Lantiq: Add locking for PMU register and check status afterwardsHauke Mehrtens2015-11-111-5/+27
| | | | | | | | | | | | | | | | | The PMU register are accessed in a non atomic way and they could be accessed by different threads simultaneously, which could cause problems this patch adds locking around the PMU registers. In addition we now also wait till the PMU is actually deactivated. [ralf@linux-mips.org: Fix spelling mistake in commit message as noticed by Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>.] Signed-off-by: Hauke Mehrtens <hauke.mehrtens@lantiq.com> Acked-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/11381/ Patchwork: https://patchwork.linux-mips.org/patch/11396/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* treewide: fix errors in printkMasanari Iida2014-09-011-1/+1
| | | | | | | | | This patch fix spelling typo in printk. Signed-off-by: Masanari Iida <standby24x7@gmail.com> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
* MIPS: Panic messages should not end in \n.Ralf Baechle2013-10-291-1/+1
| | | | | | | Panic() is going to add a \n itself and it's annoying if a panic message rolls of the screen on a device with no scrollback. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: add GPHY clock gate bitsJohn Crispin2013-02-171-0/+1
| | | | | | | Explicitly enable the clock gate of the internal GPHYs found on xrx200. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4816/
* MIPS: lantiq: adds static clock for PP32John Crispin2013-02-171-5/+7
| | | | | | | | The Lantiq DSL SoCs have an internal networking processor. Add code to read the static clock rate. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4815/
* MIPS: lantiq: trivial typo fixJohn Crispin2013-02-171-1/+1
| | | | | | | "nodes" is written with a single "s" Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4814/
* MIPS: lantiq: adds xrx200 ethernet clock definitionJohn Crispin2012-11-111-0/+4
| | | | | Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4521
* Merge branch 'master' of git://dev.phrozen.org/mips-next into ↵Ralf Baechle2012-10-051-0/+2
|\ | | | | | | mips-for-linux-next
| * MIPS: lantiq: explicitly enable clkout generationJohn Crispin2012-08-221-0/+2
| | | | | | | | | | | | | | | | Previously we relied on the bootloader to have enabled this bit. However some bootloaders seem to not enable this for us. Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4120/
* | MIPS: lantiq: enable pci clk conditional for xrx200 SoCJohn Crispin2012-08-231-1/+2
|/ | | | | | | | The xrx200 SoC family has the same PCI clock register layout as the AR9. Enable the same quirk as for AR9 Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/4235/
* MIPS: Lantiq: Fix interface clock and PCI control register offsetJohn Crispin2012-08-011-21/+28
| | | | | | | | | | | The XRX200 based SoC have a different register offset for the interface clock and PCI control registers. This patch detects the SoC and sets the register offset at runtime. This make PCI work on the VR9 SoC. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/4113/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: remove orphaned codeJohn Crispin2012-05-261-0/+4
| | | | | | | | | | Now that all drivers are converted to OF we are able to remove some remaining pieces of orphaned code. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3841/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* MIPS: lantiq: implement support for clkdev apiJohn Crispin2012-05-211-0/+367
This patch unifies all clock generation and gating code into one file. All drivers will now be able to request their clocks via their device. This patch also adds support for the clockout feature, which allows clock generation on external pins. Support for COMMON_CLK will be provided in the next series. Signed-off-by: John Crispin <blogic@openwrt.org> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3804/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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