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| | | | | | * clk: socfpga: clk-pll: Remove unused variable 'rc'Jian Xin2021-06-281-2/+1
| | | | | | * clk: agilex/stratix10/n5x: fix how the bypass_reg is handledDinh Nguyen2021-06-281-3/+8
| | | | | | * clk: agilex/stratix10: add support for the 2nd bypassDinh Nguyen2021-06-283-2/+123
| | | | | | * clk: agilex/stratix10: fix bypass representationDinh Nguyen2021-06-282-21/+91
| | | | | | * clk: agilex/stratix10: remove noc_clkDinh Nguyen2021-06-282-34/+30
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| | | | | * clk: zynqmp: Handle divider specific read only flagRajan Vaja2021-06-291-1/+9
| | | | | * clk: zynqmp: Use firmware specific mux clock flagsRajan Vaja2021-06-292-1/+30
| | | | | * clk: zynqmp: Use firmware specific divider clock flagsRajan Vaja2021-06-292-1/+33
| | | | | * clk: zynqmp: Use firmware specific common clock flagsRajan Vaja2021-06-296-6/+52
| | | | | * clk: zynqmp: pll: Remove some dead codeChristophe JAILLET2021-06-261-2/+0
| | | | | * clk: zynqmp: fix compile testing without ZYNQMP_FIRMWAREMichal Simek2021-06-262-8/+24
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| | | * | clk: meson: g12a: Add missing NNA source clocks for g12bNick Xie2021-06-091-0/+6
| | | * | clk: meson: axg-audio: improve deferral handlingJerome Brunet2021-05-241-3/+2
| | | * | clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet2021-05-201-1/+1
| | | * | clk: meson: pll: switch to determine_rate for the PLL opsMartin Blumenstingl2021-05-191-11/+15
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| | * | clk: rockchip: export ACLK_VCODEC for RK3036Alex Bee2021-05-281-1/+1
| | * | clk: rockchip: fix rk3568 cpll clk gate bitsPeter Geis2021-05-241-5/+5
| | * | clk: rockchip: Optimize PLL table memory usageElaine Zhang2021-05-111-11/+18
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| *-------. \ Merge branches 'clk-legacy', 'clk-vc5', 'clk-allwinner', 'clk-nvidia' and 'cl...Stephen Boyd2021-06-2923-296/+931
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| | | | | | * | clk: imx8mq: remove SYS PLL 1/2 clock gatesLucas Stach2021-06-141-38/+18
| | | | | | * | clk: imx: scu: Do not enable runtime PM for CPU clksNitin Garg2021-06-141-12/+18
| | | | | | * | clk: imx: scu: add parent save and restoreDong Aisheng2021-06-141-1/+28
| | | | | | * | clk: imx: scu: Only save DC SS clock using non-cached clock rateAnson Huang2021-06-141-1/+8
| | | | | | * | clk: imx: scu: Add A72 frequency scaling supportAnson Huang2021-06-141-1/+3
| | | | | | * | clk: imx: scu: Add A53 frequency scaling supportAnson Huang2021-06-141-2/+2
| | | | | | * | clk: imx: scu: bypass pi_pll enable status restoreDong Aisheng2021-06-141-1/+1
| | | | | | * | clk: imx: scu: detach pd if can't power upDong Aisheng2021-06-141-0/+1
| | | | | | * | clk: imx: scu: bypass cpu clock save and restoreDong Aisheng2021-06-141-0/+10
| | | | | | * | clk: imx: scu: add parallel port clock opsGuoniu.zhou2021-06-141-0/+8
| | | | | | * | clk: imx: scu: add more scu clocksDong Aisheng2021-06-141-2/+150
| | | | | | * | clk: imx: scu: add enet rgmii gpr clocksDong Aisheng2021-06-141-4/+18
| | | | | | * | clk: imx8qm: add clock valid resource checkingDong Aisheng2021-06-144-1/+119
| | | | | | * | clk: imx8qxp: add clock valid checking mechnismDong Aisheng2021-06-145-8/+137
| | | | | | * | clk: imx: scu: add gpr clocks supportDong Aisheng2021-06-142-0/+215
| | | | | | * | clk: imx: scu: remove legacy scu clock binding supportDong Aisheng2021-06-142-135/+81
| | | | | | * | clk: imx: Remove the audio ipg clock from imx8mpJacky Bai2021-06-141-1/+0
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| | | | | * | clk: tegra: clk-tegra124-dfll-fcpu: don't use devm functions for regulatorAlexandru Ardelean2021-06-261-2/+2
| | | | | * | clk: tegra: tegra124-emc: Fix clock imbalance in emc_set_timing()Yang Yingliang2021-06-021-1/+3
| | | | | * | clk: tegra: Don't deassert reset on enabling clocksDmitry Osipenko2021-05-313-13/+1
| | | | | * | clk: tegra: Mark external clocks as not having reset controlDmitry Osipenko2021-05-311-3/+3
| | | | | * | clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttlingDmitry Osipenko2021-05-312-3/+15
| | | | | * | clk: tegra: Don't allow zero clock rate for PLLsDmitry Osipenko2021-05-311-0/+3
| | | | | * | clk: tegra: Halve SCLK rate on Tegra20Dmitry Osipenko2021-05-311-3/+3
| | | | | * | clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko2021-05-311-5/+4
| | | | | * | clk: tegra: Fix refcounting of gate clocksDmitry Osipenko2021-05-312-25/+58
| | | | | * | clk: tegra30: Use 300MHz for video decoder by defaultDmitry Osipenko2021-05-311-1/+1
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| | | | * / clk: sunxi-ng: v3s: fix incorrect postdivider on pll-audioTobias Schramm2021-05-241-2/+2
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| | | * / clk: vc5: fix output disabling when enabling a FODLuca Ceresoli2021-06-091-3/+24
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| | * | clkdev: remove unused clkdev_alloc() interfacesArnd Bergmann2021-06-081-28/+0
| | * | clkdev: remove CONFIG_CLKDEV_LOOKUPArnd Bergmann2021-06-082-7/+2
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