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* clk: ti: omap3+: dpll: use non-locking version of clk_get_rateTero Kristo2016-02-221-1/+2
| | | | | | | | | | | | | | As the code in this file is being executed within irq context in some cases, we must avoid the clk_get_rate which uses mutex internally. Switch the code to use clk_hw_get_rate instead which is non-locking. This fixes an issue where PM runtime will hang the system if enabled with a serial console before a suspend-resume cycle. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Tony Lindgren <tony@atomide.com> Fixes: a53ad8ef3dcc ("clk: ti: Convert to clk_hw based provider APIs") Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: gpio: Really allow an optional clock= DT propertyStephen Boyd2016-02-191-1/+1
| | | | | | | | | | | | | | We mis-merged the original patch from Russell here and so the patch went almost all the way, except that we still failed to probe when there wasn't a clocks property in the DT node. Allow that case by making a negative value from of_clk_get_parent_count() into "no parents", like the original patch did. Fixes: 7ed88aa2efa5 ("clk: fix clk-gpio.c with optional clock= DT property") Cc: Russell King <rmk+kernel@arm.linux.org.uk> Cc: Michael Turquette <mturquette@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Revert "clk: qcom: Specify LE device endianness"Stephen Boyd2016-02-1211-13/+0
| | | | | | | | | | | | | | | | | This reverts commit 329cabcecf94d8d7821e729dda284ba9dec44c87. The commit that caused us to specify LE device endianness here, 29bb45f25ff3 (regmap-mmio: Use native endianness for read/write, 2015-10-29), has been reverted in mainline so now when we specify LE it actively breaks big endian kernels because the byte swapping in regmap-mmio is incorrect. Let's revert this change because it will 1) fix the big endian kernels and 2) be redundant to specify LE because that will become the default soon. Cc: Kevin Hilman <khilman@linaro.org> Tested-by: Kevin Hilman <khilman@baylibre.com> Cc: Mark Brown <broonie@kernel.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* clk: versatile: mask VCO bits before writingLinus Walleij2016-02-101-0/+3
| | | | | | | | | | | | | | | | The Versatile syscon ICST driver OR:s the bits into place but forgets to mask the previous value, making the code only work if the register is zero or giving haphazard results. Mask the 19 bits used by the Versatile syscon interface register. Regression caused and now fixed by yours truly. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Fixes: 179c8fb3c2a6 ("clk: versatile-icst: convert to use regmap") Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* Merge tag 'tegra-for-4.5-clk-fixes' of ↵Stephen Boyd2016-02-086-97/+103
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into clk-fixes Pull tegra fixes from Thierry Reding: clk: tegra: Fixes for v4.5-rc3 This set contains a bunch of miscellaneous fixes that have accumulated over the past couple of weeks, primarily for the Tegra210 support added in v4.5-rc1. * tag 'tegra-for-4.5-clk-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: clk: tegra: super: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warnings for functions not declared as static clk: tegra: Fix sparse warning for pll_m clk: tegra: Use definition for pll_u override bit clk: tegra: Fix warning caused by pll_u failing to lock clk: tegra: Fix clock sources for Tegra210 EMC clk: tegra: Add the APB2APE audio clock on Tegra210 clk: tegra: Add missing of_node_put() clk: tegra: Fix PLLE SS coefficients clk: tegra: Fix typos around clearing PLLE bits during enable clk: tegra: Do not disable PLLE when under hardware control clk: tegra: Fix pllx dyn step calculation clk: tegra: pll: Fix potential sleeping-while-atomic clk: tegra: Fix the misnaming of nvenc from msenc clk: tegra: Fix naming of MISC registers clk: tegra: Remove improper flags for lock_enable clk: tegra: Fix divider on VI_I2C
| * clk: tegra: super: Fix sparse warnings for functions not declared as staticJon Hunter2016-02-021-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sparse reports the following warnings for structures and functions that should be declared static: drivers/clk/tegra/clk-tegra-super-gen4.c:70:35: warning: symbol 'tegra_super_gen_info_gen4' was not declared. Should it be static? drivers/clk/tegra/clk-tegra-super-gen4.c:96:35: warning: symbol 'tegra_super_gen_info_gen5' was not declared. Should it be static? drivers/clk/tegra/clk-tegra-super-gen4.c:174:13: warning: symbol 'tegra_super_clk_init' was not declared. Should it be static? Fix this by making the above static. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix sparse warnings for functions not declared as staticJon Hunter2016-02-021-17/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sparse reports the following warnings for functions in clk-tegra210.c that should be declared as static: drivers/clk/tegra/clk-tegra210.c:460:6: warning: symbol 'tegra210_pllcx_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:485:6: warning: symbol '_pllc_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:490:6: warning: symbol '_pllc2_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:495:6: warning: symbol '_pllc3_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:500:6: warning: symbol '_plla1_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:510:6: warning: symbol 'tegra210_plla_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:562:6: warning: symbol 'tegra210_plld_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:701:6: warning: symbol 'tegra210_plld2_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:709:6: warning: symbol 'tegra210_plldp_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:722:6: warning: symbol 'tegra210_pllc4_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:731:6: warning: symbol 'tegra210_pllre_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:844:6: warning: symbol 'tegra210_pllx_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:904:6: warning: symbol 'tegra210_pllmb_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:963:6: warning: symbol 'tegra210_pllp_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:1025:6: warning: symbol 'tegra210_pllu_set_defaults' was not declared. Should it be static? drivers/clk/tegra/clk-tegra210.c:1215:15: warning: symbol 'tegra210_clk_adjust_vco_min' was not declared. Should it be static? Fix this by declaring the above as static. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix sparse warning for pll_mJon Hunter2016-02-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sparse generates the following warning for the pll_m params structure: drivers/clk/tegra/clk-tegra210.c:1569:10: warning: Initializer entry defined twice drivers/clk/tegra/clk-tegra210.c:1570:10: also defined here Fix this by correcting the index for the MISC1 register. Fixes: b31eba5ff3f7 ("clk: tegra: Add support for Tegra210 clocks") Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Use definition for pll_u override bitJon Hunter2016-02-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | The definition, PLLU_BASE_OVERRIDE, for the pll_u OVERRIDE bit is defined but not used and when the OVERRIDE bit is cleared in tegra210_pll_init() the code directly uses the bit number. Therefore, use the definition, PLLU_BASE_OVERRIDE when clearing the OVERRIDE bit. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix warning caused by pll_u failing to lockJon Hunter2016-02-021-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the pll_u is not configured by the bootloader, then on kernel boot the following warning is seen: clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock tegra_init_from_table: Failed to enable pll_u_out1 ------------[ cut here ]------------ WARNING: at drivers/clk/tegra/clk.c:269 Modules linked in: CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.4.0-rc4-next-20151214+ #1 Hardware name: NVIDIA Tegra210 P2371 reference board (E.1) (DT) task: ffffffc0bc0a0000 ti: ffffffc0bc0a8000 task.ti: ffffffc0bc0a8000 PC is at tegra_init_from_table+0x140/0x164 LR is at tegra_init_from_table+0x140/0x164 pc : [<ffffffc0008fee78>] lr : [<ffffffc0008fee78>] pstate: 80000045 sp : ffffffc0bc0abd50 x29: ffffffc0bc0abd50 x28: ffffffc00090b8a8 x27: ffffffc000a06000 x26: ffffffc0bc019780 x25: ffffffc00086a708 x24: ffffffc00086a790 x23: ffffffc0006d7188 x22: ffffffc0bc010000 x21: 000000000000016e x20: ffffffc0bc00d100 x19: ffffffc000944178 x18: 0000000000000007 x17: 000000000000000e x16: 0000000000000001 x15: 0000000000000007 x14: 000000000000000e x13: 0000000000000013 x12: 000000000000001a x11: 000000000000004d x10: 0000000000000750 x9 : ffffffc0bc0a8000 x8 : ffffffc0bc0a07b0 x7 : 0000000000000001 x6 : 0000000002d5f0f8 x5 : 0000000000000000 x4 : 0000000000000000 x3 : 0000000000000002 x2 : ffffffc000996724 x1 : 0000000000000000 x0 : 0000000000000032 ---[ end trace cbd20ae519e92ced ]--- Call trace: [<ffffffc0008fee78>] tegra_init_from_table+0x140/0x164 [<ffffffc000900ac8>] tegra210_clock_apply_init_table+0x20/0x28 [<ffffffc0008fec40>] tegra_clocks_apply_init_table+0x18/0x24 [<ffffffc00008291c>] do_one_initcall+0x90/0x194 [<ffffffc0008cfab0>] kernel_init_freeable+0x148/0x1e8 [<ffffffc000636bb0>] kernel_init+0x10/0xdc [<ffffffc000085cd0>] ret_from_fork+0x10/0x40 clk_pll_wait_for_lock: Timed out waiting for pll pll_u_vco lock tegra_init_from_table: Failed to enable pll_u_out2 ------------[ cut here ]------------ pll_u can be either controlled by software or hardware and this is selected via the OVERRIDE bit in the pll_u base register. In the function tegra210_pll_init(), the OVERRIDE bit for pll_u is cleared, which selects hardware control of the pll. However, at the same time the pll_u clocks are populated in the init_table for tegra210 and so software will try to configure the pll_u if it is not already configured and hence, the above warning is seen when the pll fails to lock. Remove the pll_u clocks from the init_table so that software does not try to configure this pll on boot. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix clock sources for Tegra210 EMCJon Hunter2016-02-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMC clock sources for Tegra210 currently incorrectly include pll_c2 and pll_c3. However, both of these should have been pll_mb as shown in the TRM. If Tegra210 happens to be configured such that the pll_mb is the default clock for the EMC, as configured by the bootloader, then this will cause a system hang on boot. This is because the kernel will disable the pll_mb when disabling unused clock as it appears to be unused when it is not. Also add the additional pll_p clock source for the EMC. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Acked-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Add the APB2APE audio clock on Tegra210Jon Hunter2016-02-023-0/+3
| | | | | | | | | | | | | | | | | | The APB2APE clock for the audio subsystem is required for powering up the audio power domain and accessing the various modules in this subsystem on Tegra210 devices. Add this clock for Tegra210. Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Add missing of_node_put()Amitoj Kaur Chawla2016-02-021-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for_each_child_of_node() performs an of_node_get() on each iteration, so before breaking out of the loop an of_node_put() is required. Found using Coccinelle. The semantic patch used for this is as follows: // <smpl> @@ expression e; local idexpression child; @@ for_each_child_of_node(root, child) { ... when != of_node_put(child) when != e = child ( return child; | + of_node_put(child); ? return ...; ) ... } // </smpl> Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix PLLE SS coefficientsMark Kuo2016-02-021-6/+12
| | | | | | | | | | | | | | | | | | | | The PLLE SS coefficients are different between Tegra210 and Tegra114. Add SoC generation specific versions for Tegra114 and Tegra210 and use them in their respective ->enable() callbacks. Signed-off-by: Mark Kuo <mkuo@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix typos around clearing PLLE bits during enableRhyland Klein2016-02-021-2/+2
| | | | | | | | | | | | | | | | | | | | While enabling PLLE on both Tegra114 and Tegra210, we should be clearing PLLE_MISC_VREG_BG_CTRL_MASK and PLLE_MISC_VREG_CTRL_MASK not setting them. This patch fixes both places where we incorrectly set instead of cleared those bits. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Do not disable PLLE when under hardware controlMark Kuo2016-02-021-7/+15
| | | | | | | | | | | | | | | | | | Software should not disable PLLE if PLLE is already put under hardware control. Signed-off-by: Mark Kuo <mkuo@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix pllx dyn step calculationRhyland Klein2016-02-021-5/+5
| | | | | | | | | | | | | | | | | | | | The logic for calculating the input rate used when figuring out the proper dynamic steps for pllx was incorrect. It is supposed to be calculated using parent_rate / m but it was just using the parent rate directly, therefore using the wrong step values. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: pll: Fix potential sleeping-while-atomicAndrew Bresticker2016-02-021-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Since the ->enable() callback is called with a spinlock held, we cannot call potentially blocking functions such as clk_get_rate() or clk_get_parent(), so use the unlocked versions instead. Signed-off-by: Andrew Bresticker <abrestic@chromium.org> [rklein: Adapted from ChromeOS patch, removing pllu_enable cleanup as it isn't present upstream] Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix the misnaming of nvenc from msencRhyland Klein2016-02-021-1/+1
| | | | | | | | | | | | | | | | | | | | When adding the nvenc clock, it was partially named msenc in the code. Since the msenc clock isn't present in Tegra210 and has been replaced by the nvenc clock, its misleading to see it present. Therefore, properly rename it. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix naming of MISC registersRhyland Klein2016-02-021-18/+18
| | | | | | | | | | | | | | | | | | Some register for PLLM and PLLMB were named MISC0 but according to the TRM, they have different names. Sync up the names to make it easier to understand which register they are really referring to. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Remove improper flags for lock_enableRhyland Klein2016-01-251-28/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most PLL's don't actually have LOCK_ENABLE bits. However, most PLL's also had that flag set, which meant that the clk code was trying to enable locks, and inadvertantly flipping bits in other fields. For PLLM, ensure the correct register is used for the misc_register. PLL_MISC0 contains the EN_LCKDET bit which should be used for enabling the lock, and PLLM_MISC1 shouldn't be used at all. Lastly, remove some of the settings which would point to the EN_LCKDET bits for some PLLs. There is no need to enable the locks, and that is done as part of the set_defaults logic already. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * clk: tegra: Fix divider on VI_I2CRhyland Klein2016-01-251-1/+1
| | | | | | | | | | | | | | | | VI-I2C has 16 bits available for its divider. Switch the divider width to 16 instead of 8 so correct rates can be set. Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | Merge tag 'v4.5-rockchip-clkfixes1' of ↵Stephen Boyd2016-01-302-26/+26
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-fixes Pull rockchip fixes from Heiko Stuebner: Fixes for wrong register offsets in both rk3036 and rk3368. Also rename the external input for the emac on rk3036, which should still be ok to do, as that binding was only introduced during this merge-window. * tag 'v4.5-rockchip-clkfixes1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: rk3368: fix some clock gates clk: rockchip: rk3036: rename emac ext source clock clk: rockchip: rk3036: fix the div offset for emac clock clk: rockchip: rk3036: fix uarts clock error clk: rockchip: rk3036: fix the FLAGs for clock mux
| * | clk: rockchip: rk3368: fix some clock gatesJianqun xu2016-01-161-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | Reference to the Rockchip RK3368 TRM v1.1, some clock gates need to be updated. Signed-off-by: Jianqun xu <jay.xu@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rk3036: rename emac ext source clockXing Zheng2016-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is only support rmii in the RK3036, so we should use the correct ext clock name as described in the TRM. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> [update dt-binding document as well] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rk3036: fix the div offset for emac clockXing Zheng2016-01-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Due to reference to old version TRM, there are incorrect emac clock node. The SEL_21_9 is used for the parent div, the SEL_21_4 is used for the child div. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rk3036: fix uarts clock errorXing Zheng2016-01-161-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Due to a copy-paste error the uart1 and uart2 clock div set incorrect, fix it. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
| * | clk: rockchip: rk3036: fix the FLAGs for clock muxXing Zheng2016-01-161-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | The DFLAGS are used for the clock dividers, the CLKSEL_CON flags of COMPOSITE_NODIV type should be MFLAGS. Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* | | clk: tango4: rename ARCH_TANGOX to ARCH_TANGOMarc Gonzalez2016-01-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Requested by arm-soc maintainer Kevin Hilman in v9 review. http://article.gmane.org/gmane.linux.ports.arm.kernel/456331 Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | clk: scpi: Fix checking return value of platform_device_register_simple()Axel Lin2016-01-291-1/+1
| | | | | | | | | | | | | | | | | | | | | platform_device_register_simple() returns ERR_PTR on error. Signed-off-by: Axel Lin <axel.lin@ingics.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | clk: mvebu: Mark ioremapped memory as __iomemStephen Boyd2016-01-291-1/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Silence the following sparse warning drivers/clk/mvebu/dove-divider.c:252:14: warning: incorrect type in assignment (different address spaces) drivers/clk/mvebu/dove-divider.c:252:14: expected void *base drivers/clk/mvebu/dove-divider.c:252:14: got void [noderef] <asn:2>* drivers/clk/mvebu/dove-divider.c:256:13: warning: incorrect type in argument 2 (different address spaces) drivers/clk/mvebu/dove-divider.c:256:13: expected void [noderef] <asn:2>*base drivers/clk/mvebu/dove-divider.c:256:13: got void *base drivers/clk/mvebu/dove-divider.c:257:25: warning: incorrect type in argument 1 (different address spaces) drivers/clk/mvebu/dove-divider.c:257:25: expected void volatile [noderef] <asn:2>*iomem_cookie drivers/clk/mvebu/dove-divider.c:257:25: got void *base Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | Merge tag 'armsoc-dt' of ↵Linus Torvalds2016-01-211-0/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM DT updates from Olof Johansson: "As usual, the bulk of this release is again DT file contents. There's a huge number of changes here, and it's challenging to give a crisp overview of just what is in here. To start with: New boards: - TI-based DM3730 from LogicPD (Torpedo) - Cosmic+ M4 (nommu) initial support (Freescale Vybrid) - Raspberry Pi 2 DT files - Watchdog on Meson8b - Veyron-mickey (ASUS Chromebit) DTS - Rockchip rk3228 SoC and eval board - Sigma Designs Tango4 Improvements: - Improved support for Qualcomm APQ8084, including Sony Xperia Z DT files - Misc new devices for Rockchip rk3036 and rk3288 - Allwinner updates for misc SoCs and systems ... and a _large_ number of other changes across the field. Devices added to SoC DTSI and board DTS files for a number of SoC vendors, new product boards on already-supported SoCs, cleanups and refactorings of existing DTS/DTSI files and a bunch of other changes" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (469 commits) ARM: dts: compulab: add new board description ARM: versatile: add the syscon LEDs to the DT dts: vt8500: Fix errors in SDHC node for WM8505 ARM: dts: imx6q: clean up unused ipu2grp ARM: dts: silk: Add compatible property to "partitions" node ARM: dts: gose: Add compatible property to "partitions" node ARM: dts: porter: Add compatible property to "partitions" node ARM: dts: koelsch: Add compatible property to "partitions" node ARM: dts: lager: Add compatible property to "partitions" node ARM: dts: bockw: Add compatible property to "partitions" node ARM: dts: meson8b: Add watchdog node Documentation: watchdog: Add new bindings for meson8b ARM: meson: Add status LED for Odroid-C1 ARM: dts: uniphier: fix a typo in comment block ARM: bcm2835: Add the auxiliary clocks to the device tree. ARM: bcm2835: Add devicetree for bcm2836 and Raspberry Pi 2 B ARM: bcm2835: Move the CPU/peripheral include out of common RPi DT. ARM: bcm2835: Split the DT for peripherals from the DT for the CPU ARM: realview: set up cache correctly on the PB11MPCore ARM: dts: Unify G2D device node with other devices on exynos4 ...
| * \ Merge tag 'samsung-dt-4.5-2' of ↵Arnd Bergmann2015-12-311-0/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/dt Merge "Samsung DeviceTree updates and improvements for 4.5" from Krzysztof Kozlowski: 1. eMMC/SDIO minor fixes usage of bindings on Snow and Peach Chromebooks. 2. Remove FIMD from Odroid XU3-family because on XU3 it cannot be used yet and on XU3-Lite and XU4 it is not supported. 3. Remove deprecated since June 2013 samsung,exynos5-hdmi. 4. Add support for Pseudo Random Generator on Exynos4 (Trats2 for now). This depends on new SSS clock. 5. Add rotator nodes for Exynos4 and Exynos5. 6. Switch DWC3_1 on Odroid XU3 and XU3-Lite to peripheral mode because now it cannot be used as OTG. 7. Cleanup the G2D usage on Exynos4 and add it to a proper domain in case of Exynos4210. 8. Put MDMA1 in proper domain on Exynos4210 as well. 9. Minor cleanups. * tag 'samsung-dt-4.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (21 commits) ARM: dts: Unify G2D device node with other devices on exynos4 ARM: dts: Add power domain to G2D device on exynos4210 ARM: dts: MDMA1 device belongs to LCD0 power domain on exynos4210 ARM: dts: Remove unneeded GPIO include in exynos4412-odroidu3 ARM: dts: exynos4210-universal_c210: Disable DMA for UARTs ARM: dts: Use peripheral mode for dwc3_1 on exynos5422-odroidxu3 ARM: dts: Add rotator node on exynos5420 ARM: dts: Add rotator node on exynos5250 ARM: dts: Fix power domain for sysmmu-rotator device on exynos4 ARM: dts: Add rotator nodes on exynos4 ARM: dts: Enable PRNG module on exynos4412-trats2 ARM: dts: Add PRNG module for exynos4 dt-bindings: remove deprecated compatible string from exynos-hdmi ARM: dts: Remove fimd node from exynos5422-odroidxu3-common ARM: dts: Mark eMMC as non-removable in exynos5250-snow-common ARM: dts: Remove broken-cd from eMMC node in exynos5420-peach-pi ARM: dts: Remove broken-cd from eMMC node in exynos5800-peach-pi ARM: dts: Mark SDIO as non-removable in exynos5250-snow-common ARM: dts: Mark SDIO as non-removable in exynos5420-peach-pit ARM: dts: Mark SDIO as non-removable in exynos5800-peach-pi ...
| | * | clk: samsung: exynos4: Add SSS gate clockKrzysztof Kozlowski2015-11-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a gate clock for controlling all clocks of Security Sub System (SSS). Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
| * | | Merge tag 'omap-for-v4.5/81xx-dts-signed' of ↵Arnd Bergmann2015-12-311-0/+4
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/dt Pull "reworked dts changes for ti81xx devices and minimal dra62x j5ec-evm support" from Tony Lindgren: Add minimal device tree support for dra62x also known j5eco. It is related to dm814x, just the clocks are a bit different and it has a different set of integrated devices. And let's get some basic dm814x and dra62x devices working as many of the devices are like on am33xx:: - pinctrl using the pinctrl defines as for am33xx - Updated EDMA bindings with support for using exma_xbar - MMC support for dm814x-evm, t410 and dra62x-j5eco-evm - USB support for dm814x-evm, t410 and dra62x-j5eco-evm This branch depends on an earlier omap-for-v4.5/81xx-fixes-signed branch that has dm814x dts fixes interlaced with SoC related fixes to keep things booting. The interlaced SoC and dts fixes were needed because of issues with the device tree defined clocks that just happened to work on bootloader timings for t410 earlier. * tag 'omap-for-v4.5/81xx-dts-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (21 commits) ARM: dts: Add usb support for j5-eco evm ARM: dts: Add usb support for hp t410 ARM: dts: Add usb support for dm814x-evm ARM: dts: Add usb support for dm814x and dra62x ARM: dts: Enable emmc on hp t410 ARM: dts: Add mmc support for dra62x j5-eco evm ARM: dts: Add mmc support for dm8148-evm ARM: dts: Add mmc device entries for dm814x ARM: dts: Update edma bindings on dm814x to use edma_xbar ARM: dts: Add pinctrl macros for dm814x ARM: dts: Add minimal dra62x j5-eco evm support ARM: dts: Add basic support for dra62x j5-eco SoC ARM: OMAP2+: Remove useless check for legacy booting for dm814x ARM: OMAP2+: Enable GPIO for dm814x ARM: dts: Fix dm814x pinctrl address and mask ARM: dts: Fix dm8148 control modules ranges ARM: OMAP2+: Fix timer entries for dm814x ARM: dts: Fix some mux and divider clocks to get dm814x-evm booting ARM: OMAP2+: Add DPPLS clock manager for dm814x clk: ti: Add few dm814x clock aliases ...
| * \ \ \ Merge tag 'imx-dt-4.5' of ↵Olof Johansson2015-12-227-32/+34
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt The i.MX device tree updates for 4.5: - New boards support: imx51-ts4800, imx6q-novena, CompuLab imx7d SoM/SBC, vf610m4-cosmic - Add ADC device support for imx6ul and imx7d - Remove config space from PCIe controller ranges property for i.MX6 - Add Vivante GPU nodes for i.MX6 - Add DCU, LCD, and SATA devices for LS1021A - A series to update Ventana gw5xxx boards getting HDMI and LVDS to work simultaneously and devices like PWM and SPI added - Quite a few random cleanups and minor updates * tag 'imx-dt-4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (50 commits) ARM: dts: imx7d: sbc-imx7: add basic board support ARM: dts: imx7d: cl-som-imx7: add basic module support ARM: dts: TS-4800: add touchscreen support ARM: dts: ts-4800: Add LCD support ARM: dts: imx6q: add Novena board devicetree: bindings: Add vendor prefix for Kosagi ARM: dts: TS-4800: use weim IP to map the FPGA ARM: dts: TS-4800: drop uart rts/cts pin reservations ARM: dts: imx6: add Vivante GPU nodes ARM: dts: imx28: add alternate auart4 pinmux ARM: dts: ls1021a: add sata node to dts ARM: dts: TS-4800: add basic device tree of: documentation: add bindings documentation for TS-4800 of: add vendor prefix for Technologic Systems ARM: dts: imx7d-sdb: add ADC support ARM: dts: imx7d.dtsi: add ADC support ARM: dts: vf-colibri: add CAN support ARM: mxs: dt: cfa10057: fix backlight PWM ARM: dts: imx6qdl: move GIC to right location in DT ARM: dts: imx6qdl: add IPU aliases ... Signed-off-by: Olof Johansson <olof@lixom.net>
| | * \ \ \ Merge branch 'imx/clk' into imx/dtShawn Guo2015-12-226-28/+30
| | |\ \ \ \
| * | | | | | clk: bcm: Add BCM63138 clock supportFlorian Fainelli2015-12-073-0/+33
| | |_|_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BCM63138 has a simple clocking domain which is primarily the ARMPLL clocking complex, from which the ARM (CPU), APB and AXI clocks would be derived from. Since the ARMPLL controller is entirely compatible with the iProc ARM PLL, we just initialize it without additional parameters. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
* | | | | | Merge tag 'armsoc-multiplatform' of ↵Linus Torvalds2016-01-217-57/+188
|\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC multiplatform code updates from Arnd Bergmann: "This branch is the culmination of 5 years of effort to bring the ARMv6 and ARMv7 platforms together such that they can all be enabled and boot the same kernel. It has been a tremendous amount of cleanup and refactoring by a huge number of people, and creation of several new (and major) subsystems to better abstract out all the platform details in an appropriate manner. The bulk of this branch is a large patchset from Arnd that brings several of the more minor and older platforms we have closer to multiplatform support. Among these are MMP, S3C64xx, Orion5x, mv78xx0 and realview Much of this is moving around header files from old mach directories, but there are also some cleanup patches of debug_ll (lowlevel debug per-platform options) and other parts. Linus Walleij also has some patchs to clean up the older ARM Realview platforms by finally introducing DT support, and Rob Herring has some for ARM Versatile which is now DT-only. Both of these platforms are now multiplatform. Finally, a couple of patches from Russell for Dove PMU, and a fix from Valentin Rothberg for Exynos ADC, which were rebased on top of the series to avoid conflicts" * tag 'armsoc-multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (75 commits) ARM: realview: don't select SMP_ON_UP for UP builds ARM: s3c: simplify s3c_irqwake_{e,}intallow definition ARM: s3c64xx: fix pm-debug compilation iio: exynos-adc: fix irqf_oneshot.cocci warnings ARM: realview: build realview-dt SMP support only when used ARM: realview: select apropriate targets ARM: realview: clean up header files ARM: realview: make all header files local ARM: no longer make CPU targets visible separately ARM: integrator: use explicit core module options ARM: realview: enable multiplatform ARM: make default platform work for NOMMU ARM: debug-ll: move DEBUG_LL_UART_EFM32 to correct Kconfig location ARM: defconfig: use correct debug_ll settings ARM: versatile: convert to multi-platform ARM: versatile: merge mach code into a single file ARM: versatile: switch to DT only booting and remove legacy code ARM: versatile: add DT based PCI detection ARM: pxa: mark ezx structures as __maybe_unused ARM: pxa: mark raumfeld init functions as __maybe_unused ...
| * \ \ \ \ \ Merge branch 'fixes' into next/multiplatformArnd Bergmann2015-12-171-4/+4
| |\ \ \ \ \ \ | | | |/ / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'fixes' branch contains d5d4fdd86f57 ("irqchip/versatile-fpga: Fix PCI IRQ mapping on Versatile PB") that is required for booting the versatile platform prior to the rework in this branch, but including both causes a build-time error. I'm doing an evil merge here to pull in the fixes branch so we have that commit included but at the same time revert the trivial change. This gives us a bisectable history. * fixes: (22 commits) fsl-ifc: add missing include on ARM64 ls2080a/dts: Add little endian property for GPIO IP block dt-bindings: define little-endian property for QorIQ GPIO ARM64: dts: ls2080a: fix eSDHC endianness ARM: dts: vf610: use reset values for L2 cache latencies ARM: pxa: use PWM lookup table for all machines ARM: dts: berlin: add 2nd clock for BG2Q sdhci0 and sdhci1 ARM: dts: berlin: correct BG2Q's sdhci2 2nd clock ARM: dts: am4372: fix clock source for arm twd and global timers ARM: at91: fix pinctrl driver selection ARM: at91/dt: add always-on to 1.8V regulator ARM: dts: vf610: fix clock definition for SAI2 ARM: imx: clk-vf610: fix SAI clock tree ARM: ixp4xx: fix read{b,w,l} return types irqchip/versatile-fpga: Fix PCI IRQ mapping on Versatile PB ARM: OMAP2+: enable REGULATOR_FIXED_VOLTAGE ARM: dts: add dm816x missing spi DT dma handles ARM: dts: add dm816x missing #mbox-cells cpufreq: s3c24xx: Do not mark s3c2410_plls_add as __init bus: sunxi-rsb: unlock on error in sunxi_rsb_read() ...
| * | | | | | Merge tag 'realview-base-armsoc-1-tag' of ↵Arnd Bergmann2015-12-163-36/+169
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/multiplatform Merge "Realview multiplatform support" from Linus Walleij: The board and infrastructure changes for RealView multiplatform and extended DT support. * tag 'realview-base-armsoc-1-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: realview: add an DT SMP boot method ARM: realview: select SP810 and ICST for the DT variant soc: versatile: add support for the PB11MPCore clk: versatile-icst: add device tree support clk: versatile-icst: refactor to allocate regmap separately clk: versatile-icst: convert to use regmap ARM: realview: remove private barrier implementation ARM: no longer force unbuffered DMA for realview clk/realview: stop using machine headers ARM: realview: don't map undefined PCI registers ARM: realview: remove sparsemem hack Conflicts: drivers/clk/versatile/Kconfig
| | * | | | | | clk: versatile-icst: add device tree supportLinus Walleij2015-12-151-1/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds support for the ARM syscon ICST clocks to initialized directly from the device tree syscon node on ARM Integrator, Versatile and RealView reference designs. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | | | | | clk: versatile-icst: refactor to allocate regmap separatelyLinus Walleij2015-12-151-19/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Break out the registration function so it creates a regmap and pass to the setup function, so the latter can be shared with a device tree probe function that already has a regmap. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | | | | | clk: versatile-icst: convert to use regmapLinus Walleij2015-12-152-28/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of passing around register bases, pass around a regmap in this driver. This refactoring make things so much easier when we later want to manage an ICST that is part of a syscon. Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@codeaurora.org> Cc: linux-clk@vger.kernel.org Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| | * | | | | | clk/realview: stop using machine headersArnd Bergmann2015-12-151-3/+7
| | | |/ / / / | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to move realview into multiplatform, we have to prevent device drivers from accessing the machine header files. In case of the clk driver, this is very simple, we just copy the small set of register definitions into the driver that needs them. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| * | | | | | Merge branch 'versatile/multiplatform' into next/multiplatformArnd Bergmann2015-12-151-1/+3
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge "ARM Versatile multi-platform support" from Rob Herring: Arnd lit a fire under me to dust this off and get it merged. So here it is. The main change from prior version is I merged all the code to a single file. It's a bigger patch than I'd like, but I don't think trying to do it in multiple steps is worth it. This is dependent on some solution for the default platform choice on !MMU builds (allnoconfig) as it can't be Versatile after this series. Arnd has some ideas on how to address that. This is tested under QEMU. Linus previously tested this on actual h/w and had a problem with the display identification which needs investigation or agreement to worry about it if and when someone actually cares. * versatile/multiplatform: ARM: versatile: convert to multi-platform ARM: versatile: merge mach code into a single file ARM: versatile: switch to DT only booting and remove legacy code ARM: versatile: add DT based PCI detection Acked-by: Marc Zyngier <marc.zyngier@arm.com>
| | * | | | | | ARM: versatile: switch to DT only booting and remove legacy codeRob Herring2015-12-151-1/+3
| | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With DT support for clocks, irqchips, timers, and PCI now in place, DT based booting has feature parity with non-DT legacy boot. The final piece is actually enabling common clock support on Versatile. Enabling full DT support requires either removing the old Versatile clock code, updating the legacy boot to use the common clock code, or making DT and legacy boot mutually exclusive. Given that removing legacy boot code is the goal anyway, I am going with the 1st option. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Russell King <linux@arm.linux.org.uk> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Mike Turquette <mturquette@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| * | | | | | Merge branch 'mmp/multiplatform' into next/multiplatformArnd Bergmann2015-12-153-19/+19
| |\ \ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * mmp/multiplatform: ARM: mmp: avoid unused functions ARM: mmp: move into ARCH_MULTIPLATFORM ARM: mmp: make all header files local ARM: mmp: make plat-pxa build standalone ARM: mmp: remove remaining legacy pxa-dma support ARM: mohawk: allow building with MMU disabled ARM: make xscale iwmmxt code multiplatform aware clk: mmp: stop using platform headers
| | * | | | | | clk: mmp: stop using platform headersArnd Bergmann2015-12-013-19/+19
| | |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mmp clock drivers currently hardcode the physical addresses for the clock registers. This is generally a bad idea, and it also gets in the way of multiplatform builds, which make the platform header files inaccessible to device drivers. To work around the header file problem, this patch changes the calling convention so the three mmp clock drivers get initialized with the base addresses as arguments from the platform code. It would still be useful to have a larger rework of the clock drivers, with DT integration to let the clocks actually be probed automatically, and the base addresses passed as DT properties. I am unsure if anyone is still interested in the mmp platform, so it is possible that this won't happen. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org> Cc: Chao Xie <chao.xie@marvell.com> Cc: Eric Miao <eric.y.miao@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
| * / / / / / ARM: pxa: make more mach/*.h files localArnd Bergmann2015-12-011-1/+0
| |/ / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lots of header files are never included outside of a mach-pxa directory and do not need to be made visible in include/mach, so let's just move them all down one level. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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