summaryrefslogtreecommitdiffstats
path: root/drivers (follow)
Commit message (Collapse)AuthorAgeFilesLines
* Merge tag 'drm-next-2020-12-18' of git://anongit.freedesktop.org/drm/drmLinus Torvalds2020-12-18122-1134/+2592
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull more drm updates from Daniel Vetter: "UAPI Changes: - Only enable char/agp uapi when CONFIG_DRM_LEGACY is set Cross-subsystem Changes: - vma_set_file helper to make vma->vm_file changing less brittle, acked by Andrew Core Changes: - dma-buf heaps improvements - pass full atomic modeset state to driver callbacks - shmem helpers: cached bo by default - cleanups for fbdev, fb-helpers - better docs for drm modes and SCALING_FITLER uapi - ttm: fix dma32 page pool regression Driver Changes: - multi-hop regression fixes for amdgpu, radeon, nouveau - lots of small amdgpu hw enabling fixes (display, pm, ...) - fixes for imx, mcde, meson, some panels, virtio, qxl, i915, all fairly minor - some cleanups for legacy drm/fbdev drivers" * tag 'drm-next-2020-12-18' of git://anongit.freedesktop.org/drm/drm: (117 commits) drm/qxl: don't allocate a dma_address array drm/nouveau: fix multihop when move doesn't work. drm/i915/tgl: Fix REVID macros for TGL to fetch correct stepping drm/i915: Fix mismatch between misplaced vma check and vma insert drm/i915/perf: also include Gen11 in OATAILPTR workaround Revert "drm/i915: re-order if/else ladder for hpd_irq_setup" drm/amdgpu/disply: fix documentation warnings in display manager drm/amdgpu: print mmhub client name for dimgrey_cavefish drm/amdgpu: set mode1 reset as default for dimgrey_cavefish drm/amd/display: Add get_dig_frontend implementation for DCEx drm/radeon: remove h from printk format specifier drm/amdgpu: remove h from printk format specifier drm/amdgpu: Fix spelling mistake "Heterogenous" -> "Heterogeneous" drm/amdgpu: fix regression in vbios reservation handling on headless drm/amdgpu/SRIOV: Extend VF reset request wait period drm/amdkfd: correct amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu log. drm/amd/display: Adding prototype for dccg21_update_dpp_dto() drm/amdgpu: print what method we are using for runtime pm drm/amdgpu: simplify logic in atpx resume handling drm/amdgpu: no need to call pci_ignore_hotplug for _PR3 ...
| * Merge tag 'drm-intel-next-fixes-2020-12-18' of ↵Daniel Vetter2020-12-184-20/+23
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/drm/drm-intel into drm-next drm/i915 fixes for the merge window Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/87zh2bp34m.fsf@intel.com
| | * drm/i915/tgl: Fix REVID macros for TGL to fetch correct steppingAditya Swarup2020-12-181-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix TGL REVID macros to fetch correct display/gt stepping based on SOC rev id from INTEL_REVID() macro. Previously, we were just returning the first element of the revid array instead of using the correct index based on SOC rev id. Fixes: c33298cb34f5 ("drm/i915/tgl: Fix stepping WA matching") Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201203072359.156682-1-aditya.swarup@intel.com (cherry picked from commit 83dbd74f8243f020d1ad8a3a3b3cd0795067920e) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| | * drm/i915: Fix mismatch between misplaced vma check and vma insertChris Wilson2020-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When inserting a VMA, we restrict the placement to the low 4G unless the caller opts into using the full range. This was done to allow usersapce the opportunity to transition slowly from a 32b address space, and to avoid breaking inherent 32b assumptions of some commands. However, for insert we limited ourselves to 4G-4K, but on verification we allowed the full 4G. This causes some attempts to bind a new buffer to sporadically fail with -ENOSPC, but at other times be bound successfully. commit 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page") suggests that there is a genuine problem with stateless addressing that cannot utilize the last page in 4G and so we purposefully excluded it. This means that the quick pin pass may cause us to utilize a buggy placement. Reported-by: CQ Tang <cq.tang@intel.com> Testcase: igt/gem_exec_params/larger-than-life-batch Fixes: 48ea1e32c39d ("drm/i915/gen9: Set PIN_ZONE_4G end to 4GB - 1 page") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: CQ Tang <cq.tang@intel.com> Reviewed-by: CQ Tang <cq.tang@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Cc: <stable@vger.kernel.org> # v4.5+ Link: https://patchwork.freedesktop.org/patch/msgid/20201216092951.7124-1-chris@chris-wilson.co.uk (cherry picked from commit 5f22cc0b134ab702d7f64b714e26018f7288ffee) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| | * drm/i915/perf: also include Gen11 in OATAILPTR workaroundLionel Landwerlin2020-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CI shows this workaround is also needed on Gen11. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: 059a0beb486344 ("drm/i915/perf: workaround register corruption in OATAILPTR") Reviewed-by: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201126105155.540350-1-lionel.g.landwerlin@intel.com (cherry picked from commit fa5d598b8cbab0af92bac48fd60e74a893550923) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| | * Revert "drm/i915: re-order if/else ladder for hpd_irq_setup"Chris Wilson2020-12-181-12/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We now use ilk_hpd_irq_setup for all GMCH platforms that do not have hotplug. These are early gen3 and gen2 devices that now explode on boot as they try to access non-existent registers. Fixes: 794d61a19090 ("drm/i915: re-order if/else ladder for hpd_irq_setup") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Lucas De Marchi <lucas.demarchi@intel.com> Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Jani Nikula <jani.nikula@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201127145748.29491-1-chris@chris-wilson.co.uk (cherry picked from commit e5346a1ff38a405c14ce8e595269e9b7dcfbb2e9) Signed-off-by: Jani Nikula <jani.nikula@intel.com>
| * | drm/qxl: don't allocate a dma_address arrayChristian König2020-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | That seems to be unused. Daniel: Mike reported a warning when booting with qxl, which this patch fixes: [ 1.815561] WARNING: CPU: 7 PID: 355 at drivers/gpu/drm/ttm/ttm_pool.c:365 ttm_pool_alloc+0x41b/0x540 [ttm] Signed-off-by: Christian König <christian.koenig@amd.com> Reported-by: Mike Galbraith <efault@gmx.de> Tested-by: Mike Galbraith <efault@gmx.de> References: https://lore.kernel.org/lkml/7cb43d5b-4e6a-defc-1ab6-5f713ad5a963@amd.com/ Reviewed-by: David Airlie <airlied@redhat.com> [davnet: bring commit message up to par.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20201218134243.110884-1-christian.koenig@amd.com
| * | drm/nouveau: fix multihop when move doesn't work.Dave Airlie2020-12-181-15/+16
| |/ | | | | | | | | | | | | | | | | | | | | | | As per the radeon/amdgpu fix don't use multihop if hw moves aren't enabled. Reported-by: Mike Galbraith <efault@gmx.de> Tested-by: Mike Galbraith <efault@gmx.de> Fixes: 0c8c0659d747 ("drm/nouveau/ttm: use multihop") Signed-off-by: Dave Airlie <airlied@redhat.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20201217200943.30511-1-airlied@gmail.com
| * Merge tag 'amd-drm-fixes-5.11-2020-12-16' of ↵Daniel Vetter2020-12-1658-279/+605
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-fixes-5.11-2020-12-16: amdgpu: - Fix a eDP regression for DCE asics - SMU fixes for sienna cichlid - Misc W=1 fixes - SDMA 5.2 reset fix - Suspend/resume fix - Misc display fixes - Misc runtime PM fixes and cleanups - Dimgrey Cavefish fixes - printk cleanup - Documentation warning fixes amdkfd: - Error logging fix - Fix pipe offset calculation radeon: - printk cleanup Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> From: Alex Deucher <alexdeucher@gmail.com> Link: https://patchwork.freedesktop.org/patch/msgid/20201216192421.18627-1-alexander.deucher@amd.com
| | * drm/amdgpu/disply: fix documentation warnings in display managerAlex Deucher2020-12-161-1/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add documentation for crc window. Fixes: c920888c604d ("drm/amd/display: Expose new CRC window property") Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Wayne Lin <Wayne.Lin@amd.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reviewed-by: Wayne Lin <Wayne.Lin@amd.com>
| | * drm/amdgpu: print mmhub client name for dimgrey_cavefishTao Zhou2020-12-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | This makes it easier to debug what block is causing the fault, same as sienna_cichlid. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: set mode1 reset as default for dimgrey_cavefishTao Zhou2020-12-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Use mode1 reset for dimgrey_cavefish by default. Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Add get_dig_frontend implementation for DCExRodrigo Siqueira2020-12-162-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some old ASICs might not implement/require get_dig_frontend helper; in this scenario, we can have a NULL pointer exception when we try to call it inside vbios disable operation. For example, this situation might happen when using Polaris12 with an eDP panel. This commit avoids this situation by adding a specific get_dig_frontend implementation for DCEx. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Harry Wentland <Harry.Wentland@amd.com> Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Cc: Chiawen Huang <chiawen.huang@amd.com> Reported-and-tested-by: Borislav Petkov <bp@suse.de> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
| | * drm/radeon: remove h from printk format specifierTom Rix2020-12-152-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | See Documentation/core-api/printk-formats.rst. h should no longer be used in the format specifier for printk. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: remove h from printk format specifierTom Rix2020-12-153-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | See Documentation/core-api/printk-formats.rst. h should no longer be used in the format specifier for printk. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: Fix spelling mistake "Heterogenous" -> "Heterogeneous"Colin Ian King2020-12-151-1/+1
| | | | | | | | | | | | | | | | | | | | | There is a spelling mistake in a comment in the Kconfig. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: fix regression in vbios reservation handling on headlessAlex Deucher2020-12-151-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | We need to move the check under the non-headless case, otherwise we always reserve the VGA save size. Fixes: 157fe68d74c2ad ("drm/amdgpu: fix size calculation with stolen vga memory") Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/SRIOV: Extend VF reset request wait periodJiange Zhao2020-12-154-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Virtualization case, when one VF is sending too many FLR requests, hypervisor would stop responding to this VF's request for a long period of time. This is called event guard. During this period of cooling time, guest driver should wait instead of doing other things. After this period of time, guest driver would resume reset process and return to normal. Currently, guest driver would wait 12 seconds and return fail if it doesn't get response from host. Solution: extend this waiting time in guest driver and poll response periodically. Poll happens every 6 seconds and it will last for 60 seconds. v2: change the max repetition times from number to macro. Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com> Acked-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdkfd: correct amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu log.Yifan Zhang2020-12-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | it could also be insufficient vram that makes amdgpu_amdkfd_reserve_mem_limit fail. Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Adding prototype for dccg21_update_dpp_dto()Souptick Joarder2020-12-151-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kernel test robot throws below warning -> drivers/gpu/drm/amd/amdgpu/../display/dc/dcn21/dcn21_dccg.c:46:6: warning: no previous prototype for 'dccg21_update_dpp_dto' [-Wmissing-prototypes] Adding prototype for dccg21_update_dpp_dto(). Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: print what method we are using for runtime pmAlex Deucher2020-12-151-0/+4
| | | | | | | | | | | | | | | | | | | | | So we know when it's enabled and what method we are using. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: simplify logic in atpx resume handlingAlex Deucher2020-12-151-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | Simplify the logic in the runtime resume handling for atpx Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: no need to call pci_ignore_hotplug for _PR3Alex Deucher2020-12-151-8/+1
| | | | | | | | | | | | | | | | | | | | | The platform knows it's doing d3cold. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: support runtime pm for GPUs that support BOCOAlex Deucher2020-12-151-1/+4
| | | | | | | | | | | | | | | | | | | | | Enable runtime pm on non HG/PX BOCO capable boards. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: update amdgpu_device_supports_boco()Alex Deucher2020-12-151-2/+2
| | | | | | | | | | | | | | | | | | | | | Change it to check if the device has ACPI power resources. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: add check for ACPI power resourcesAlex Deucher2020-12-152-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | Check if the device has ACPI power resources so we can enable runtime pm if so. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: split BOCO and ATPX handlingAlex Deucher2020-12-154-14/+42
| | | | | | | | | | | | | | | | | | | | | | | | In preparation for systems that support d3cold on dGPUs independent of PX/HG. No functional change intended. Acked-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Fixed kernel test robot warningSouptick Joarder2020-12-151-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kernel test robot throws below warning -> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5349:5: warning: no previous prototype for 'amdgpu_dm_crtc_atomic_set_property' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5349:5: warning: no previous prototype for function 'amdgpu_dm_crtc_atomic_set_property' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5373:5: warning: no previous prototype for 'amdgpu_dm_crtc_atomic_get_property' [-Wmissing-prototypes] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:5373:5: warning: no previous prototype for function 'amdgpu_dm_crtc_atomic_get_property' [-Wmissing-prototypes] As these functions are only used inside amdgpu_dm.c, these can be made static. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: 3.2.116Aric Cyr2020-12-151-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: [FW Promotion] Release 0.0.46Anthony Koo2020-12-151-25/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add new aux_channel_type - Changed port_index to instance in dmub_cmd_dp_aux_control_data - Change aux_return_code_type to sync up with driver - param for ramping abm based on backlight level Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Fix cleanup typo in MPCC visual confirmAric Cyr2020-12-151-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Typo in MPCC visual confirmation. [How] Fix to correct values. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Fix OGAM LUT calculation precisionFelipe2020-12-151-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] The OGAM LUT precision was accumulating too much error in the higher end. [How] Instead of calculating all points of the LUT in relation to the previous ones, perform a full calculation in one of the intermediate segments to stop error propagation. Signed-off-by: Felipe Clark <Felipe.Clark@amd.com> Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Only update FP2 for full updatesAric Cyr2020-12-152-11/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] FP2 is not double buffered and must wait for VACTIVE before programming. [How] Only update when there is a full update we should change FP2 to avoid delay every flip. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: updated wm table for RenoirJake Wang2020-12-151-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] For certain timings, Renoir may underflow due to sr exit latency being too slow. [How] Updated wm table for renoir. Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: delay fp2 programming until vactive before lockMartin Leung2020-12-155-18/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] race condition of programming FP2 wrt pipe locking and vactive state can cause underflow/black screen [How] Enforce the FP2 is only programmed during vactive, and unlock pipe soon afterwards. Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Add DP info frame update for dcn30Leo (Hanghong) Ma2020-12-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] We are missing the DP info frame update on dcn30, and this will lead to DP SDPs not being sent; [How] Add the DP info frame update for dcn30; Signed-off-by: Leo (Hanghong) Ma <hanghong.ma@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: add dcn30_link_encoder_validate_output_with_stream to headerEric Bernstein2020-12-153-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] dcn30_link_encoder_validate_output_with_stream was a static function. [How] remove the static define and include it in the header. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Fix to be able to stop crc calculationWayne Lin2020-12-151-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Find out when we try to disable CRC calculation, crc generation is still enabled. Main reason is that dc_stream_configure_crc() will never get called when the source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE. [How] Add checking condition that when source is AMDGPU_DM_PIPE_CRC_SOURCE_NONE, we should also call dc_stream_configure_crc() to disable crc calculation. Also, clean up crc window when disable crc calculation. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: HP Reverb G2 VR fails to light upAric Cyr2020-12-153-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] Many VR headsets require a HSYNC width of 4, but DCN has default minimum of 8. [How] Change the arbitrary minimum HSYNC width to 4 to match DCN20. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Add missing DP_SEC register definitions and masksMax Tseng2020-12-152-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] some DP_SEC register defs and masks are missing. [How] add the missing defs and masks. Signed-off-by: Max Tseng <chuan-yu.tseng@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: Change pstate expected timeout warning to 180us on linuxVictor Lu2020-12-151-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [Why] There is a warning that triggers when pstate takes too long. Pstate can take up to ~200us on Linux without hanging but it is currently set to 40us. [How] Change the timeout for the warning to be 180us on Linux. Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Roman Li <Roman.Li@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: skip load smu and sdma microcode on sriov for SIENNA_CICHLIDStanley.Yang2020-12-153-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | skip load smu and sdma fw on sriov due to sos, ta and asd fw have been skipped for SIENNA_CICHLID. V2: move asic check into smu11 Signed-off-by: Stanley.Yang <Stanley.Yang@amd.com> Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/display: drop retired CONFIG_DRM_AMD_DC_DCN3_0Flora Cui2020-12-151-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_DRM_AMD_DC_DCN3_0 is retired. drop it Signed-off-by: Flora Cui <flora.cui@amd.com> Reviewed-by: Guchun Chen <guchun.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu: add judgement for suspend/resume sequenceLikun Gao2020-12-153-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | S0ix only makes sense on APUs since they are part of the platform, so only when the ASIC is APU should set amdgpu_acpi_is_s0ix_supported flag to deal with the related situation. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amdgpu/sdma5.2: soft reset sdma blocks before setup and start sdmaXiaomeng Hou2020-12-151-7/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without doing the soft reset, register mmSDMA0_GFX_RB_WPTR's value could not be reset to 0 when sdma block resumes. That would cause the ring buffer's read and write pointers not equal and ring test fail. So add the soft reset step. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/pm: add deep sleep control for uclk and fclkEvan Quan2020-12-151-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | These are supported by Sienna Cichlid and should be taken into consideration during DS control. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/pm: update the data strucutre for SMU metrics exchangeEvan Quan2020-12-151-36/+39
| | | | | | | | | | | | | | | | | | | | | | | | This is needed for Sienna Cichlid. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/pm: correct the data structure for activity monitor coeff exchangeEvan Quan2020-12-151-60/+65
| | | | | | | | | | | | | | | | | | | | | | | | This is needed for Sienna Cichlid. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/pm: fulfill the sienna cichlid UMD PSTATE profiling clocksEvan Quan2020-12-152-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | Fulfill the UMD PSTATE profiling clocks of sienna cichlid. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
| | * drm/amd/pm: inform SMU RLC status thus enable/disable DPM feature for vangoghXiaomeng Hou2020-12-102-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RLC is halted when system suspend/shutdown. However, due to DPM enabled, PMFW is unaware of RLC being halted and will continue sending messages, which would eventually cause an ACPI hang. Use the system_feature_control interface to notify SMU the status of RLC (Normal/OFF) thus enable/disable DPM feature. Signed-off-by: Xiaomeng Hou <Xiaomeng.Hou@amd.com> Reviewed-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Lazar Lijo <Lijo.Lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-21 11:45:14 +0100