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* irqchip: GICv3: ITS: device allocation and configurationMarc Zyngier2014-11-261-0/+74
| | | | | | | | | | | | | The ITS has a notion of "device" that can write to it in order to generate an interrupt. Conversly, the driver maintains a per-ITS list of devices, together with their configuration information, and uses this to configure the HW. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-9-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: GICv3: ITS: tables allocatorsMarc Zyngier2014-11-261-0/+292
| | | | | | | | | | | | | The interrupt translation is driven by a set of tables (device, ITT, and collection) to be in the end delivered to a CPU. Also, the redistributors rely on a couple of tables (configuration, and pending) to deliver the interrupts to the CPUs. This patch adds the required allocators for these tables. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-8-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: GICv3: ITS: LPI allocatorMarc Zyngier2014-11-261-0/+103
| | | | | | | | | | LPIs are the type of interrupts that are used by the ITS. Given the size of the namespace (anywhere between 16 and 32bit), interrupt IDs are allocated in chunks of 32. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-7-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: GICv3: ITS: irqchip implementationMarc Zyngier2014-11-261-0/+77
| | | | | | | | | The usual methods that are used to present an irqchip to the rest of the kernel Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-6-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: GICv3: ITS command queueMarc Zyngier2014-11-261-0/+511
| | | | | | | | | | | | The ITS is configured through a number commands that the driver issues to the HW using a memory-based circular buffer. This patch implements the subset of commands that are required for Linux. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-5-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: GICv3: rework redistributor structureMarc Zyngier2014-11-261-29/+44
| | | | | | | | | | | | | The basic GICv3 driver has almost no use for the redistributor (other than the basic per-CPU interrupts), but the ITS needs a lot more from them. As such, rework the set of data structures. The behaviour of the GICv3 driver is otherwise unaffected. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-4-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip: GICv3: Convert to domain hierarchyMarc Zyngier2014-11-262-5/+38
| | | | | | | | | | In order to start supporting stacked domains, convert the GICv3 code base to the new domain hierarchy framework, which mostly amounts to supporting the new alloc/free callbacks. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Link: https://lkml.kernel.org/r/1416839720-18400-3-git-send-email-marc.zyngier@arm.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* PCI/MSI: Allow an msi_controller to be associated to an irq domainMarc Zyngier2014-11-231-2/+14
| | | | | | | | | | | | | | | | | | | | | With the new stacked irq domains, it becomes pretty tempting to allocate an MSI domain per PCI bus, which would remove the requirement of either relying on arch-specific code, or a default PCI MSI domain. By allowing the msi_controller structure to carry a pointer to an irq_domain, we can easily use this in pci_msi_setup_msi_irqs. The existing code can still be used as a fallback if the MSI driver does not populate the domain field. Tested on arm64 with the GICv3 ITS driver. Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Jiang Liu <jiang.liu@linux.intel.com> Link: http://lkml.kernel.org/r/1416048553-29289-2-git-send-email-marc.zyngier@arm.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI/MSI: Provide mechanism to alloc/free MSI/MSIX interrupt from irqdomainJiang Liu2014-11-231-3/+64
| | | | | | | | | | | | | | | | | | | | | | | | | Provide mechanism to directly alloc/free MSI/MSIX interrupt from irqdomain, which will be used to replace arch_setup_msi_irq()/ arch_setup_msi_irqs()/arch_teardown_msi_irq()/arch_teardown_msi_irqs(). To kill weak functions, this patch introduce a new weak function arch_get_pci_msi_domain(), which is to retrieve the MSI irqdomain for a PCI device. This weak function could be killed once we get a common way to associate MSI domain with PCI device. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Tony Luck <tony.luck@intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yijing Wang <wangyijing@huawei.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Matthias Brugger <matthias.bgg@gmail.com> Cc: Alexander Gordeev <agordeev@redhat.com> Link: http://lkml.kernel.org/r/1416061447-9472-10-git-send-email-jiang.liu@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI/MSI: Enhance core to support hierarchy irqdomainJiang Liu2014-11-232-0/+173
| | | | | | | | | | | | | | | Enhance PCI MSI core to support hierarchy irqdomain, so the common code can be shared across architectures. [ tglx: Extracted and combined from several patches ] Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI/MSI: Move cached entry functions to irq coreJiang Liu2014-11-232-18/+1
| | | | | | | | | Required to support non PCI based MSI. [ tglx: Extracted from Jiangs patch series ] Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI/MSI: Rename mask/unmask_msi_irq treewideThomas Gleixner2014-11-236-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | The PCI/MSI irq chip callbacks mask/unmask_msi_irq have been renamed to pci_msi_mask/unmask_irq to mark them PCI specific. Rename all usage sites. The conversion helper functions are kept around to avoid conflicts in next and will be removed after merging into mainline. Coccinelle assisted conversion. No functional change. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Heiko Carstens <heiko.carstens@de.ibm.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Chris Metcalf <cmetcalf@tilera.com> Cc: x86@kernel.org Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Murali Karicheri <m-karicheri2@ti.com> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Mohit Kumar <mohit.kumar@st.com> Cc: Simon Horman <horms@verge.net.au> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Yijing Wang <wangyijing@huawei.com>
* PCI/MSI: Rename mask/unmask_msi_irq et alThomas Gleixner2014-11-231-8/+16
| | | | | | | | | | | | | | | | | | | | | mask/unmask_msi_irq and __mask_msi/msix_irq are PCI/MSI specific functions and should be named accordingly. This is a preparatory patch to support MSI on non PCI devices. Rename mask/unmask_msi_irq to pci_msi_mask/unmask_irq and document the functions. Provide conversion helpers. Rename __mask_msi/msix_irq to __pci_msi/msix_desc_mask so its clear that they operated on msi_desc. Fixup the only user outside of pci/msi. Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Jiang Liu <jiang.liu@linux.intel.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yijing Wang <wangyijing@huawei.com> Cc: Heiko Carstens <heiko.carstens@de.ibm.com>
* PCI/MSI: Rename write_msi_msg() to pci_write_msi_msg()Jiang Liu2014-11-237-11/+11
| | | | | | | | | | | | | Rename write_msi_msg() to pci_write_msi_msg() to mark it as PCI specific. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI/MSI: Rename __read_msi_msg() to __pci_read_msi_msg()Jiang Liu2014-11-231-8/+1
| | | | | | | | | | | | | | Rename __read_msi_msg() to __pci_read_msi_msg() and kill unused read_msi_msg(). It's a preparation to separate generic MSI code from PCI core. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI/MSI: Kill redundant call of irq_set_msi_desc() for MSI-X interruptsJiang Liu2014-11-231-1/+0
| | | | | | | | | | | | | | | It is the repsonsibility of arch_setup_msi_irq()/arch_setup_msi_irqs() to call irq_set_msi_desc() to associate IRQ descriptors and MSI descriptors. Kill the redundant call of irq_set_msi_desc() for MSI-X interrupts in the PCI MSI core. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI/MSI: Simplify PCI MSI code by initializing msi_desc.nvec_used earlierJiang Liu2014-11-232-33/+15
| | | | | | | | | | | | | | | | | Simplify PCI MSI code by initializing msi_desc.nvec_used and msi_desc.msi_attrib.multiple when creating MSI descriptors. Also remove redundant checks in IRQ remapping drivers, PCI MSI core already guarantees these. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI/MSI: Remove unnecessary braces around single statementsJiang Liu2014-11-231-6/+3
| | | | | | | | | | | | | Per Documentation/CodingStyle, don't use braces around single statements. Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Yingjoe Chen <yingjoe.chen@mediatek.com> Cc: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* PCI: xilinx: Save MSI controller in pci_sys_dataYijing Wang2014-11-211-15/+5
| | | | | | | | Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). [bhelgaas: use xilinx_pcie_msi_chip, not xilinx_pcie_msi_controller] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: mvebu: Save MSI controller in pci_sys_dataYijing Wang2014-11-211-7/+4
| | | | | | | Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: rcar: Save MSI controller in pci_sys_dataYijing Wang2014-11-211-10/+3
| | | | | | | | Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). [bhelgaas: use struct rcar_msi.chip, not ctrl] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: designware: Save MSI controller in pci_sys_dataYijing Wang2014-11-211-11/+5
| | | | | | | | Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). [bhelgaas: use dw_pcie_msi_chip, not dw_pcie_msi_controller] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: tegra: Save MSI controller in pci_sys_dataYijing Wang2014-11-211-10/+4
| | | | | | | | Save MSI controller in pci_sys_data instead of assigning MSI controller pointer to every PCI bus in .add_bus(). [bhelgaas: use struct tegra_msi.chip, not ctrl] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI/MSI: Add weak pcibios_msi_controller()Yijing Wang2014-11-121-1/+16
| | | | | | | | | | Add pcibios_msi_controller() to get the msi_controller associated with a PCI device. This is to allow arches to store the msi_controller in the arch-specific PCI sysdata. [bhelgaas: changelog, take pci_dev instead of pci_bus] Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI/MSI: Rename "struct msi_chip" to "struct msi_controller"Yijing Wang2014-11-1211-28/+30
| | | | | | | | | | | | "msi_chip" isn't very descriptive, so rename it to "msi_controller". That tells a little more about what it does and is already used in device tree bindings. No functional change. [bhelgaas: changelog, change *only* the struct name so it's reviewable] Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* Revert "PCI: Add x86_msi.msi_mask_irq() and msix_mask_irq()"Yijing Wang2014-11-111-16/+6
| | | | | | | | | | | | | | | | | | | The problem fixed by 0e4ccb1505a9 ("PCI: Add x86_msi.msi_mask_irq() and msix_mask_irq()") has been fixed in a simpler way by a previous commit ("PCI/MSI: Add pci_msi_ignore_mask to prevent writes to MSI/MSI-X Mask Bits"). The msi_mask_irq() and msix_mask_irq() x86_msi_ops added by 0e4ccb1505a9 are no longer needed, so revert the commit. default_msi_mask_irq() and default_msix_mask_irq() were added by 0e4ccb1505a9 and are still used by s390, so keep them for now. [bhelgaas: changelog] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: David Vrabel <david.vrabel@citrix.com> CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> CC: xen-devel@lists.xenproject.org
* PCI/MSI: Add pci_msi_ignore_mask to prevent writes to MSI/MSI-X Mask BitsYijing Wang2014-11-071-1/+6
| | | | | | | | | | | | | | | | | | | | | | MSI-X vector Mask Bits are in MSI-X Tables in PCI memory space. Xen PV guests can't write to those tables. MSI vector Mask Bits are in PCI configuration space. Xen PV guests can write to config space, but those writes are ignored. Commit 0e4ccb1505a9 ("PCI: Add x86_msi.msi_mask_irq() and msix_mask_irq()") added a way to override default_mask_msi_irqs() and default_mask_msix_irqs() so they can be no-ops in Xen guests, but this is more complicated than necessary. Add "pci_msi_ignore_mask" in the core PCI MSI code. If set, default_mask_msi_irqs() and default_mask_msix_irqs() return without doing anything. This is less flexible, but much simpler. [bhelgaas: changelog] Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: David Vrabel <david.vrabel@citrix.com> CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com> CC: xen-devel@lists.xenproject.org
* Merge tag 'ntb-3.18' of git://github.com/jonmason/ntbLinus Torvalds2014-10-193-123/+501
|\ | | | | | | | | | | | | | | | | | | | | | | | | Pull ntb (non-transparent bridge) updates from Jon Mason: "Add support for Haswell NTB split BARs, a debugfs entry for basic debugging info, and some code clean-ups" * tag 'ntb-3.18' of git://github.com/jonmason/ntb: ntb: Adding split BAR support for Haswell platforms ntb: use errata flag set via DID to implement workaround ntb: conslidate reading of PPD to move platform detection earlier ntb: move platform detection to separate function NTB: debugfs device entry
| * ntb: Adding split BAR support for Haswell platformsDave Jiang2014-10-173-60/+210
| | | | | | | | | | | | | | | | | | On the Haswell platform, a split BAR option to allow creation of 2 32bit BARs (4 and 5) from the 64bit BAR 4. Adding support for this new option. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * ntb: use errata flag set via DID to implement workaroundDave Jiang2014-10-172-9/+42
| | | | | | | | | | | | | | | | | | Instead of using a module parameter, we should detect the errata via PCI DID and then set an appropriate flag. This will be used for additional errata later on. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * ntb: conslidate reading of PPD to move platform detection earlierDave Jiang2014-10-171-28/+98
| | | | | | | | | | | | | | | | To simplify some of the platform detection code. Move the platform detection to a function to be called earlier. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * ntb: move platform detection to separate functionDave Jiang2014-10-171-27/+47
| | | | | | | | | | | | | | | | Move the platform detection function to separate functions to allow easier maintenence. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * NTB: debugfs device entryJon Mason2014-10-173-2/+107
| | | | | | | | | | | | | | Create a debugfs entry for the NTB device to log the basic device info, as well as display the error count on a number of registers. Signed-off-by: Jon Mason <jon.mason@intel.com>
* | Merge branch 'i2c/for-next' of ↵Linus Torvalds2014-10-1913-48/+1326
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux Pull i2c updates from Wolfram Sang: "Highlights from the I2C subsystem for 3.18: - new drivers for Axxia AM55xx, and Hisilicon hix5hd2 SoC. - designware driver gained AMD support, exynos gained exynos7 support The rest is usual driver stuff. Hopefully no lowlights this time" * 'i2c/for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux: i2c: i801: Add Device IDs for Intel Sunrise Point PCH i2c: hix5hd2: add i2c controller driver i2c-imx: Disable the clock on probe failure i2c: designware: Add support for AMD I2C controller i2c: designware: Rework probe() to get clock a bit later i2c: designware: Default to fast mode in case of ACPI i2c: axxia: Add I2C driver for AXM55xx i2c: exynos: add support for HSI2C module on Exynos7 i2c: mxs: detect No Slave Ack on SELECT in PIO mode i2c: cros_ec: Remove EC_I2C_FLAG_10BIT i2c: cros-ec-tunnel: Add of match table i2c: rcar: remove sign-compare flaw i2c: ismt: Use minimum descriptor size i2c: imx: Add arbitration lost check i2c: rk3x: Remove unlikely() annotations i2c: rcar: check for no IRQ in rcar_i2c_irq() i2c: rcar: make rcar_i2c_prepare_msg() *void* i2c: rcar: simplify check for last message i2c: designware: add support of platform data to set I2C mode i2c: designware: add support of I2C standard mode
| * | i2c: i801: Add Device IDs for Intel Sunrise Point PCHjames.d.ralston@intel.com2014-10-162-0/+4
| | | | | | | | | | | | | | | | | | | | | This patch adds the I2C/SMBus Device IDs for the Intel Sunrise Point PCH. Signed-off-by: James Ralston <james.d.ralston@intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: hix5hd2: add i2c controller driverWei Yan2014-10-163-0/+568
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I2C drivers for hix5hd2 soc series, including following chipset Hi3716CV200, Hi3719CV100, Hi3718CV100, Hi3719MV100, Hi3718MV100. Signed-off-by: Wei Yan <sledge.yanwei@huawei.com> Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org> [wsa: folded dt docs into this patch] Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c-imx: Disable the clock on probe failureFabio Estevam2014-10-061-2/+6
| | | | | | | | | | | | | | | | | | | | | In the case of errors during probe, we should disable i2c_imx->clk. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: designware: Add support for AMD I2C controllerCarl Peng2014-10-062-0/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for AMD version of the DW I2C host controller. The device is enumerated from ACPI namespace with ACPI ID AMD0010. Because the core driver needs an input source clock, and this is not an Intel LPSS device where clocks are provided through drivers/acpi/acpi_lpss.c, we register the clock ourselves if the clock rate is given in ->driver_data Signed-off-by: Carl Peng <carlpeng008@gmail.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: designware: Rework probe() to get clock a bit laterMika Westerberg2014-10-061-20/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to be able to create missing clock for AMD (and in future possibly others) we move getting clock for the device a bit later. Also make ACPI/DT configuration in the same place depending on from where the device was enumerated from. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: designware: Default to fast mode in case of ACPIMika Westerberg2014-10-061-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no way in ACPI to tell in which speed the host controller is supposed to run, so we default to fast mode (400KHz). Since this has been the default all the time there should be no functional changes with this change. This is the first step required to refactor the driver probe so that we can supply source clock from ACPI part of the driver to the core. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: axxia: Add I2C driver for AXM55xxAnders Berg2014-10-033-0/+571
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add I2C bus driver for the controller found in the LSI Axxia family SoCs. The driver implements 10-bit addressing and SMBus transfer modes via emulation (including SMBus block data read). Signed-off-by: Anders Berg <anders.berg@avagotech.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: exynos: add support for HSI2C module on Exynos7Naveen Krishna Ch2014-10-032-7/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The HSI2C module on Exynos7 differs in the transfer status bits. Transfer status bits were moved to INT_ENABLE and INT_STATUS registers This patch adds support for the HSI2C module on Exynos7. 1. Implementes a "hw" field in the variant struct to distinguish the hardware. 2. Updates the dt-new compatible in dt-binding documenation Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: mxs: detect No Slave Ack on SELECT in PIO modeJanusz Użycki2014-10-031-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | i2cdetect scanned i2c bus slow because the i2c-mxs driver ignored the NO_SLAVE_ACK bit during busy-waiting loop. Thanks to the patch, the speedup happens. Signed-off-by: Janusz Uzycki <j.uzycki@elproma.com.pl> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: cros_ec: Remove EC_I2C_FLAG_10BITDoug Anderson2014-09-301-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In <https://lkml.org/lkml/2014/6/10/265> pointed out that the 10-bit flag in the cros_ec_tunnel was useless. It went into a 16-bit flags field but was defined at (1 << 16). Since we have no 10-bit i2c devices on the other side of the tunnel on any known devices this was never a problem. Until we do it makes sense to remove this code. On the EC side the code to handle this flag was removed in <https://chromium-review.googlesource.com/204162>. Reported-by: Dave Jones <davej@redhat.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: cros-ec-tunnel: Add of match tableSjoerd Simons2014-09-291-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To enable the cros-ec-tunnel driver to be auto-loaded when build as a module add an of match table (and export it) to match the modalias information passed on to userspace as the Cros EC MFD driver registers the MFD subdevices with an of_compatibility string. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: rcar: remove sign-compare flawWolfram Sang2014-09-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gcc rightfully says: drivers/i2c/busses/i2c-rcar.c:198:10: warning: comparison between signed and unsigned integer expressions [-Wsign-compare] Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: ismt: Use minimum descriptor sizeFan Du2014-09-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Software is allowed to allocate number of descriptor size from 2 to 256, this i2c controller could process more descriptor, but for i2c core soft ware layer, only one i2c transaction is allowed each time. So here switch to minimum 2 descriptor when initialization. Signed-off-by: Fan Du <fan.du@intel.com> Acked-by: Neil Horman <nhorman@tuxdriver.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: imx: Add arbitration lost checkHaibo Chen2014-09-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the i.mx spec, for multimaster mode, if I2C is enabled when the bus is busy and asserts start, hardware inhibits the transmission, clears MSTA without signaling a stop, generate an interrupt, and set I2C_I2SR[IAL] to indicate a failed attempt to engage the bus, which means arbitration lost. In this case, we should first test I2C_I2SR[IAL], and clear this bit if it is set, and then I2C controller default to slave receive mode. This patch check the IAL bit every time before an I2c transmission. if IAL is set, clear it and make I2C controller to default mode. Signed-off-by: Haibo Chen <haibo.chen@freescale.com> Acked-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: rk3x: Remove unlikely() annotationsDoug Anderson2014-09-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having a transfer more than 32 bits is not all that unlikely. Remove the annotation. The unlikely in the IRQ handler can't gain us much. It's not in a loop, so at most it would save 1 instruction per IRQ, which isn't much. In fact on the compiler I tested it produced the exact same code. Remove it too. Suggested-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Signed-off-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| * | i2c: rcar: check for no IRQ in rcar_i2c_irq()Sergei Shtylyov2014-09-291-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Check if the ICMSR register (masked with the ICMIER register) evaluates to 0 in the driver's interrupt handler and return IRQ_NONE in that case, like many other drivers do. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-30 07:35:16 +0100