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2011-09-20drm/nvd0/disp: dac load detectBen Skeggs1-1/+16
2011-09-20drm/nvd0/disp: handle sync polarity, kill off some unknownBen Skeggs1-6/+10
2011-09-20drm/nvd0/disp: scalingBen Skeggs1-5/+32
2011-09-20drm/nvd0/disp: push the update button in mode_set_base()Ben Skeggs1-0/+4
2011-09-20drm/nvd0/disp: fixup clut so it actually worksBen Skeggs1-4/+6
2011-09-20drm/nvd0/disp: initial attempt at modeset irq handlingBen Skeggs1-0/+130
2011-09-20drm/nvd0/disp: stub dac load detect, prevents oopsBen Skeggs1-0/+7
2011-09-20drm/nvd0/disp: dac encoder moduleBen Skeggs1-0/+137
2011-09-20drm/nvd0/disp: extend the init voodoo to cover crtcsBen Skeggs1-19/+27
2011-09-20drm/nvd0/disp: remove lp reordering from vram dmaobj, create fb dmaobjsBen Skeggs1-5/+22
2011-09-20drm/nvd0/disp: some magic to make evo happeirBen Skeggs1-0/+12
2011-09-20drm/nvd0/disp: they moved the linear flag..Ben Skeggs1-3/+6
2011-09-20drm/nvd0/disp: initial crtc object implementationBen Skeggs1-1/+456
2011-09-20drm/nvd0/disp: skeletal handling of modeset interruptsBen Skeggs1-0/+60
2011-09-20drm/nvd0/disp: start on SOR encoder functionsBen Skeggs1-1/+202
2011-09-20drm/nvd0/disp: setup a couple of dma objects we'll needBen Skeggs1-2/+41
2011-09-20drm/nvd0/disp: start on interrupt handlingBen Skeggs1-0/+42
2011-09-20drm/nvd0/disp: whip up some basic dma handling for the evo channelsBen Skeggs1-3/+65
2011-09-20drm/nvd0/disp: very initial evo setupBen Skeggs4-3/+179
2011-09-20drm/nouveau/bios: allow passing in crtc to the init table parserBen Skeggs6-36/+41
2011-09-20drm/nvd0/pm: enable clock/voltage hooksBen Skeggs1-0/+3
2011-09-20drm/nouveau/bios: fix INIT_GPIO for new chipsetsBen Skeggs1-22/+51
2011-09-20drm/nvd0/gpio: initial implementationBen Skeggs4-4/+48
2011-09-20drm/nvd0/i2c: initial implementationBen Skeggs1-16/+35
2011-09-20drm/nouveau: initial chipset description for nvdX chipsetsBen Skeggs1-2/+46
2011-09-20drm/nouveau: allow modeset module option to select 'headless mode'Ben Skeggs3-1/+11
2011-09-20drm/nouveau: fixup init/fini sequence to deal with no CRTCsBen Skeggs2-38/+30
2011-09-20drm/nouveau: make general drm modesetting init commonBen Skeggs8-67/+32
2011-09-20drm/nvd0: add a card_type for 0xdX chipsetsBen Skeggs4-3/+4
2011-09-20drm/nv04/pm: recalibrate timer on nvclk changesMartin Peres1-0/+4
2011-09-20drm/nouveau/tmr: calibrate for ns timestamps on initBen Skeggs1-26/+82
2011-09-20drm/nvc0/gr: unblacklist nvcf accelerationBen Skeggs1-1/+0
2011-09-20drm/nouveau: don't complain for disabled timingset entriesBen Skeggs1-1/+2
2011-09-20drm/nvc0/gr: copy GPC mpart config from PFFBBen Skeggs1-1/+1
2011-09-20drm/nvc0/vram: support non-uniform memory size per controllerBen Skeggs1-5/+43
2011-09-20drm/nvc0/gr: add support for nvcf chipsetBen Skeggs8-24/+44
2011-09-20drm/nouveau: allow a nouveau_mm to be created with holesBen Skeggs2-20/+28
2011-09-20drm/nouveau: embed nouveau_mmBen Skeggs7-61/+51
2011-09-20drm/nv31/mpeg: support for a single class3174 userBen Skeggs2-4/+40
2011-09-20drm/nouveau: rename nv40_mpeg to nv31_mpegBen Skeggs4-29/+29
2011-09-20drm/nvc0/pm: more complete parsing of clock domainsBen Skeggs4-19/+31
2011-09-20drm/nvc0/pm: initial implementation of clocks_get()Ben Skeggs4-1/+150
2011-09-20drm/nva3/pm: idle graphics engine before changing clocksBen Skeggs1-0/+40
2011-09-20drm/nouveau: add function to wait until a callback returns trueBen Skeggs2-0/+21
2011-09-20drm/nv50/gr: insert set/clr of a ctxprog flag at start/end of ctxprogBen Skeggs1-0/+6
2011-09-20drm/nva3/pm: tidy and add some comments here and thereBen Skeggs1-47/+78
2011-09-20drm/nva3/pm: parse/reclock vdec/41a0 clocksBen Skeggs3-0/+26
2011-09-20drm/nva3/pm: rewrite clock_set, and switch to new interfacesBen Skeggs3-143/+147
2011-09-20drm/nouveau/pm: add hooks to get/set *all* clocks at onceBen Skeggs2-0/+16
2011-09-20drm/nva3/pm: rewrite clock readback functions, far more correct nowBen Skeggs1-33/+62