From b52fb259dff8d0da76d38005464edf4201b01d76 Mon Sep 17 00:00:00 2001 From: Ulf Hansson Date: Fri, 29 May 2020 12:23:41 +0200 Subject: mmc: core: Always allow the card detect uevent to be consumed The approach to allow userspace ~5s to consume the uevent, which is triggered when a new card is inserted/initialized, currently requires the mmc host to support system wakeup. This is unnecessary limiting, especially for an mmc host that relies on a GPIO IRQ for card detect. More precisely, the mmc host may not support system wakeup for its corresponding struct device, while the GPIO IRQ still could be configured as a wakeup IRQ via enable_irq_wake(). To support all various cases, let's simply drop the need for the wakeup support. Instead let's always register a wakeup source and activate it for all card detect IRQs by calling __pm_wakeup_event(). Signed-off-by: Ulf Hansson Link: https://lore.kernel.org/r/20200529102341.12529-1-ulf.hansson@linaro.org --- drivers/mmc/core/core.c | 10 +++++----- drivers/mmc/core/host.c | 3 +++ include/linux/mmc/host.h | 1 + 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index 8d2b808e9b58..aff3fa937674 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -1455,12 +1455,12 @@ void mmc_detach_bus(struct mmc_host *host) void _mmc_detect_change(struct mmc_host *host, unsigned long delay, bool cd_irq) { /* - * If the device is configured as wakeup, we prevent a new sleep for - * 5 s to give provision for user space to consume the event. + * Prevent system sleep for 5s to allow user space to consume the + * corresponding uevent. This is especially useful, when CD irq is used + * as a system wakeup, but doesn't hurt in other cases. */ - if (cd_irq && !(host->caps & MMC_CAP_NEEDS_POLL) && - device_can_wakeup(mmc_dev(host))) - pm_wakeup_event(mmc_dev(host), 5000); + if (cd_irq && !(host->caps & MMC_CAP_NEEDS_POLL)) + __pm_wakeup_event(host->ws, 5000); host->detect_change = 1; mmc_schedule_delayed_work(&host->detect, delay); diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index c8768726d925..6141a85749ca 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,7 @@ static DEFINE_IDA(mmc_host_ida); static void mmc_host_classdev_release(struct device *dev) { struct mmc_host *host = cls_dev_to_mmc_host(dev); + wakeup_source_unregister(host->ws); ida_simple_remove(&mmc_host_ida, host->index); kfree(host); } @@ -400,6 +402,7 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev) host->index = err; dev_set_name(&host->class_dev, "mmc%d", host->index); + host->ws = wakeup_source_register(NULL, dev_name(&host->class_dev)); host->parent = dev; host->class_dev.parent = dev; diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 7149bab555d7..1fa4fa1caef5 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -287,6 +287,7 @@ struct mmc_host { #ifdef CONFIG_PM_SLEEP struct notifier_block pm_notify; #endif + struct wakeup_source *ws; /* Enable consume of uevents */ u32 max_current_330; u32 max_current_300; u32 max_current_180; -- cgit v1.2.3 From b4fc8278d252288610d6160afb3df125c0514da3 Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Tue, 9 Jun 2020 14:07:25 +0530 Subject: mmc: sdhci-msm: Add interconnect bandwidth scaling support Interconnect bandwidth scaling support is now added as a part of OPP. So, make sure interconnect driver is ready before handling interconnect scaling. Signed-off-by: Pradeep P V K Reviewed-by: Sibi Sankar Reviewed-by: Matthias Kaehlcke Link: https://lore.kernel.org/r/1591691846-7578-2-git-send-email-ppvk@codeaurora.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-msm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index c0d58e9fcc33..cdafc4f69ca5 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -14,6 +14,7 @@ #include #include #include +#include #include "sdhci-pltfm.h" #include "cqhci.h" @@ -2071,6 +2072,11 @@ static int sdhci_msm_probe(struct platform_device *pdev) } msm_host->bulk_clks[0].clk = clk; + /* Check for optional interconnect paths */ + ret = dev_pm_opp_of_find_icc_paths(&pdev->dev, NULL); + if (ret) + goto bus_clk_disable; + msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core"); if (IS_ERR(msm_host->opp_table)) { ret = PTR_ERR(msm_host->opp_table); -- cgit v1.2.3 From 557ed5f06c63fc6dc37847ad299c4fb77aa90015 Mon Sep 17 00:00:00 2001 From: Pradeep P V K Date: Tue, 9 Jun 2020 14:07:26 +0530 Subject: dt-bindings: mmc: sdhci-msm: Add interconnect BW scaling strings Add interconnect bandwidth scaling supported strings for qcom-sdhci controller. Signed-off-by: Pradeep P V K Acked-by: Rob Herring Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1591691846-7578-3-git-send-email-ppvk@codeaurora.org Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-msm.txt | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt index b8e1d2b7aea9..3b602fd6180b 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.txt @@ -54,6 +54,21 @@ Required properties: - qcom,dll-config: Chipset and Platform specific value. Use this field to specify the DLL_CONFIG register value as per Hardware Programming Guide. +Optional Properties: +* Following bus parameters are required for interconnect bandwidth scaling: +- interconnects: Pairs of phandles and interconnect provider specifier + to denote the edge source and destination ports of + the interconnect path. + +- interconnect-names: For sdhc, we have two main paths. + 1. Data path : sdhc to ddr + 2. Config path : cpu to sdhc + For Data interconnect path the name supposed to be + is "sdhc-ddr" and for config interconnect path it is + "cpu-sdhc". + Please refer to Documentation/devicetree/bindings/ + interconnect/ for more details. + Example: sdhc_1: sdhci@f9824900 { @@ -71,6 +86,9 @@ Example: clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; clock-names = "core", "iface"; + interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>, + <&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>; + interconnect-names = "sdhc-ddr","cpu-sdhc"; qcom,dll-config = <0x000f642c>; qcom,ddr-config = <0x80040868>; -- cgit v1.2.3 From 47fad46b7ae096242ce46ddbc79184d7e0254b86 Mon Sep 17 00:00:00 2001 From: Sowjanya Komatineni Date: Thu, 4 Jun 2020 20:04:00 -0700 Subject: mmc: sdhci-tegra: Add comment for PADCALIB and PAD_CONTROL NVQUIRKS This patch adds comments about NVQUIRKS HAS_PADCALIB and NEEDS_PAD_CONTROL. Signed-off-by: Sowjanya Komatineni Link: https://lore.kernel.org/r/1591326240-28928-1-git-send-email-skomatineni@nvidia.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-tegra.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 3a372ab3d12e..0a3f9d024f2a 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -96,7 +96,16 @@ #define NVQUIRK_ENABLE_SDR50 BIT(3) #define NVQUIRK_ENABLE_SDR104 BIT(4) #define NVQUIRK_ENABLE_DDR50 BIT(5) +/* + * HAS_PADCALIB NVQUIRK is for SoC's supporting auto calibration of pads + * drive strength. + */ #define NVQUIRK_HAS_PADCALIB BIT(6) +/* + * NEEDS_PAD_CONTROL NVQUIRK is for SoC's having separate 3V3 and 1V8 pads. + * 3V3/1V8 pad selection happens through pinctrl state selection depending + * on the signaling mode. + */ #define NVQUIRK_NEEDS_PAD_CONTROL BIT(7) #define NVQUIRK_DIS_CARD_CLK_CONFIG_TAP BIT(8) #define NVQUIRK_CQHCI_DCMD_R1B_CMD_TIMING BIT(9) -- cgit v1.2.3 From 42a166d7e05452c9af44d65cc14725a181b0569f Mon Sep 17 00:00:00 2001 From: Yue Hu Date: Thu, 4 Jun 2020 18:01:02 +0800 Subject: mmc: sdio: Return ret if sdio_disable_func() fails We should return any possible error returned by mmc_io_rw_direct() rather than only -EIO in sdio_disable_func() failure path. Signed-off-by: Yue Hu Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20200604100102.13572-1-zbestahu@gmail.com Signed-off-by: Ulf Hansson --- drivers/mmc/core/sdio_io.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/core/sdio_io.c b/drivers/mmc/core/sdio_io.c index 2ba00acf64e6..cba54dfb04f7 100644 --- a/drivers/mmc/core/sdio_io.c +++ b/drivers/mmc/core/sdio_io.c @@ -133,7 +133,7 @@ int sdio_disable_func(struct sdio_func *func) err: pr_debug("SDIO: Failed to disable device %s\n", sdio_func_id(func)); - return -EIO; + return ret; } EXPORT_SYMBOL_GPL(sdio_disable_func); -- cgit v1.2.3 From ec97863cac3e36e877cc326b12568a237865ee69 Mon Sep 17 00:00:00 2001 From: Yue Hu Date: Mon, 8 Jun 2020 18:30:09 +0800 Subject: mmc: sdio: Enable SDIO 4-bit bus if not support SD_SCR_BUS_WIDTH_4 for SD combo card If the card type is SD combo(MMC_TYPE_SD_COMBO) and the memory part does not support wider bus(SD_SCR_BUS_WIDTH_4), nothing will be done except return 0. However, we should check whether IO part support wider bus or not. We should use available IO ability if supported. In addition, there's a duplicated check to MMC_CAP_4_BIT_DATA since sdio_enable_wide() will include that check. And we can also save one call site to sdio_enable_wide() after this change. Signed-off-by: Yue Hu Link: https://lore.kernel.org/r/20200608103009.5000-1-zbestahu@gmail.com Signed-off-by: Ulf Hansson --- drivers/mmc/core/sdio.c | 26 ++++++++++++-------------- 1 file changed, 12 insertions(+), 14 deletions(-) diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index b65b26f76d71..d9ba7dd7cf1b 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -308,25 +308,23 @@ static int sdio_enable_4bit_bus(struct mmc_card *card) { int err; + err = sdio_enable_wide(card); + if (err <= 0) + return err; if (card->type == MMC_TYPE_SDIO) - err = sdio_enable_wide(card); - else if ((card->host->caps & MMC_CAP_4_BIT_DATA) && - (card->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) { + goto out; + + if (card->scr.bus_widths & SD_SCR_BUS_WIDTH_4) { err = mmc_app_set_bus_width(card, MMC_BUS_WIDTH_4); - if (err) + if (err) { + sdio_disable_wide(card); return err; - err = sdio_enable_wide(card); - if (err <= 0) - mmc_app_set_bus_width(card, MMC_BUS_WIDTH_1); - } else - return 0; - - if (err > 0) { - mmc_set_bus_width(card->host, MMC_BUS_WIDTH_4); - err = 0; + } } +out: + mmc_set_bus_width(card->host, MMC_BUS_WIDTH_4); - return err; + return 0; } -- cgit v1.2.3 From 40e6c479e9250808ff19ccfb6d48979ecb2377bd Mon Sep 17 00:00:00 2001 From: Yue Hu Date: Tue, 9 Jun 2020 16:14:31 +0800 Subject: mmc: sdio: Fix 1-bit mode for SD-combo cards during suspend Commit 6b5eda369ac3 ("sdio: put active devices into 1-bit mode during suspend") disabled 4-bit mode during system suspend. After this patch, commit 7310ece86ad7 ("mmc: implement SD-combo (IO+mem) support") used new sdio_enable_4bit_bus() instead of sdio_enable_wide() to support SD-combo cards, also for card resume. However, no corresponding support added during suspend. That is not correct. Let's fix it. Signed-off-by: Yue Hu Link: https://lore.kernel.org/r/20200609081431.6376-1-zbestahu@gmail.com Signed-off-by: Ulf Hansson --- drivers/mmc/core/sdio.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index d9ba7dd7cf1b..0e32ca7b9488 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -303,6 +303,27 @@ static int sdio_disable_wide(struct mmc_card *card) return 0; } +static int sdio_disable_4bit_bus(struct mmc_card *card) +{ + int err; + + if (card->type == MMC_TYPE_SDIO) + goto out; + + if (!(card->host->caps & MMC_CAP_4_BIT_DATA)) + return 0; + + if (!(card->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) + return 0; + + err = mmc_app_set_bus_width(card, MMC_BUS_WIDTH_1); + if (err) + return err; + +out: + return sdio_disable_wide(card); +} + static int sdio_enable_4bit_bus(struct mmc_card *card) { @@ -970,7 +991,7 @@ static int mmc_sdio_suspend(struct mmc_host *host) mmc_claim_host(host); if (mmc_card_keep_power(host) && mmc_card_wake_sdio_irq(host)) - sdio_disable_wide(host->card); + sdio_disable_4bit_bus(host->card); if (!mmc_card_keep_power(host)) { mmc_power_off(host); -- cgit v1.2.3 From c99e1d0c91ac8d7db3062ea1af315f21295701d7 Mon Sep 17 00:00:00 2001 From: Chuhong Yuan Date: Tue, 9 Jun 2020 00:22:26 +0800 Subject: mmc: sdhci-of-arasan: Add missed checks for devm_clk_register() These functions do not check the return value of devm_clk_register(): - sdhci_arasan_register_sdcardclk() - sdhci_arasan_register_sampleclk() Therefore, add the missed checks to fix them. Fixes: c390f2110adf1 ("mmc: sdhci-of-arasan: Add ability to export card clock") Signed-off-by: Chuhong Yuan Reviewed-by: Douglas Anderson Link: https://lore.kernel.org/r/20200608162226.3259186-1-hslester96@gmail.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-of-arasan.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index db9b544465cd..fb26e743e1fd 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -1299,6 +1299,8 @@ sdhci_arasan_register_sdcardclk(struct sdhci_arasan_data *sdhci_arasan, clk_data->sdcardclk_hw.init = &sdcardclk_init; clk_data->sdcardclk = devm_clk_register(dev, &clk_data->sdcardclk_hw); + if (IS_ERR(clk_data->sdcardclk)) + return PTR_ERR(clk_data->sdcardclk); clk_data->sdcardclk_hw.init = NULL; ret = of_clk_add_provider(np, of_clk_src_simple_get, @@ -1349,6 +1351,8 @@ sdhci_arasan_register_sampleclk(struct sdhci_arasan_data *sdhci_arasan, clk_data->sampleclk_hw.init = &sampleclk_init; clk_data->sampleclk = devm_clk_register(dev, &clk_data->sampleclk_hw); + if (IS_ERR(clk_data->sampleclk)) + return PTR_ERR(clk_data->sampleclk); clk_data->sampleclk_hw.init = NULL; ret = of_clk_add_provider(np, of_clk_src_simple_get, -- cgit v1.2.3 From 81a77ee9092dc819a7a53c18175fe907d55f7fef Mon Sep 17 00:00:00 2001 From: Ludovic Barre Date: Thu, 11 Jun 2020 15:28:39 +0200 Subject: mmc: mmci: add sdio datactrl mask for sdmmc revisions This patch adds datactrl_mask_sdio for sdmmc revisions. sdmmc revisions used same bit of previous ST variant. Signed-off-by: Ludovic Barre Link: https://lore.kernel.org/r/20200611132839.4515-1-ludovic.barre@st.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/mmci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c index a69d6a0c2e15..b5a41a7ce165 100644 --- a/drivers/mmc/host/mmci.c +++ b/drivers/mmc/host/mmci.c @@ -267,6 +267,7 @@ static struct variant_data variant_stm32_sdmmc = { .datalength_bits = 25, .datactrl_blocksz = 14, .datactrl_any_blocksz = true, + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, .stm32_idmabsize_mask = GENMASK(12, 5), .busy_timeout = true, .busy_detect = true, @@ -292,6 +293,7 @@ static struct variant_data variant_stm32_sdmmcv2 = { .datalength_bits = 25, .datactrl_blocksz = 14, .datactrl_any_blocksz = true, + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, .stm32_idmabsize_mask = GENMASK(16, 5), .dma_lli = true, .busy_timeout = true, -- cgit v1.2.3 From 27d8a86a30506624d0e49f20fa1c92edb58443cc Mon Sep 17 00:00:00 2001 From: Flavio Suligoi Date: Wed, 17 Jun 2020 17:19:38 +0200 Subject: mmc: sdhci-msm: Fix spelling mistake Fix typo: "trigered" --> "triggered" Signed-off-by: Flavio Suligoi Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/20200617151938.30217-1-f.suligoi@asem.it Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-msm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index cdafc4f69ca5..d515a0915e3a 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1364,7 +1364,7 @@ static inline void sdhci_msm_complete_pwr_irq_wait( * To what state the register writes will change the IO lines should be passed * as the argument req_type. This API will check whether the IO line's state * is already the expected state and will wait for power irq only if - * power irq is expected to be trigerred based on the current IO line state + * power irq is expected to be triggered based on the current IO line state * and expected IO line state. */ static void sdhci_msm_check_power_status(struct sdhci_host *host, u32 req_type) -- cgit v1.2.3 From b9a349fdc716a099e96e96de0dd21faf1d4cd594 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Thu, 18 Jun 2020 10:03:21 +0200 Subject: mmc: sh_mmcif: Use "kHz" for kilohertz "K" stands for "kelvin". While at it, make the spacing before units consistent. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200618080321.16678-1-geert+renesas@glider.be Reviewed-by: Wolfram Sang Signed-off-by: Ulf Hansson --- drivers/mmc/host/sh_mmcif.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c index 7e1fd557109c..9f53634aa411 100644 --- a/drivers/mmc/host/sh_mmcif.c +++ b/drivers/mmc/host/sh_mmcif.c @@ -191,9 +191,9 @@ STS2_AC12BSYTO | STS2_RSPBSYTO | \ STS2_AC12RSPTO | STS2_RSPTO) -#define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ -#define CLKDEV_MMC_DATA 20000000 /* 20MHz */ -#define CLKDEV_INIT 400000 /* 400 KHz */ +#define CLKDEV_EMMC_DATA 52000000 /* 52 MHz */ +#define CLKDEV_MMC_DATA 20000000 /* 20 MHz */ +#define CLKDEV_INIT 400000 /* 400 kHz */ enum sh_mmcif_state { STATE_IDLE, -- cgit v1.2.3 From 72f47aec86e1e0ffd0969698f45a53d5c7c930a7 Mon Sep 17 00:00:00 2001 From: Jisheng Zhang Date: Mon, 22 Jun 2020 16:44:31 +0800 Subject: dt-bindings: mmc: Convert pwrseq to json-schema Convert the pwrseq binding to DT schema format using json-schema. At the same time, fix a couple of issues with the examples discovered by the validation tool -- missing ";" Signed-off-by: Jisheng Zhang Link: https://lore.kernel.org/r/20200622164431.3dbc8c5a@xhacker.debian Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/mmc-pwrseq-emmc.txt | 25 --------- .../devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml | 46 ++++++++++++++++ .../devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt | 16 ------ .../devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml | 39 ++++++++++++++ .../devicetree/bindings/mmc/mmc-pwrseq-simple.txt | 31 ----------- .../devicetree/bindings/mmc/mmc-pwrseq-simple.yaml | 62 ++++++++++++++++++++++ 6 files changed, 147 insertions(+), 72 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.txt create mode 100644 Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml delete mode 100644 Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt create mode 100644 Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml delete mode 100644 Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt create mode 100644 Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.txt deleted file mode 100644 index 3d965d57e00b..000000000000 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.txt +++ /dev/null @@ -1,25 +0,0 @@ -* The simple eMMC hardware reset provider - -The purpose of this driver is to perform standard eMMC hw reset -procedure, as described by Jedec 4.4 specification. This procedure is -performed just after MMC core enabled power to the given mmc host (to -fix possible issues if bootloader has left eMMC card in initialized or -unknown state), and before performing complete system reboot (also in -case of emergency reboot call). The latter is needed on boards, which -doesn't have hardware reset logic connected to emmc card and (limited or -broken) ROM bootloaders are unable to read second stage from the emmc -card if the card is left in unknown or already initialized state. - -Required properties: -- compatible : contains "mmc-pwrseq-emmc". -- reset-gpios : contains a GPIO specifier. The reset GPIO is asserted - and then deasserted to perform eMMC card reset. To perform - reset procedure as described in Jedec 4.4 specification, the - gpio line should be defined as GPIO_ACTIVE_LOW. - -Example: - - sdhci0_pwrseq { - compatible = "mmc-pwrseq-emmc"; - reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - } diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml new file mode 100644 index 000000000000..77f746f57284 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-emmc.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-emmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple eMMC hardware reset provider binding + +maintainers: + - Ulf Hansson + +description: + The purpose of this driver is to perform standard eMMC hw reset + procedure, as described by Jedec 4.4 specification. This procedure is + performed just after MMC core enabled power to the given mmc host (to + fix possible issues if bootloader has left eMMC card in initialized or + unknown state), and before performing complete system reboot (also in + case of emergency reboot call). The latter is needed on boards, which + doesn't have hardware reset logic connected to emmc card and (limited or + broken) ROM bootloaders are unable to read second stage from the emmc + card if the card is left in unknown or already initialized state. + +properties: + compatible: + const: mmc-pwrseq-emmc + + reset-gpios: + minItems: 1 + description: + contains a GPIO specifier. The reset GPIO is asserted + and then deasserted to perform eMMC card reset. To perform + reset procedure as described in Jedec 4.4 specification, the + gpio line should be defined as GPIO_ACTIVE_LOW. + +required: + - compatible + - reset-gpios + +examples: + - | + #include + sdhci0_pwrseq { + compatible = "mmc-pwrseq-emmc"; + reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + }; +... diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt deleted file mode 100644 index 22e9340e4ba2..000000000000 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt +++ /dev/null @@ -1,16 +0,0 @@ -* Marvell SD8787 power sequence provider - -Required properties: -- compatible: must be "mmc-pwrseq-sd8787". -- powerdown-gpios: contains a power down GPIO specifier with the - default active state -- reset-gpios: contains a reset GPIO specifier with the default - active state - -Example: - - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-sd8787"; - powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; - reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; - } diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml new file mode 100644 index 000000000000..a68820d31d50 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-sd8787.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell SD8787 power sequence provider binding + +maintainers: + - Ulf Hansson + +properties: + compatible: + const: mmc-pwrseq-sd8787 + + powerdown-gpios: + minItems: 1 + description: + contains a power down GPIO specifier with the default active state + + reset-gpios: + minItems: 1 + description: + contains a reset GPIO specifier with the default active state + +required: + - compatible + - powerdown-gpios + - reset-gpios + +examples: + - | + #include + wifi_pwrseq: wifi_pwrseq { + compatible = "mmc-pwrseq-sd8787"; + powerdown-gpios = <&twl_gpio 0 GPIO_ACTIVE_LOW>; + reset-gpios = <&twl_gpio 1 GPIO_ACTIVE_LOW>; + }; +... diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt deleted file mode 100644 index 9029b45b8a22..000000000000 --- a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.txt +++ /dev/null @@ -1,31 +0,0 @@ -* The simple MMC power sequence provider - -The purpose of the simple MMC power sequence provider is to supports a set of -common properties between various SOC designs. It thus enables us to use the -same provider for several SOC designs. - -Required properties: -- compatible : contains "mmc-pwrseq-simple". - -Optional properties: -- reset-gpios : contains a list of GPIO specifiers. The reset GPIOs are asserted - at initialization and prior we start the power up procedure of the card. - They will be de-asserted right after the power has been provided to the - card. -- clocks : Must contain an entry for the entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names : Must include the following entry: - "ext_clock" (External clock provided to the card). -- post-power-on-delay-ms : Delay in ms after powering the card and - de-asserting the reset-gpios (if any) -- power-off-delay-us : Delay in us after asserting the reset-gpios (if any) - during power off of the card. - -Example: - - sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; - clocks = <&clk_32768_ck>; - clock-names = "ext_clock"; - } diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml new file mode 100644 index 000000000000..449215444723 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-simple.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/mmc-pwrseq-simple.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple MMC power sequence provider binding + +maintainers: + - Ulf Hansson + +description: + The purpose of the simple MMC power sequence provider is to supports a set + of common properties between various SOC designs. It thus enables us to use + the same provider for several SOC designs. + +properties: + compatible: + const: mmc-pwrseq-simple + + reset-gpios: + minItems: 1 + description: + contains a list of GPIO specifiers. The reset GPIOs are asserted + at initialization and prior we start the power up procedure of the card. + They will be de-asserted right after the power has been provided to the + card. + + clocks: + minItems: 1 + description: Handle for the entry in clock-names. + + clock-names: + items: + - const: ext_clock + description: External clock provided to the card. + + post-power-on-delay-ms: + description: + Delay in ms after powering the card and de-asserting the + reset-gpios (if any). + $ref: /schemas/types.yaml#/definitions/uint32 + + power-off-delay-us: + description: + Delay in us after asserting the reset-gpios (if any) + during power off of the card. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + +examples: + - | + #include + sdhci0_pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; + clocks = <&clk_32768_ck>; + clock-names = "ext_clock"; + }; +... -- cgit v1.2.3 From b1f85c8f2f033d462ce53cae6cbdfd6521dd54c5 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Fri, 19 Jun 2020 18:27:55 +0530 Subject: dt-bindings: mmc: sdhci-am654: Add ti,clkbuf-sel binding Add documentation for the clock buffer select phy property in the am654x and j721e 4 bit IP Signed-off-by: Faiz Abbas Link: https://lore.kernel.org/r/20200619125801.9530-2-faiz_abbas@ti.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/sdhci-am654.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt index c6ccecb9ae5a..6d202f4d9249 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-am654.txt +++ b/Documentation/devicetree/bindings/mmc/sdhci-am654.txt @@ -39,6 +39,7 @@ Optional Properties (Required for ti,am654-sdhci-5.1 and ti,j721e-sdhci-8bit): Valid values are 33, 40, 50, 66 and 100 ohms. Optional Properties: - ti,strobe-sel: strobe select delay for HS400 speed mode. Default value: 0x0. + - ti,clkbuf-sel: Clock Delay Buffer Select Example: -- cgit v1.2.3 From 23514731f4ab885dc0692ee4113e924b5ab3b492 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Fri, 19 Jun 2020 18:27:56 +0530 Subject: mmc: sdhci_am654: Add flag for PHY calibration Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB flag to indicate the same. Signed-off-by: Faiz Abbas Link: https://lore.kernel.org/r/20200619125801.9530-3-faiz_abbas@ti.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci_am654.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 061b4398a4f1..85a05344f825 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -97,6 +97,7 @@ struct sdhci_am654_driver_data { #define FREQSEL_2_BIT (1 << 1) #define STRBSEL_4_BIT (1 << 2) #define DLL_PRESENT (1 << 3) +#define DLL_CALIB (1 << 4) }; struct timing_data { @@ -325,7 +326,8 @@ static const struct sdhci_pltfm_data sdhci_am654_pdata = { static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { .pdata = &sdhci_am654_pdata, - .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, + .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | + DLL_CALIB, }; static struct sdhci_ops sdhci_j721e_8bit_ops = { @@ -348,7 +350,7 @@ static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { .pdata = &sdhci_j721e_8bit_pdata, - .flags = DLL_PRESENT, + .flags = DLL_PRESENT | DLL_CALIB, }; static struct sdhci_ops sdhci_j721e_4bit_ops = { @@ -469,7 +471,7 @@ static int sdhci_am654_init(struct sdhci_host *host) mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); - if (sdhci_am654->flags & DLL_PRESENT) { + if (sdhci_am654->flags & DLL_CALIB) { regmap_read(sdhci_am654->base, PHY_STAT1, &val); if (~val & CALDONE_MASK) { /* Calibrate IO lines */ -- cgit v1.2.3 From 09db994358ece22ab68190f8be020411bef5d2e2 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Fri, 19 Jun 2020 18:27:57 +0530 Subject: mmc: sdhci_am654: Add Support for SR2.0 Add Support for AM65x PG2.0. Use the SoC bus framework to fixup the driver data and skip do DLL calibration if the revision is 1.0 Signed-off-by: Faiz Abbas Link: https://lore.kernel.org/r/20200619125801.9530-4-faiz_abbas@ti.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci_am654.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 85a05344f825..365eb2819dd9 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -11,6 +11,7 @@ #include #include #include +#include #include "cqhci.h" #include "sdhci-pltfm.h" @@ -324,12 +325,17 @@ static const struct sdhci_pltfm_data sdhci_am654_pdata = { .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, }; -static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { +static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { .pdata = &sdhci_am654_pdata, .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | DLL_CALIB, }; +static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { + .pdata = &sdhci_am654_pdata, + .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, +}; + static struct sdhci_ops sdhci_j721e_8bit_ops = { .get_max_clock = sdhci_pltfm_clk_get_max_clock, .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, @@ -376,6 +382,14 @@ static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { .flags = IOMUX_PRESENT, }; +static const struct soc_device_attribute sdhci_am654_devices[] = { + { .family = "AM65X", + .revision = "SR1.0", + .data = &sdhci_am654_sr1_drvdata + }, + {/* sentinel */} +}; + static void sdhci_am654_dumpregs(struct mmc_host *mmc) { sdhci_dumpregs(mmc_priv(mmc)); @@ -587,6 +601,7 @@ static const struct of_device_id sdhci_am654_of_match[] = { static int sdhci_am654_probe(struct platform_device *pdev) { const struct sdhci_am654_driver_data *drvdata; + const struct soc_device_attribute *soc; struct sdhci_pltfm_host *pltfm_host; struct sdhci_am654_data *sdhci_am654; const struct of_device_id *match; @@ -598,6 +613,12 @@ static int sdhci_am654_probe(struct platform_device *pdev) match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); drvdata = match->data; + + /* Update drvdata based on SoC revision */ + soc = soc_device_match(sdhci_am654_devices); + if (soc && soc->data) + drvdata = soc->data; + host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); if (IS_ERR(host)) return PTR_ERR(host); -- cgit v1.2.3 From fe52e2fbc6ef3b36dafebde61d1d87717bcde3d4 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Fri, 19 Jun 2020 18:27:58 +0530 Subject: mmc: sdhci_am654: Fix conditions for enabling dll The clock > CLOCK_TOO_SLOW_HZ condition gating phy configuration is only required because dll should not be enabled at too low a clock frequency or too low timing. Make sure that this condition only gates dll enablement. Signed-off-by: Faiz Abbas Link: https://lore.kernel.org/r/20200619125801.9530-5-faiz_abbas@ti.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci_am654.c | 42 ++++++++++++++++++++---------------------- 1 file changed, 20 insertions(+), 22 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 365eb2819dd9..8b0f69012d09 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -204,34 +204,32 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) sdhci_set_clock(host, clock); - if (clock > CLOCK_TOO_SLOW_HZ) { - /* Setup DLL Output TAP delay */ - if (sdhci_am654->legacy_otapdly) - otap_del_sel = sdhci_am654->otap_del_sel[0]; - else - otap_del_sel = sdhci_am654->otap_del_sel[timing]; + /* Setup DLL Output TAP delay */ + if (sdhci_am654->legacy_otapdly) + otap_del_sel = sdhci_am654->otap_del_sel[0]; + else + otap_del_sel = sdhci_am654->otap_del_sel[timing]; - otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; + otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; - mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; - val = (otap_del_ena << OTAPDLYENA_SHIFT) | - (otap_del_sel << OTAPDLYSEL_SHIFT); + mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; + val = (otap_del_ena << OTAPDLYENA_SHIFT) | + (otap_del_sel << OTAPDLYSEL_SHIFT); - /* Write to STRBSEL for HS400 speed mode */ - if (timing == MMC_TIMING_MMC_HS400) { - if (sdhci_am654->flags & STRBSEL_4_BIT) - mask |= STRBSEL_4BIT_MASK; - else - mask |= STRBSEL_8BIT_MASK; + /* Write to STRBSEL for HS400 speed mode */ + if (timing == MMC_TIMING_MMC_HS400) { + if (sdhci_am654->flags & STRBSEL_4_BIT) + mask |= STRBSEL_4BIT_MASK; + else + mask |= STRBSEL_8BIT_MASK; - val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; - } + val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; + } - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); - if (timing > MMC_TIMING_UHS_SDR25) - sdhci_am654_setup_dll(host, clock); - } + if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) + sdhci_am654_setup_dll(host, clock); } static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, -- cgit v1.2.3 From 0003417d5738fe2c8736aaa9abb3170fa0757689 Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Fri, 19 Jun 2020 18:27:59 +0530 Subject: mmc: sdhci_am654: Update delay chain configuration For speed modes where DLL is not enabled write to TXDLYCLK to enable transmitter delay chain mode. Signed-off-by: Faiz Abbas Link: https://lore.kernel.org/r/20200619125801.9530-6-faiz_abbas@ti.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci_am654.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 8b0f69012d09..f7535ee3a232 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -61,6 +61,8 @@ #define CALDONE_MASK BIT(CALDONE_SHIFT) #define RETRIM_SHIFT 17 #define RETRIM_MASK BIT(RETRIM_SHIFT) +#define SELDLYTXCLK_SHIFT 17 +#define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) #define DRIVER_STRENGTH_50_OHM 0x0 #define DRIVER_STRENGTH_33_OHM 0x1 @@ -228,8 +230,14 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); - if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) + if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) { + regmap_update_bits(sdhci_am654->base, PHY_CTRL5, + SELDLYTXCLK_MASK, 0); sdhci_am654_setup_dll(host, clock); + } else { + regmap_update_bits(sdhci_am654->base, PHY_CTRL5, + SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT); + } } static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, -- cgit v1.2.3 From 61d9c4aa97f32a67ccde89325e5048d66095b55b Mon Sep 17 00:00:00 2001 From: Faiz Abbas Date: Fri, 19 Jun 2020 18:28:00 +0530 Subject: mmc: sdhci_am654: Add support for clkbuf_sel property Add support for writing new clkbuf_sel property for the J721e 4 bit IP. Signed-off-by: Faiz Abbas Signed-off-by: Sekhar Nori Link: https://lore.kernel.org/r/20200619125801.9530-7-faiz_abbas@ti.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci_am654.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index f7535ee3a232..f9d24af12396 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -47,6 +47,8 @@ #define SEL100_MASK BIT(SEL100_SHIFT) #define FREQSEL_SHIFT 8 #define FREQSEL_MASK GENMASK(10, 8) +#define CLKBUFSEL_SHIFT 0 +#define CLKBUFSEL_MASK GENMASK(2, 0) #define DLL_TRIM_ICP_SHIFT 4 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) #define DR_TY_SHIFT 20 @@ -86,6 +88,7 @@ struct sdhci_am654_data { struct regmap *base; bool legacy_otapdly; int otap_del_sel[11]; + int clkbuf_sel; int trm_icp; int drv_strength; bool dll_on; @@ -238,6 +241,9 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL5, SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT); } + + regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, + sdhci_am654->clkbuf_sel); } static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, @@ -260,6 +266,9 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, (otap_del_sel << OTAPDLYSEL_SHIFT); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); + regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, + sdhci_am654->clkbuf_sel); + sdhci_set_clock(host, clock); } @@ -582,6 +591,8 @@ static int sdhci_am654_get_of_property(struct platform_device *pdev, } device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); + device_property_read_u32(dev, "ti,clkbuf-sel", + &sdhci_am654->clkbuf_sel); sdhci_get_of_property(pdev); -- cgit v1.2.3 From e81515556d76cc00272bded98ec8d1def6eb9e2c Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Mon, 22 Jun 2020 16:19:19 +0800 Subject: mmc: sdio: fix clock rate setting for SDR12/SDR25 mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In current code logic, when work in SDR12/SDR25 mode, the final clock rate is incorrect, just the legancy 400KHz, because the card->sw_caps.sd3_bus_mode do not has the flag SD_MODE_UHS_SDR12 or SD_MODE_UHS_SDR25. Besides, SDIO_SPEED_SDR12 is actually value 0, and every mode need to config the timing and clock rate, so remove the ‘if’ operator. Signed-off-by: Haibo Chen Tested-by: Pali Rohár Link: https://lore.kernel.org/r/1592813959-5914-1-git-send-email-haibo.chen@nxp.com Signed-off-by: Ulf Hansson --- drivers/mmc/core/sdio.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c index 0e32ca7b9488..7b40553d3934 100644 --- a/drivers/mmc/core/sdio.c +++ b/drivers/mmc/core/sdio.c @@ -176,15 +176,18 @@ static int sdio_read_cccr(struct mmc_card *card, u32 ocr) if (mmc_host_uhs(card->host)) { if (data & SDIO_UHS_DDR50) card->sw_caps.sd3_bus_mode - |= SD_MODE_UHS_DDR50; + |= SD_MODE_UHS_DDR50 | SD_MODE_UHS_SDR50 + | SD_MODE_UHS_SDR25 | SD_MODE_UHS_SDR12; if (data & SDIO_UHS_SDR50) card->sw_caps.sd3_bus_mode - |= SD_MODE_UHS_SDR50; + |= SD_MODE_UHS_SDR50 | SD_MODE_UHS_SDR25 + | SD_MODE_UHS_SDR12; if (data & SDIO_UHS_SDR104) card->sw_caps.sd3_bus_mode - |= SD_MODE_UHS_SDR104; + |= SD_MODE_UHS_SDR104 | SD_MODE_UHS_SDR50 + | SD_MODE_UHS_SDR25 | SD_MODE_UHS_SDR12; } ret = mmc_io_rw_direct(card, 0, 0, @@ -537,10 +540,8 @@ static int sdio_set_bus_speed_mode(struct mmc_card *card) max_rate = min_not_zero(card->quirk_max_rate, card->sw_caps.uhs_max_dtr); - if (bus_speed) { - mmc_set_timing(card->host, timing); - mmc_set_clock(card->host, max_rate); - } + mmc_set_timing(card->host, timing); + mmc_set_clock(card->host, max_rate); return 0; } -- cgit v1.2.3 From 3722c74c721b5612ffa45027984bd8161d1aae06 Mon Sep 17 00:00:00 2001 From: Haibo Chen Date: Wed, 24 Jun 2020 16:03:50 +0800 Subject: mmc: sdhci-esdhc-imx: dump internal IC debug status during error USDHC of i.MX has internal IC debug register, which record the IC logical status. So dump these logical status in error condition, this can help analyzing issue. Signed-off-by: Haibo Chen Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/1592985830-13038-1-git-send-email-haibo.chen@nxp.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-esdhc-imx.c | 39 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 1d7f84b23a22..a76b4513fbec 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c @@ -38,6 +38,16 @@ #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) +#define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2 +#define ESDHC_DEBUG_SEL_REG 0xc3 +#define ESDHC_DEBUG_SEL_MASK 0xf +#define ESDHC_DEBUG_SEL_CMD_STATE 1 +#define ESDHC_DEBUG_SEL_DATA_STATE 2 +#define ESDHC_DEBUG_SEL_TRANS_STATE 3 +#define ESDHC_DEBUG_SEL_DMA_STATE 4 +#define ESDHC_DEBUG_SEL_ADMA_STATE 5 +#define ESDHC_DEBUG_SEL_FIFO_STATE 6 +#define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7 #define ESDHC_WTMK_LVL 0x44 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF @@ -348,6 +358,34 @@ static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, i writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); } +#define DRIVER_NAME "sdhci-esdhc-imx" +#define ESDHC_IMX_DUMP(f, x...) \ + pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) +static void esdhc_dump_debug_regs(struct sdhci_host *host) +{ + int i; + char *debug_status[7] = { + "cmd debug status", + "data debug status", + "trans debug status", + "dma debug status", + "adma debug status", + "fifo debug status", + "async fifo debug status" + }; + + ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n"); + for (i = 0; i < 7; i++) { + esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, + ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG); + ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i], + readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); + } + + esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG); + +} + static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host) { u32 present_state; @@ -1237,6 +1275,7 @@ static struct sdhci_ops sdhci_esdhc_ops = { .set_uhs_signaling = esdhc_set_uhs_signaling, .reset = esdhc_reset, .irq = esdhc_cqhci_irq, + .dump_vendor_regs = esdhc_dump_debug_regs, }; static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { -- cgit v1.2.3 From b343a0911057899aaf082a29f15c66a1a4531952 Mon Sep 17 00:00:00 2001 From: Akshu Agrawal Date: Tue, 23 Jun 2020 19:03:27 +0530 Subject: mmc: sdhci-acpi: For amd device set driver type as MMC_SET_DRIVER_TYPE_A HS400/HS200/eMMC HS doesn't have Preset Value register. Hence, sdhci_set_ios function overrides the value set by fmw to SDHCI_CTRL_DRV_TYPE_B. This patch sets drv_type to MMC_SET_DRIVER_TYPE_A so that host_control2 register gets updated with the required strength value. Signed-off-by: Akshu Agrawal Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/20200623133347.4598-1-akshu.agrawal@amd.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-acpi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c index d8b76cb8698a..48ecbd0b180d 100644 --- a/drivers/mmc/host/sdhci-acpi.c +++ b/drivers/mmc/host/sdhci-acpi.c @@ -542,6 +542,7 @@ static int amd_select_drive_strength(struct mmc_card *card, unsigned int max_dtr, int host_drv, int card_drv, int *drv_type) { + *drv_type = MMC_SET_DRIVER_TYPE_A; return MMC_SET_DRIVER_TYPE_A; } -- cgit v1.2.3 From 0fcb031e52d7fc03913f2b1aa5302c09ba6155db Mon Sep 17 00:00:00 2001 From: Vijay Viswanath Date: Tue, 23 Jun 2020 19:04:46 +0530 Subject: mmc: sdhci: Allow platform controlled voltage switching If vendor platform drivers are controlling whole logic of voltage switching, then sdhci driver no need control vqmmc regulator. So skip enabling/disable vqmmc from SDHC driver. Signed-off-by: Vijay Viswanath Signed-off-by: Veerabhadrarao Badiganti Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/1592919288-1020-2-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci.c | 32 +++++++++++++++++++------------- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 20 insertions(+), 13 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 37b1158c1c0c..e6275c2202b0 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -4105,6 +4105,7 @@ int sdhci_setup_host(struct sdhci_host *host) unsigned int override_timeout_clk; u32 max_clk; int ret; + bool enable_vqmmc = false; WARN_ON(host == NULL); if (host == NULL) @@ -4118,9 +4119,12 @@ int sdhci_setup_host(struct sdhci_host *host) * the host can take the appropriate action if regulators are not * available. */ - ret = mmc_regulator_get_supply(mmc); - if (ret) - return ret; + if (!mmc->supply.vqmmc) { + ret = mmc_regulator_get_supply(mmc); + if (ret) + return ret; + enable_vqmmc = true; + } DBG("Version: 0x%08x | Present: 0x%08x\n", sdhci_readw(host, SDHCI_HOST_VERSION), @@ -4377,7 +4381,15 @@ int sdhci_setup_host(struct sdhci_host *host) mmc->caps |= MMC_CAP_NEEDS_POLL; if (!IS_ERR(mmc->supply.vqmmc)) { - ret = regulator_enable(mmc->supply.vqmmc); + if (enable_vqmmc) { + ret = regulator_enable(mmc->supply.vqmmc); + if (ret) { + pr_warn("%s: Failed to enable vqmmc regulator: %d\n", + mmc_hostname(mmc), ret); + mmc->supply.vqmmc = ERR_PTR(-EINVAL); + } + host->sdhci_core_to_disable_vqmmc = !ret; + } /* If vqmmc provides no 1.8V signalling, then there's no UHS */ if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, @@ -4390,12 +4402,6 @@ int sdhci_setup_host(struct sdhci_host *host) if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000, 3600000)) host->flags &= ~SDHCI_SIGNALING_330; - - if (ret) { - pr_warn("%s: Failed to enable vqmmc regulator: %d\n", - mmc_hostname(mmc), ret); - mmc->supply.vqmmc = ERR_PTR(-EINVAL); - } } if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { @@ -4626,7 +4632,7 @@ int sdhci_setup_host(struct sdhci_host *host) return 0; unreg: - if (!IS_ERR(mmc->supply.vqmmc)) + if (host->sdhci_core_to_disable_vqmmc) regulator_disable(mmc->supply.vqmmc); undma: if (host->align_buffer) @@ -4644,7 +4650,7 @@ void sdhci_cleanup_host(struct sdhci_host *host) { struct mmc_host *mmc = host->mmc; - if (!IS_ERR(mmc->supply.vqmmc)) + if (host->sdhci_core_to_disable_vqmmc) regulator_disable(mmc->supply.vqmmc); if (host->align_buffer) @@ -4787,7 +4793,7 @@ void sdhci_remove_host(struct sdhci_host *host, int dead) destroy_workqueue(host->complete_wq); - if (!IS_ERR(mmc->supply.vqmmc)) + if (host->sdhci_core_to_disable_vqmmc) regulator_disable(mmc->supply.vqmmc); if (host->align_buffer) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 0008bbd27127..0770c036e2ff 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -567,6 +567,7 @@ struct sdhci_host { u32 caps1; /* CAPABILITY_1 */ bool read_caps; /* Capability flags have been read */ + bool sdhci_core_to_disable_vqmmc; /* sdhci core can disable vqmmc */ unsigned int ocr_avail_sdio; /* OCR bit masks */ unsigned int ocr_avail_sd; unsigned int ocr_avail_mmc; -- cgit v1.2.3 From ed54ef9878fe87d8df5aafdd763a70f96fdbce03 Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Tue, 23 Jun 2020 19:04:47 +0530 Subject: mmc: core: Set default power mode in mmc_alloc_host() Set the default power mode, MMC_POWER_UNDEFINED, in mmc_alloc_host() rather than in mmc_start_host(). This enables host drivers to make use of the initial state during ->probe(). Signed-off-by: Veerabhadrarao Badiganti Link: https://lore.kernel.org/r/1592919288-1020-3-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson --- drivers/mmc/core/core.c | 1 - drivers/mmc/core/host.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c index aff3fa937674..8ccae6452b9c 100644 --- a/drivers/mmc/core/core.c +++ b/drivers/mmc/core/core.c @@ -2303,7 +2303,6 @@ void mmc_start_host(struct mmc_host *host) { host->f_init = max(min(freqs[0], host->f_max), host->f_min); host->rescan_disable = 0; - host->ios.power_mode = MMC_POWER_UNDEFINED; if (!(host->caps2 & MMC_CAP2_NO_PRESCAN_POWERUP)) { mmc_claim_host(host); diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 6141a85749ca..793597556cd7 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -434,6 +434,7 @@ struct mmc_host *mmc_alloc_host(int extra, struct device *dev) host->fixed_drv_type = -EINVAL; host->ios.power_delay_ms = 10; + host->ios.power_mode = MMC_POWER_UNDEFINED; return host; } -- cgit v1.2.3 From 92a2173837d2c872362e32d5e54f4c8aa539bdbf Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Tue, 23 Jun 2020 19:04:48 +0530 Subject: mmc: sdhci-msm: Use internal voltage control On qcom SD host controllers voltage switching be done after the HW is ready for it. The HW informs its readiness through power irq. The voltage switching should happen only then. Use the internal voltage switching and then control the voltage switching using power irq. IO-bus supply of eMMC would be kept always-on. So set the load for this supply to configure it in LPM when eMMC is suspend state and in HPM when eMMC is active. Co-developed-by: Asutosh Das Signed-off-by: Asutosh Das Co-developed-by: Vijay Viswanath Signed-off-by: Vijay Viswanath Co-developed-by: Veerabhadrarao Badiganti Signed-off-by: Veerabhadrarao Badiganti Link: https://lore.kernel.org/r/1592919288-1020-4-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-msm.c | 206 +++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 197 insertions(+), 9 deletions(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index d515a0915e3a..bd5b63f8c76b 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -37,7 +37,9 @@ #define CORE_PWRCTL_IO_LOW BIT(2) #define CORE_PWRCTL_IO_HIGH BIT(3) #define CORE_PWRCTL_BUS_SUCCESS BIT(0) +#define CORE_PWRCTL_BUS_FAIL BIT(1) #define CORE_PWRCTL_IO_SUCCESS BIT(2) +#define CORE_PWRCTL_IO_FAIL BIT(3) #define REQ_BUS_OFF BIT(0) #define REQ_BUS_ON BIT(1) #define REQ_IO_LOW BIT(2) @@ -127,6 +129,9 @@ /* Timeout value to avoid infinite waiting for pwr_irq */ #define MSM_PWR_IRQ_TIMEOUT_MS 5000 +/* Max load for eMMC Vdd-io supply */ +#define MMC_VQMMC_MAX_LOAD_UA 325000 + #define msm_host_readl(msm_host, host, offset) \ msm_host->var_ops->msm_readl_relaxed(host, offset) @@ -278,6 +283,7 @@ struct sdhci_msm_host { bool uses_tassadar_dll; u32 dll_config; u32 ddr_config; + bool vqmmc_enabled; }; static const struct sdhci_msm_offset *sdhci_priv_msm_offset(struct sdhci_host *host) @@ -1347,6 +1353,95 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, sdhci_msm_hs400(host, &mmc->ios); } +static int sdhci_msm_set_vmmc(struct mmc_host *mmc) +{ + if (IS_ERR(mmc->supply.vmmc)) + return 0; + + return mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, mmc->ios.vdd); +} + +static int msm_toggle_vqmmc(struct sdhci_msm_host *msm_host, + struct mmc_host *mmc, bool level) +{ + int ret; + struct mmc_ios ios; + + if (msm_host->vqmmc_enabled == level) + return 0; + + if (level) { + /* Set the IO voltage regulator to default voltage level */ + if (msm_host->caps_0 & CORE_3_0V_SUPPORT) + ios.signal_voltage = MMC_SIGNAL_VOLTAGE_330; + else if (msm_host->caps_0 & CORE_1_8V_SUPPORT) + ios.signal_voltage = MMC_SIGNAL_VOLTAGE_180; + + if (msm_host->caps_0 & CORE_VOLT_SUPPORT) { + ret = mmc_regulator_set_vqmmc(mmc, &ios); + if (ret < 0) { + dev_err(mmc_dev(mmc), "%s: vqmmc set volgate failed: %d\n", + mmc_hostname(mmc), ret); + goto out; + } + } + ret = regulator_enable(mmc->supply.vqmmc); + } else { + ret = regulator_disable(mmc->supply.vqmmc); + } + + if (ret) + dev_err(mmc_dev(mmc), "%s: vqmm %sable failed: %d\n", + mmc_hostname(mmc), level ? "en":"dis", ret); + else + msm_host->vqmmc_enabled = level; +out: + return ret; +} + +static int msm_config_vqmmc_mode(struct sdhci_msm_host *msm_host, + struct mmc_host *mmc, bool hpm) +{ + int load, ret; + + load = hpm ? MMC_VQMMC_MAX_LOAD_UA : 0; + ret = regulator_set_load(mmc->supply.vqmmc, load); + if (ret) + dev_err(mmc_dev(mmc), "%s: vqmmc set load failed: %d\n", + mmc_hostname(mmc), ret); + return ret; +} + +static int sdhci_msm_set_vqmmc(struct sdhci_msm_host *msm_host, + struct mmc_host *mmc, bool level) +{ + int ret; + bool always_on; + + if (IS_ERR(mmc->supply.vqmmc) || + (mmc->ios.power_mode == MMC_POWER_UNDEFINED)) + return 0; + /* + * For eMMC don't turn off Vqmmc, Instead just configure it in LPM + * and HPM modes by setting the corresponding load. + * + * Till eMMC is initialized (i.e. always_on == 0), just turn on/off + * Vqmmc. Vqmmc gets turned off only if init fails and mmc_power_off + * gets invoked. Once eMMC is initialized (i.e. always_on == 1), + * Vqmmc should remain ON, So just set the load instead of turning it + * off/on. + */ + always_on = !mmc_card_is_removable(mmc) && + mmc->card && mmc_card_mmc(mmc->card); + + if (always_on) + ret = msm_config_vqmmc_mode(msm_host, mmc, level); + else + ret = msm_toggle_vqmmc(msm_host, mmc, level); + + return ret; +} + static inline void sdhci_msm_init_pwr_irq_wait(struct sdhci_msm_host *msm_host) { init_waitqueue_head(&msm_host->pwr_irq_wait); @@ -1450,8 +1545,9 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); + struct mmc_host *mmc = host->mmc; u32 irq_status, irq_ack = 0; - int retry = 10; + int retry = 10, ret; u32 pwr_state = 0, io_level = 0; u32 config; const struct sdhci_msm_offset *msm_offset = msm_host->offset; @@ -1489,21 +1585,42 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) if (irq_status & CORE_PWRCTL_BUS_ON) { pwr_state = REQ_BUS_ON; io_level = REQ_IO_HIGH; - irq_ack |= CORE_PWRCTL_BUS_SUCCESS; } if (irq_status & CORE_PWRCTL_BUS_OFF) { pwr_state = REQ_BUS_OFF; io_level = REQ_IO_LOW; - irq_ack |= CORE_PWRCTL_BUS_SUCCESS; } + + if (pwr_state) { + ret = sdhci_msm_set_vmmc(mmc); + if (!ret) + ret = sdhci_msm_set_vqmmc(msm_host, mmc, + pwr_state & REQ_BUS_ON); + if (!ret) + irq_ack |= CORE_PWRCTL_BUS_SUCCESS; + else + irq_ack |= CORE_PWRCTL_BUS_FAIL; + } + /* Handle IO LOW/HIGH */ - if (irq_status & CORE_PWRCTL_IO_LOW) { + if (irq_status & CORE_PWRCTL_IO_LOW) io_level = REQ_IO_LOW; - irq_ack |= CORE_PWRCTL_IO_SUCCESS; - } - if (irq_status & CORE_PWRCTL_IO_HIGH) { + + if (irq_status & CORE_PWRCTL_IO_HIGH) io_level = REQ_IO_HIGH; + + if (io_level) irq_ack |= CORE_PWRCTL_IO_SUCCESS; + + if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) { + ret = mmc_regulator_set_vqmmc(mmc, &mmc->ios); + if (ret < 0) { + dev_err(mmc_dev(mmc), "%s: IO_level setting failed(%d). signal_voltage: %d, vdd: %d irq_status: 0x%08x\n", + mmc_hostname(mmc), ret, + mmc->ios.signal_voltage, mmc->ios.vdd, + irq_status); + irq_ack |= CORE_PWRCTL_IO_FAIL; + } } /* @@ -1552,7 +1669,7 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) if (io_level) msm_host->curr_io_level = io_level; - pr_debug("%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n", + dev_dbg(mmc_dev(mmc), "%s: %s: Handled IRQ(%d), irq_status=0x%x, ack=0x%x\n", mmc_hostname(msm_host->mmc), __func__, irq, irq_status, irq_ack); } @@ -1882,6 +1999,71 @@ static void sdhci_msm_reset(struct sdhci_host *host, u8 mask) sdhci_reset(host, mask); } +static int sdhci_msm_register_vreg(struct sdhci_msm_host *msm_host) +{ + int ret; + + ret = mmc_regulator_get_supply(msm_host->mmc); + if (ret) + return ret; + + sdhci_msm_set_regulator_caps(msm_host); + + return 0; +} + +static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + u16 ctrl, status; + + /* + * Signal Voltage Switching is only applicable for Host Controllers + * v3.00 and above. + */ + if (host->version < SDHCI_SPEC_300) + return 0; + + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + + switch (ios->signal_voltage) { + case MMC_SIGNAL_VOLTAGE_330: + if (!(host->flags & SDHCI_SIGNALING_330)) + return -EINVAL; + + /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ + ctrl &= ~SDHCI_CTRL_VDD_180; + break; + case MMC_SIGNAL_VOLTAGE_180: + if (!(host->flags & SDHCI_SIGNALING_180)) + return -EINVAL; + + /* Enable 1.8V Signal Enable in the Host Control2 register */ + ctrl |= SDHCI_CTRL_VDD_180; + break; + + default: + return -EINVAL; + } + + sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); + + /* Wait for 5ms */ + usleep_range(5000, 5500); + + /* regulator output should be stable within 5 ms */ + status = ctrl & SDHCI_CTRL_VDD_180; + ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if ((ctrl & SDHCI_CTRL_VDD_180) == status) + return 0; + + dev_warn(mmc_dev(mmc), "%s: Regulator output did not became stable\n", + mmc_hostname(mmc)); + + return -EAGAIN; +} + #define DRIVER_NAME "sdhci_msm" #define SDHCI_MSM_DUMP(f, x...) \ pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) @@ -1968,6 +2150,7 @@ static const struct sdhci_ops sdhci_msm_ops = { .write_b = sdhci_msm_writeb, .irq = sdhci_msm_cqe_irq, .dump_vendor_regs = sdhci_msm_dump_vendor_regs, + .set_power = sdhci_set_power_noreg, }; static const struct sdhci_pltfm_data sdhci_msm_pdata = { @@ -2182,6 +2365,10 @@ static int sdhci_msm_probe(struct platform_device *pdev) if (core_major == 1 && core_minor >= 0x49) msm_host->updated_ddr_cfg = true; + ret = sdhci_msm_register_vreg(msm_host); + if (ret) + goto clk_disable; + /* * Power on reset state may trigger power irq if previous status of * PWRCTL was either BUS_ON or IO_HIGH_V. So before enabling pwr irq @@ -2226,6 +2413,8 @@ static int sdhci_msm_probe(struct platform_device *pdev) MSM_MMC_AUTOSUSPEND_DELAY_MS); pm_runtime_use_autosuspend(&pdev->dev); + host->mmc_host_ops.start_signal_voltage_switch = + sdhci_msm_start_signal_voltage_switch; host->mmc_host_ops.execute_tuning = sdhci_msm_execute_tuning; if (of_property_read_bool(node, "supports-cqe")) ret = sdhci_msm_cqe_add_host(host, pdev); @@ -2233,7 +2422,6 @@ static int sdhci_msm_probe(struct platform_device *pdev) ret = sdhci_add_host(host); if (ret) goto pm_runtime_disable; - sdhci_msm_set_regulator_caps(msm_host); pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); -- cgit v1.2.3 From 4f7872ae920fccf6a07ca64cc40792bd6be0d0d5 Mon Sep 17 00:00:00 2001 From: Pali Rohár Date: Mon, 29 Jun 2020 09:21:44 +0200 Subject: mmc: sdio: Move SDIO IDs from rsi_sdio driver to common include file MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Define appropriate macro names for consistency with other macros. Signed-off-by: Pali Rohár Link: https://lore.kernel.org/r/20200629072144.24351-1-pali@kernel.org Signed-off-by: Ulf Hansson --- drivers/net/wireless/rsi/rsi_91x_sdio.c | 8 ++++---- drivers/net/wireless/rsi/rsi_sdio.h | 4 ---- include/linux/mmc/sdio_ids.h | 4 ++++ 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/net/wireless/rsi/rsi_91x_sdio.c b/drivers/net/wireless/rsi/rsi_91x_sdio.c index 5d6143a55187..a04ff75c409f 100644 --- a/drivers/net/wireless/rsi/rsi_91x_sdio.c +++ b/drivers/net/wireless/rsi/rsi_91x_sdio.c @@ -1038,10 +1038,10 @@ static int rsi_probe(struct sdio_func *pfunction, goto fail_free_adapter; } - if (pfunction->device == RSI_SDIO_PID_9113) { + if (pfunction->device == SDIO_DEVICE_ID_RSI_9113) { rsi_dbg(ERR_ZONE, "%s: 9113 module detected\n", __func__); adapter->device_model = RSI_DEV_9113; - } else if (pfunction->device == RSI_SDIO_PID_9116) { + } else if (pfunction->device == SDIO_DEVICE_ID_RSI_9116) { rsi_dbg(ERR_ZONE, "%s: 9116 module detected\n", __func__); adapter->device_model = RSI_DEV_9116; } else { @@ -1526,8 +1526,8 @@ static const struct dev_pm_ops rsi_pm_ops = { #endif static const struct sdio_device_id rsi_dev_table[] = { - { SDIO_DEVICE(RSI_SDIO_VENDOR_ID, RSI_SDIO_PID_9113) }, - { SDIO_DEVICE(RSI_SDIO_VENDOR_ID, RSI_SDIO_PID_9116) }, + { SDIO_DEVICE(SDIO_VENDOR_ID_RSI, SDIO_DEVICE_ID_RSI_9113) }, + { SDIO_DEVICE(SDIO_VENDOR_ID_RSI, SDIO_DEVICE_ID_RSI_9116) }, { /* Blank */}, }; diff --git a/drivers/net/wireless/rsi/rsi_sdio.h b/drivers/net/wireless/rsi/rsi_sdio.h index c5cfb6238f73..9afc1d0d2684 100644 --- a/drivers/net/wireless/rsi/rsi_sdio.h +++ b/drivers/net/wireless/rsi/rsi_sdio.h @@ -28,10 +28,6 @@ #include #include "rsi_main.h" -#define RSI_SDIO_VENDOR_ID 0x041B -#define RSI_SDIO_PID_9113 0x9330 -#define RSI_SDIO_PID_9116 0x9116 - enum sdio_interrupt_type { BUFFER_FULL = 0x0, BUFFER_AVAILABLE = 0x2, diff --git a/include/linux/mmc/sdio_ids.h b/include/linux/mmc/sdio_ids.h index 15ed8ce9d394..ab41801c5f51 100644 --- a/include/linux/mmc/sdio_ids.h +++ b/include/linux/mmc/sdio_ids.h @@ -118,6 +118,10 @@ #define SDIO_DEVICE_ID_SIANO_NOVA_A0 0x1100 #define SDIO_DEVICE_ID_SIANO_STELLAR 0x5347 +#define SDIO_VENDOR_ID_RSI 0x041b +#define SDIO_DEVICE_ID_RSI_9113 0x9330 +#define SDIO_DEVICE_ID_RSI_9116 0x9116 + #define SDIO_VENDOR_ID_TI_WL1251 0x104c #define SDIO_DEVICE_ID_TI_WL1251 0x9066 -- cgit v1.2.3 From 6dca9a9c0cd55d08d83c3e3c0d9913f1dd86302a Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 21 May 2020 16:01:04 +0900 Subject: mmc: tmio: core: Add end operation into tmio_mmc_dma_ops Related drivers like renesas_sdhi_internal_dmac are possible to lack dma unmaping in error cases (for example response timeout). Since tmio_mmc_finish_request() will be always called in any case, to fix the issue, add end operation into struct tmio_mmc_dma_ops and call the operation in tmio_mmc_finish_request() to call dma_ummap API by the related drivers correctly. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1590044466-28372-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Tested-by: Wolfram Sang Signed-off-by: Ulf Hansson --- drivers/mmc/host/tmio_mmc.h | 3 +++ drivers/mmc/host/tmio_mmc_core.c | 8 ++++++++ 2 files changed, 11 insertions(+) diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h index b4cf10109162..0a4f36500add 100644 --- a/drivers/mmc/host/tmio_mmc.h +++ b/drivers/mmc/host/tmio_mmc.h @@ -118,6 +118,9 @@ struct tmio_mmc_dma_ops { void (*release)(struct tmio_mmc_host *host); void (*abort)(struct tmio_mmc_host *host); void (*dataend)(struct tmio_mmc_host *host); + + /* optional */ + void (*end)(struct tmio_mmc_host *host); /* held host->lock */ }; struct tmio_mmc_host { diff --git a/drivers/mmc/host/tmio_mmc_core.c b/drivers/mmc/host/tmio_mmc_core.c index d7fde57c78c1..946fb013c610 100644 --- a/drivers/mmc/host/tmio_mmc_core.c +++ b/drivers/mmc/host/tmio_mmc_core.c @@ -57,6 +57,12 @@ static inline void tmio_mmc_start_dma(struct tmio_mmc_host *host, host->dma_ops->start(host, data); } +static inline void tmio_mmc_end_dma(struct tmio_mmc_host *host) +{ + if (host->dma_ops && host->dma_ops->end) + host->dma_ops->end(host); +} + static inline void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable) { if (host->dma_ops) @@ -797,6 +803,8 @@ static void tmio_mmc_finish_request(struct tmio_mmc_host *host) spin_lock_irqsave(&host->lock, flags); + tmio_mmc_end_dma(host); + mrq = host->mrq; if (IS_ERR_OR_NULL(mrq)) { spin_unlock_irqrestore(&host->lock, flags); -- cgit v1.2.3 From 2b26e34e9af3fa24fa1266e9ea2d66a1f7d62dc0 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 21 May 2020 16:01:05 +0900 Subject: mmc: renesas_sdhi_internal_dmac: clean up the code for dma complete To add end() operation in the future, clean the code of renesas_sdhi_internal_dmac_complete_tasklet_fn(). No behavior change. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1590044466-28372-3-git-send-email-yoshihiro.shimoda.uh@renesas.com Tested-by: Wolfram Sang Signed-off-by: Ulf Hansson --- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c index 47ac53e91241..201b8ed37f2e 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -229,15 +229,12 @@ static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) DTRAN_CTRL_DM_START); } -static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) +static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) { - struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; enum dma_data_direction dir; - spin_lock_irq(&host->lock); - if (!host->data) - goto out; + return false; if (host->data->flags & MMC_DATA_READ) dir = DMA_FROM_DEVICE; @@ -250,6 +247,17 @@ static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) if (dir == DMA_FROM_DEVICE) clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); + return true; +} + +static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) +{ + struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; + + spin_lock_irq(&host->lock); + if (!renesas_sdhi_internal_dmac_complete(host)) + goto out; + tmio_mmc_do_data_irq(host); out: spin_unlock_irq(&host->lock); -- cgit v1.2.3 From 58a91d96d0bfdcbed7f9795220e42e02ed3f2f89 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Thu, 21 May 2020 16:01:06 +0900 Subject: mmc: renesas_sdhi_internal_dmac: Fix dma unmapping in error cases If this controller doesn't issue interrupt for response of command, this driver lacks to call dma_unmap_sg(). So, fix the issue by using end() of struct tmio_mmc_dma_ops. Reported-by: Takeshi Saito Fixes: 2a68ea7896e3 ("mmc: renesas-sdhi: add support for R-Car Gen3 SDHI DMAC") Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1590044466-28372-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Tested-by: Wolfram Sang Signed-off-by: Ulf Hansson --- drivers/mmc/host/renesas_sdhi_internal_dmac.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c index 201b8ed37f2e..32ab991544ef 100644 --- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c +++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c @@ -233,6 +233,9 @@ static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) { enum dma_data_direction dir; + if (!host->dma_on) + return false; + if (!host->data) return false; @@ -247,6 +250,8 @@ static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) if (dir == DMA_FROM_DEVICE) clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); + host->dma_on = false; + return true; } @@ -263,6 +268,12 @@ out: spin_unlock_irq(&host->lock); } +static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host) +{ + if (host->data) + renesas_sdhi_internal_dmac_complete(host); +} + static void renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdata) @@ -300,6 +311,7 @@ static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { .release = renesas_sdhi_internal_dmac_release_dma, .abort = renesas_sdhi_internal_dmac_abort_dma, .dataend = renesas_sdhi_internal_dmac_dataend_dma, + .end = renesas_sdhi_internal_dmac_end_dma, }; /* -- cgit v1.2.3 From 53e888d14b4b66c5b30e4b726ba431e0ac2dd8b0 Mon Sep 17 00:00:00 2001 From: Hulk Robot Date: Thu, 2 Jul 2020 10:03:47 +0800 Subject: mmc: sdhci-msm: Make function sdhci_msm_dump_vendor_regs() static Fix sparse build warning: drivers/mmc/host/sdhci-msm.c:1888:6: warning: symbol 'sdhci_msm_dump_vendor_regs' was not declared. Should it be static? Signed-off-by: Hulk Robot Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/20200702020347.77214-1-weiyongjun1@huawei.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-msm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index bd5b63f8c76b..63e2b354d232 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -2068,7 +2068,7 @@ static int sdhci_msm_start_signal_voltage_switch(struct mmc_host *mmc, #define SDHCI_MSM_DUMP(f, x...) \ pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) -void sdhci_msm_dump_vendor_regs(struct sdhci_host *host) +static void sdhci_msm_dump_vendor_regs(struct sdhci_host *host) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host); -- cgit v1.2.3 From 482cedd2e5872f5a1a17fd8b03c6e5b37f320425 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:48 +0100 Subject: mmc: core: Mark fixups as __maybe_unused MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Not all source files which include quirks.h make use of the all of the available fixup information. When this happens the compiler complains that some constant variables are defined by never used. We can fix this by telling the compiler that this intentional by simply marking them as __maybe_unused. Fixes the following W=1 kernel build warnings: In file included from drivers/mmc/core/sdio.c:22: drivers/mmc/core/quirks.h:105:31: warning: ‘mmc_ext_csd_fixups’ defined but not used [-Wunused-const-variable=] 105 | static const struct mmc_fixup mmc_ext_csd_fixups[] = { | ^~~~~~~~~~~~~~~~~~ drivers/mmc/core/quirks.h:17:31: warning: ‘mmc_blk_fixups’ defined but not used [-Wunused-const-variable=] 17 | static const struct mmc_fixup mmc_blk_fixups[] = { | ^~~~~~~~~~~~~~ In file included from drivers/mmc/core/mmc.c:25: drivers/mmc/core/quirks.h:123:31: warning: ‘sdio_fixup_methods’ defined but not used [-Wunused-const-variable=] 123 | static const struct mmc_fixup sdio_fixup_methods[] = { | ^~~~~~~~~~~~~~~~~~ drivers/mmc/core/quirks.h:17:31: warning: ‘mmc_blk_fixups’ defined but not used [-Wunused-const-variable=] 17 | static const struct mmc_fixup mmc_blk_fixups[] = { | ^~~~~~~~~~~~~~ Cc: Andrei Warkentin Cc: Martin Mares Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20200701124702.908713-2-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/core/quirks.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/core/quirks.h b/drivers/mmc/core/quirks.h index 472fa2fdcf13..d68e6e513a4f 100644 --- a/drivers/mmc/core/quirks.h +++ b/drivers/mmc/core/quirks.h @@ -14,7 +14,7 @@ #include "card.h" -static const struct mmc_fixup mmc_blk_fixups[] = { +static const struct mmc_fixup __maybe_unused mmc_blk_fixups[] = { #define INAND_CMD38_ARG_EXT_CSD 113 #define INAND_CMD38_ARG_ERASE 0x00 #define INAND_CMD38_ARG_TRIM 0x01 @@ -102,7 +102,7 @@ static const struct mmc_fixup mmc_blk_fixups[] = { END_FIXUP }; -static const struct mmc_fixup mmc_ext_csd_fixups[] = { +static const struct mmc_fixup __maybe_unused mmc_ext_csd_fixups[] = { /* * Certain Hynix eMMC 4.41 cards might get broken when HPI feature * is used so disable the HPI feature for such buggy cards. @@ -120,7 +120,7 @@ static const struct mmc_fixup mmc_ext_csd_fixups[] = { }; -static const struct mmc_fixup sdio_fixup_methods[] = { +static const struct mmc_fixup __maybe_unused sdio_fixup_methods[] = { SDIO_FIXUP(SDIO_VENDOR_ID_TI_WL1251, SDIO_DEVICE_ID_TI_WL1251, add_quirk, MMC_QUIRK_NONSTD_FUNC_IF), -- cgit v1.2.3 From a79c3f40c7c87d4238ae097fad84291dc69f2c1e Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:49 +0100 Subject: mmc: core: Provide description for sdio_set_host_pm_flags()'s 'flag' arg Add missing kerneldoc entry for sdio_set_host_pm_flags()'s 'flag' function argument. Fixes the following W=1 kernel build warning: kernel/drivers/mmc/core/sdio_io.c:722: warning: Function parameter or member 'flags' not described in 'sdio_set_host_pm_flags' Cc: Pierre Ossman Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20200701124702.908713-3-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/core/sdio_io.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/mmc/core/sdio_io.c b/drivers/mmc/core/sdio_io.c index cba54dfb04f7..79dbf90216b5 100644 --- a/drivers/mmc/core/sdio_io.c +++ b/drivers/mmc/core/sdio_io.c @@ -709,6 +709,7 @@ EXPORT_SYMBOL_GPL(sdio_get_host_pm_caps); /** * sdio_set_host_pm_flags - set wanted host power management capabilities * @func: SDIO function attached to host + * @flags: Power Management flags to set * * Set a capability bitmask corresponding to wanted host controller * power management features for the upcoming suspend state. -- cgit v1.2.3 From 33fc1ebe509ad761937434ce43e1552ce50047ce Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:50 +0100 Subject: mmc: core: Add missing documetation for 'mmc' and 'ios' Remainder of the kerneldoc descriptions look present and correct. Fixes the following W=1 kernel build warnings: drivers/mmc/core/regulator.c:178: warning: Function parameter or member 'mmc' not described in 'mmc_regulator_set_vqmmc' drivers/mmc/core/regulator.c:178: warning: Function parameter or member 'ios' not described in 'mmc_regulator_set_vqmmc' Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20200701124702.908713-4-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/core/regulator.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/core/regulator.c b/drivers/mmc/core/regulator.c index 96b1d15045d6..609201a467ef 100644 --- a/drivers/mmc/core/regulator.c +++ b/drivers/mmc/core/regulator.c @@ -159,6 +159,8 @@ static int mmc_regulator_set_voltage_if_supported(struct regulator *regulator, /** * mmc_regulator_set_vqmmc - Set VQMMC as per the ios + * @mmc: the host to regulate + * @ios: io bus settings * * For 3.3V signaling, we try to match VQMMC to VMMC as closely as possible. * That will match the behavior of old boards where VQMMC and VMMC were supplied -- cgit v1.2.3 From 46525bcc5c18f271ec522f47583066e82e964a08 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:51 +0100 Subject: mmc: sdhci-s3c: Provide documentation for missing struct properties Describe properties; ext_cd_irq, clk_rates and no_divider (x2). Squashes the following W=1 kernel build warnings: drivers/mmc/host/sdhci-s3c.c:126: warning: Function parameter or member 'ext_cd_irq' not described in 'sdhci_s3c' drivers/mmc/host/sdhci-s3c.c:126: warning: Function parameter or member 'clk_rates' not described in 'sdhci_s3c' drivers/mmc/host/sdhci-s3c.c:126: warning: Function parameter or member 'no_divider' not described in 'sdhci_s3c' drivers/mmc/host/sdhci-s3c.c:139: warning: Function parameter or member 'no_divider' not described in 'sdhci_s3c_drv_data' Cc: Adrian Hunter Cc: Ben Dooks Cc: Jaehoon Chung Signed-off-by: Lee Jones Reviewed-by: Jaehoon Chung Link: https://lore.kernel.org/r/20200701124702.908713-5-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-s3c.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/host/sdhci-s3c.c b/drivers/mmc/host/sdhci-s3c.c index 64200c78e90d..9194bb73e601 100644 --- a/drivers/mmc/host/sdhci-s3c.c +++ b/drivers/mmc/host/sdhci-s3c.c @@ -107,8 +107,11 @@ * @ioarea: The resource created when we claimed the IO area. * @pdata: The platform data for this controller. * @cur_clk: The index of the current bus clock. + * @ext_cd_irq: External card detect interrupt. * @clk_io: The clock for the internal bus interface. + * @clk_rates: Clock frequencies. * @clk_bus: The clocks that are available for the SD/MMC bus clock. + * @no_divider: No or non-standard internal clock divider. */ struct sdhci_s3c { struct sdhci_host *host; @@ -128,6 +131,7 @@ struct sdhci_s3c { /** * struct sdhci_s3c_driver_data - S3C SDHCI platform specific driver data * @sdhci_quirks: sdhci host specific quirks. + * @no_divider: no or non-standard internal clock divider. * * Specifies platform specific configuration of sdhci controller. * Note: A structure for driver specific platform data is used for future -- cgit v1.2.3 From 6ec5a7b72e2afc2ac23c6ef3156d7a092b0086b0 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:52 +0100 Subject: mmc: mtk-sd: Demote msdc_recheck_sdio_irq() function header No other function in the file is documented using kerneldoc and no effort to document the function arguments have been made. It's a bit of an oddity to say the least. Let's downgrade it from kerneldoc to a standard comment block instead. Fixes the following W=1 kernel build warning: drivers/mmc/host/mtk-sd.c:1030: warning: Function parameter or member 'host' not described in 'msdc_recheck_sdio_irq' Cc: Chaotian Jing Cc: Matthias Brugger Cc: linux-mediatek@lists.infradead.org Signed-off-by: Lee Jones Reviewed-by: Matthias Brugger Link: https://lore.kernel.org/r/20200701124702.908713-6-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/mtk-sd.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 39e7fc54c438..49ac802ebbfe 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -1018,13 +1018,12 @@ static int msdc_auto_cmd_done(struct msdc_host *host, int events, return cmd->error; } -/** +/* * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost * * Host controller may lost interrupt in some special case. * Add SDIO irq recheck mechanism to make sure all interrupts * can be processed immediately - * */ static void msdc_recheck_sdio_irq(struct msdc_host *host) { -- cgit v1.2.3 From f51874b7ec92cb5b11c6484b424bf530e0851ed2 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:53 +0100 Subject: mmc: atmel-mci: Provide 2 new and correct 1 existing property description 'sg_len' and 'dma_conf' are missing correct kerneldoc documentation and 'buf_phys_addr' was misspelled. Correcting these issues fixes the following W=1 kernel build issues: mmc/host/atmel-mci.c:352: warning: Function parameter or member 'sg_len' not described in 'atmel_mci' mmc/host/atmel-mci.c:352: warning: Function parameter or member 'buf_phys_addr' not described in 'atmel_mci' mmc/host/atmel-mci.c:352: warning: Function parameter or member 'dma_conf' not described in 'atmel_mci' Cc: Ludovic Desroches Cc: Nicolas Ferre Cc: Alexandre Belloni Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20200701124702.908713-7-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/atmel-mci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c index 5cb692687698..300901415aa2 100644 --- a/drivers/mmc/host/atmel-mci.c +++ b/drivers/mmc/host/atmel-mci.c @@ -225,12 +225,13 @@ struct atmel_mci_dma { * @lock: Spinlock protecting the queue and associated data. * @regs: Pointer to MMIO registers. * @sg: Scatterlist entry currently being processed by PIO or PDC code. + * @sg_len: Size of the scatterlist * @pio_offset: Offset into the current scatterlist entry. * @buffer: Buffer used if we don't have the r/w proof capability. We * don't have the time to switch pdc buffers so we have to use only * one buffer for the full transaction. * @buf_size: size of the buffer. - * @phys_buf_addr: buffer address needed for pdc. + * @buf_phys_addr: buffer address needed for pdc. * @cur_slot: The slot which is currently using the controller. * @mrq: The request currently being processed on @cur_slot, * or NULL if the controller is idle. @@ -240,6 +241,7 @@ struct atmel_mci_dma { * @data_size: just data->blocks * data->blksz. * @dma: DMA client state. * @data_chan: DMA channel being used for the current data transfer. + * @dma_conf: Configuration for the DMA slave * @cmd_status: Snapshot of SR taken upon completion of the current * command. Only valid when EVENT_CMD_COMPLETE is pending. * @data_status: Snapshot of SR taken upon completion of the current -- cgit v1.2.3 From 22374e9f2996b6a4460baa272121fbd2b47ea717 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:54 +0100 Subject: mmc: core: Correct misspelling of 'mq' in mmc_init_request()'s docs Correcting this misspelling squashes the following W=1 build warning(s): mmc/core/queue.c:212: warning: Function parameter or member 'mq' not described in '__mmc_init_request' mmc/core/queue.c:212: warning: Excess function parameter 'q' description in '__mmc_init_request' Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20200701124702.908713-8-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/core/queue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/core/queue.c b/drivers/mmc/core/queue.c index 4b1eb89b401d..6c022ef0f84d 100644 --- a/drivers/mmc/core/queue.c +++ b/drivers/mmc/core/queue.c @@ -203,7 +203,7 @@ static unsigned int mmc_get_max_segments(struct mmc_host *host) /** * mmc_init_request() - initialize the MMC-specific per-request data - * @q: the request queue + * @mq: the request queue * @req: the request * @gfp: memory allocation policy */ -- cgit v1.2.3 From 306c59cbe4bb717803126d6ede874998193b49b3 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:55 +0100 Subject: mmc: dw_mmc-exynos: Add kerneldoc descriptions of for 'dev' args Provide missing documentation for dw_mci_exynos_suspend_noirq() and dw_mci_exynos_resume_noirq() function headers. Fixes the following W=1 kernel build warnings: drivers/mmc/host/dw_mmc-exynos.c:184: warning: Function parameter or member 'dev' not described in 'dw_mci_exynos_suspend_noirq' drivers/mmc/host/dw_mmc-exynos.c:200: warning: Function parameter or member 'dev' not described in 'dw_mci_exynos_resume_noirq' Cc: Jaehoon Chung Cc: Kukjin Kim Cc: Krzysztof Kozlowski Cc: Thomas Abraham Cc: linux-samsung-soc@vger.kernel.org Signed-off-by: Lee Jones Reviewed-by: Jaehoon Chung Link: https://lore.kernel.org/r/20200701124702.908713-9-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/dw_mmc-exynos.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index 5e3d95b63676..bd59186f59b3 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -176,6 +176,7 @@ static int dw_mci_exynos_runtime_resume(struct device *dev) #ifdef CONFIG_PM_SLEEP /** * dw_mci_exynos_suspend_noirq - Exynos-specific suspend code + * @dev: Device to suspend (this device) * * This ensures that device will be in runtime active state in * dw_mci_exynos_resume_noirq after calling pm_runtime_force_resume() @@ -188,6 +189,7 @@ static int dw_mci_exynos_suspend_noirq(struct device *dev) /** * dw_mci_exynos_resume_noirq - Exynos-specific resume code + * @dev: Device to resume (this device) * * On exynos5420 there is a silicon errata that will sometimes leave the * WAKEUP_INT bit in the CLKSEL register asserted. This bit is 1 to indicate -- cgit v1.2.3 From 679209b3c1b00b56d18c17bfe0112fc58e14d6cb Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:56 +0100 Subject: mmc: rtsx_pci_sdmmc: Remove set but unused variable 'err' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Seeing as sd_wait_data_idle() returns void and only a very specific read value is checked, there doesn't seem to be a good reason to check the return value of rtsx_pci_read_register(). So remove the assignment and definition of 'err'. Squashes the following W=1 kernel build warning: drivers/mmc/host/rtsx_pci_sdmmc.c: In function ‘sd_wait_data_idle’: drivers/mmc/host/rtsx_pci_sdmmc.c:678:6: warning: variable ‘err’ set but not used [-Wunused-but-set-variable] 678 | int err, i; | ^~~ Cc: Wei WANG Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20200701124702.908713-10-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/rtsx_pci_sdmmc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/rtsx_pci_sdmmc.c b/drivers/mmc/host/rtsx_pci_sdmmc.c index 5a71f6678fd3..dc0dbd64a2a7 100644 --- a/drivers/mmc/host/rtsx_pci_sdmmc.c +++ b/drivers/mmc/host/rtsx_pci_sdmmc.c @@ -675,11 +675,11 @@ static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) { - int err, i; + int i; u8 val = 0; for (i = 0; i < 100; i++) { - err = rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); + rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); if (val & SD_DATA_IDLE) return; -- cgit v1.2.3 From d463cf4ea471781caa266315ae770f9808101957 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:57 +0100 Subject: mmc: rtsx_usb_sdmmc: Remove set but unused variable 'err' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Seeing as sd_wait_data_idle() returns void and only a very specific read value is checked, there doesn't seem to be a good reason to check the return value of rtsx_pci_read_register(). So remove the assignment and definition of 'err'. Squashes the following W=1 kernel build warning: drivers/mmc/host/rtsx_usb_sdmmc.c: In function ‘sd_wait_data_idle’: drivers/mmc/host/rtsx_usb_sdmmc.c:657:6: warning: variable ‘err’ set but not used [-Wunused-but-set-variable] 657 | int err, i; | ^~~ Cc: Roger Tseng Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20200701124702.908713-11-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/rtsx_usb_sdmmc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/mmc/host/rtsx_usb_sdmmc.c b/drivers/mmc/host/rtsx_usb_sdmmc.c index a7084c50ad65..7225d9312af8 100644 --- a/drivers/mmc/host/rtsx_usb_sdmmc.c +++ b/drivers/mmc/host/rtsx_usb_sdmmc.c @@ -654,12 +654,11 @@ static u8 sd_search_final_phase(struct rtsx_usb_sdmmc *host, u32 phase_map) static void sd_wait_data_idle(struct rtsx_usb_sdmmc *host) { - int err, i; + int i; u8 val = 0; for (i = 0; i < 100; i++) { - err = rtsx_usb_ep0_read_register(host->ucr, - SD_DATA_STATE, &val); + rtsx_usb_ep0_read_register(host->ucr, SD_DATA_STATE, &val); if (val & SD_DATA_IDLE) return; -- cgit v1.2.3 From 654e8750f28bc4051ef21dbdeada7ec3b999e000 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:46:58 +0100 Subject: mmc: sdhci-of-arasan: Correct formatting and provide missing function arg(s) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Kerneldoc expects arg descriptions to be in the format '@.*: '. If either the '@' or the ':' is omitted then kerneldoc complains that the description is missing. Add the missing ':' here and provide a new description for 'value'. Fixes the following kernel build W=1 warnings: drivers/mmc/host/sdhci-of-arasan.c:1394: warning: Function parameter or member 'host' not described in 'sdhci_arasan_update_support64b' drivers/mmc/host/sdhci-of-arasan.c:1394: warning: Function parameter or member 'value' not described in 'sdhci_arasan_update_support64b' drivers/mmc/host/sdhci-msm.c:1887:6: warning: no previous prototype for ‘sdhci_msm_dump_vendor_regs’ [-Wmissing-prototypes] Cc: Adrian Hunter Cc: Michal Simek Cc: Xiaobo Xie Cc: Anton Vorontsov Cc: Soeren Brinkmann Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20200701124702.908713-12-lee.jones@linaro.org Acked-by: Michal Simek Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-of-arasan.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index fb26e743e1fd..5a432f9bf1bb 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -1392,7 +1392,8 @@ static void sdhci_arasan_unregister_sdclk(struct device *dev) * - For Keem Bay, it is required to clear this bit. Its default value is 1'b1. * Keem Bay does not support 64-bit access. * - * @host The sdhci_host + * @host: The sdhci_host + * @value: The value to write */ static void sdhci_arasan_update_support64b(struct sdhci_host *host, u32 value) { -- cgit v1.2.3 From abf4633a171e39c21898fe585d6c5f598c44abf8 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:47:00 +0100 Subject: mmc: sdhci-msm: Demote faux kerneldoc header down to basic comment block __sdhci_msm_set_clock()'s function header is the only one in kerneldoc format. Which seems odd as it's not part of an external API and isn't referenced anywhere else. Seeing as there has also been no attempt to describe the expected function arguments either, we're going to assume that this is not actually a bona fide kerneldoc use-case. Fixes the following W=1 kernel build warnings: drivers/mmc/host/sdhci-msm.c:1595: warning: Function parameter or member 'host' not described in '__sdhci_msm_set_clock' drivers/mmc/host/sdhci-msm.c:1595: warning: Function parameter or member 'clock' not described in '__sdhci_msm_set_clock' Cc: Adrian Hunter Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Lee Jones Link: https://lore.kernel.org/r/20200701124702.908713-14-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-msm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 63e2b354d232..333245cf5904 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -1702,7 +1702,7 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host) return SDHCI_MSM_MIN_CLOCK; } -/** +/* * __sdhci_msm_set_clock - sdhci_msm clock control. * * Description: -- cgit v1.2.3 From 2ec2438d2052180984571e4c9065ecd9132a9f91 Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 13:47:01 +0100 Subject: mmc: cqhci: Demote faux kerneldoc header down to basic comment block cqhci_host_alloc_tdl()'s function header is the only one in kerneldoc format. Which seems odd as it's not part of an external API and isn't referenced anywhere else. Seeing as there has also been no attempt to describe the expected function arguments either, we're going to assume that this is not actually a bona fide kerneldoc use-case. Fixes the following W=1 kernel build warning: drivers/mmc/host/cqhci.c:163: warning: Function parameter or member 'cq_host' not described in 'cqhci_host_alloc_tdl' Cc: Adrian Hunter Cc: Ritesh Harjani Cc: Asutosh Das Cc: Venkat Gopalakrishnan Signed-off-by: Lee Jones Acked-by: Adrian Hunter Link: https://lore.kernel.org/r/20200701124702.908713-15-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/cqhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c index 75934f3c117e..8cc277b4ffe9 100644 --- a/drivers/mmc/host/cqhci.c +++ b/drivers/mmc/host/cqhci.c @@ -144,7 +144,7 @@ static void cqhci_dumpregs(struct cqhci_host *cq_host) CQHCI_DUMP(": ===========================================\n"); } -/** +/* * The allocated descriptor table for task, link & transfer descritors * looks like: * |----------| -- cgit v1.2.3 From 2f96126500991f356b9eacdc6611bec78e6253ed Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Wed, 1 Jul 2020 11:23:17 +0100 Subject: arch: arm: mach-omap2: mmc: Move omap_mmc_notify_cover_event() prototype MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When building the kernel with W=1 the build system complains of: drivers/mmc/host/omap.c:854:6: warning: no previous prototype for ‘omap_mmc_notify_cover_event’ [-Wmissing-prototypes] 854 | void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ If we move the prototype into a shared headerfile the build system will be satisfied. Rather than create a whole new headerfile just for this purpose, it makes sense to use the already existing mmc-omap.h. Cc: Ulf Hansson Cc: linux-mmc@vger.kernel.org Cc: Tony Lindgren Cc: linux-omap@vger.kernel.org Signed-off-by: Lee Jones Acked-by: Tony Lindgren Link: https://lore.kernel.org/r/20200701102317.235032-1-lee.jones@linaro.org Signed-off-by: Ulf Hansson --- arch/arm/mach-omap2/mmc.h | 4 ---- include/linux/platform_data/mmc-omap.h | 3 +++ 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-omap2/mmc.h b/arch/arm/mach-omap2/mmc.h index 7f4e053c3434..b5533e93cb63 100644 --- a/arch/arm/mach-omap2/mmc.h +++ b/arch/arm/mach-omap2/mmc.h @@ -16,7 +16,3 @@ static inline int omap_msdi_reset(struct omap_hwmod *oh) return 0; } #endif - -/* called from board-specific card detection service routine */ -extern void omap_mmc_notify_cover_event(struct device *dev, int slot, - int is_closed); diff --git a/include/linux/platform_data/mmc-omap.h b/include/linux/platform_data/mmc-omap.h index 9acf0e87aa9b..f0b8947e6b07 100644 --- a/include/linux/platform_data/mmc-omap.h +++ b/include/linux/platform_data/mmc-omap.h @@ -116,3 +116,6 @@ struct omap_mmc_platform_data { } slots[OMAP_MMC_MAX_SLOTS]; }; + +extern void omap_mmc_notify_cover_event(struct device *dev, int slot, + int is_closed); -- cgit v1.2.3 From 479cb7cfea764d368912927d045aadf50ed2ea34 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Mon, 6 Jul 2020 17:30:31 +0100 Subject: mmc: dw_mmc-exynos: remove redundant initialization of variable 'found' The variable 'found' is being initialized with a value that is never read and it is being updated later with a new value. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King Link: https://lore.kernel.org/r/20200706163031.503431-1-colin.king@canonical.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/dw_mmc-exynos.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-exynos.c b/drivers/mmc/host/dw_mmc-exynos.c index bd59186f59b3..95adeee07217 100644 --- a/drivers/mmc/host/dw_mmc-exynos.c +++ b/drivers/mmc/host/dw_mmc-exynos.c @@ -474,7 +474,7 @@ static int dw_mci_exynos_execute_tuning(struct dw_mci_slot *slot, u32 opcode) struct dw_mci_exynos_priv_data *priv = host->priv; struct mmc_host *mmc = slot->mmc; u8 start_smpl, smpl, candiates = 0; - s8 found = -1; + s8 found; int ret = 0; start_smpl = dw_mci_exynos_get_clksmpl(host); -- cgit v1.2.3 From edfa69ded566d11183206d2d45cb4b90ccb5a56e Mon Sep 17 00:00:00 2001 From: Lee Jones Date: Tue, 7 Jul 2020 07:47:01 +0100 Subject: mmc: sdhci-iproc: Do not define 'struct acpi_device_id' when !CONFIG_ACPI MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Since ACPI_PTR() is used to NULLify the value when !CONFIG_ACPI, 'struct sdhci_iproc_acpi_ids' becomes defined but unused. Fixes the following W=1 kernel build warning: mmc/host/sdhci-iproc.c:297:36: warning: ‘sdhci_iproc_acpi_ids’ defined but not used [-Wunused-const-variable=] Cc: Adrian Hunter Cc: Ray Jui Cc: Scott Branden Cc: bcm-kernel-feedback-list@broadcom.com Signed-off-by: Lee Jones Acked-by: Scott Branden Link: https://lore.kernel.org/r/20200707064701.GC3500@dell Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-iproc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/mmc/host/sdhci-iproc.c b/drivers/mmc/host/sdhci-iproc.c index 225603148d7d..e2d8dfe90077 100644 --- a/drivers/mmc/host/sdhci-iproc.c +++ b/drivers/mmc/host/sdhci-iproc.c @@ -294,12 +294,14 @@ static const struct of_device_id sdhci_iproc_of_match[] = { }; MODULE_DEVICE_TABLE(of, sdhci_iproc_of_match); +#ifdef CONFIG_ACPI static const struct acpi_device_id sdhci_iproc_acpi_ids[] = { { .id = "BRCM5871", .driver_data = (kernel_ulong_t)&iproc_cygnus_data }, { .id = "BRCM5872", .driver_data = (kernel_ulong_t)&iproc_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(acpi, sdhci_iproc_acpi_ids); +#endif static int sdhci_iproc_probe(struct platform_device *pdev) { -- cgit v1.2.3 From b5c833b703cc3507dac2cd8c9197a965724c8d3a Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Wed, 8 Jul 2020 18:41:20 +0530 Subject: mmc: sdhci-msm: Set IO pins in low power state during suspend Configure SDHC IO pins with low power configuration when the driver is in suspend state. Signed-off-by: Veerabhadrarao Badiganti Link: https://lore.kernel.org/r/1594213888-2780-2-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-msm.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c index 333245cf5904..5a33389037cd 100644 --- a/drivers/mmc/host/sdhci-msm.c +++ b/drivers/mmc/host/sdhci-msm.c @@ -15,6 +15,7 @@ #include #include #include +#include #include "sdhci-pltfm.h" #include "cqhci.h" @@ -1353,6 +1354,19 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host, sdhci_msm_hs400(host, &mmc->ios); } +static int sdhci_msm_set_pincfg(struct sdhci_msm_host *msm_host, bool level) +{ + struct platform_device *pdev = msm_host->pdev; + int ret; + + if (level) + ret = pinctrl_pm_select_default_state(&pdev->dev); + else + ret = pinctrl_pm_select_sleep_state(&pdev->dev); + + return ret; +} + static int sdhci_msm_set_vmmc(struct mmc_host *mmc) { if (IS_ERR(mmc->supply.vmmc)) @@ -1596,6 +1610,9 @@ static void sdhci_msm_handle_pwr_irq(struct sdhci_host *host, int irq) if (!ret) ret = sdhci_msm_set_vqmmc(msm_host, mmc, pwr_state & REQ_BUS_ON); + if (!ret) + ret = sdhci_msm_set_pincfg(msm_host, + pwr_state & REQ_BUS_ON); if (!ret) irq_ack |= CORE_PWRCTL_BUS_SUCCESS; else -- cgit v1.2.3 From ba26e91d9f8ee94b49dc24f440d4c5efd403456b Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 7 Jul 2020 20:58:41 +0900 Subject: dt-bindings: mmc: Add full-pwr-cycle-in-suspend property The commit 5a36d6bcdf23 ("mmc: core: Add DT-bindings for MMC_CAP2_FULL_PWR_CYCLE") added the "full-pwr-cycle" property which is possible to perform a full power cycle of the card at any time. However, some environment (like r8a77951-salvator-xs) is possible to perform a full power cycle of the card in suspend via firmware (PSCI on arm-trusted-firmware). So, add a new property for such environment. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1594123122-13156-2-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mmc-controller.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 4931fab34d81..b96da0c7f819 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -169,6 +169,11 @@ properties: description: Full power cycle of the card is supported. + full-pwr-cycle-in-suspend: + $ref: /schemas/types.yaml#/definitions/flag + description: + Full power cycle of the card in suspend is supported. + mmc-ddr-1_2v: $ref: /schemas/types.yaml#/definitions/flag description: -- cgit v1.2.3 From ec02760b63c21c439d44956e9c66d0af24011f03 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Tue, 7 Jul 2020 20:58:42 +0900 Subject: mmc: core: Add MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND The commit 5a36d6bcdf23 ("mmc: core: Add DT-bindings for MMC_CAP2_FULL_PWR_CYCLE") added the "full-pwr-cycle" property which is possible to perform a full power cycle of the card at any time. However, some environment (like r8a77951-salvator-xs) is possible to perform a full power cycle of the card in suspend via firmware (PSCI on arm-trusted-firmware). So, in worst case, since we are not doing a graceful shutdown of the eMMC device (just cut VCCQ while the eMMC is "sleeping") in suspend, it could lead to internal data corruptions. So, add MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND to do a graceful shutdown which issues Power Off notification before entering system suspend. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/1594123122-13156-3-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Ulf Hansson --- drivers/mmc/core/host.c | 2 ++ drivers/mmc/core/mmc.c | 3 ++- include/linux/mmc/host.h | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c index 793597556cd7..ce43f7573d80 100644 --- a/drivers/mmc/core/host.c +++ b/drivers/mmc/core/host.c @@ -277,6 +277,8 @@ int mmc_of_parse(struct mmc_host *host) host->caps |= MMC_CAP_SDIO_IRQ; if (device_property_read_bool(dev, "full-pwr-cycle")) host->caps2 |= MMC_CAP2_FULL_PWR_CYCLE; + if (device_property_read_bool(dev, "full-pwr-cycle-in-suspend")) + host->caps2 |= MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND; if (device_property_read_bool(dev, "keep-power-in-suspend")) host->pm_caps |= MMC_PM_KEEP_POWER; if (device_property_read_bool(dev, "wakeup-source") || diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 4203303f946a..b3fa193de846 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -2038,7 +2038,8 @@ static int _mmc_suspend(struct mmc_host *host, bool is_suspend) goto out; if (mmc_can_poweroff_notify(host->card) && - ((host->caps2 & MMC_CAP2_FULL_PWR_CYCLE) || !is_suspend)) + ((host->caps2 & MMC_CAP2_FULL_PWR_CYCLE) || !is_suspend || + (host->caps2 & MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND))) err = mmc_poweroff_notify(host->card, notify_type); else if (mmc_can_sleep(host->card)) err = mmc_sleep(host); diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h index 1fa4fa1caef5..c5b6e97cb21a 100644 --- a/include/linux/mmc/host.h +++ b/include/linux/mmc/host.h @@ -352,6 +352,7 @@ struct mmc_host { #define MMC_CAP2_BOOTPART_NOACC (1 << 0) /* Boot partition no access */ #define MMC_CAP2_FULL_PWR_CYCLE (1 << 2) /* Can do full power cycle */ +#define MMC_CAP2_FULL_PWR_CYCLE_IN_SUSPEND (1 << 3) /* Can do full power cycle in suspend */ #define MMC_CAP2_HS200_1_8V_SDR (1 << 5) /* can support */ #define MMC_CAP2_HS200_1_2V_SDR (1 << 6) /* can support */ #define MMC_CAP2_HS200 (MMC_CAP2_HS200_1_8V_SDR | \ -- cgit v1.2.3 From 3debc24f7fe637ebefbaa3d37aeecb33a69bde11 Mon Sep 17 00:00:00 2001 From: Veerabhadrarao Badiganti Date: Thu, 9 Jul 2020 18:43:25 +0530 Subject: mmc: sdhci: Fix potential null pointer access while accessing vqmmc Don't access vqmmc regulator handler, if it's already invalidated. Reported-by: Dan Carpenter Signed-off-by: Veerabhadrarao Badiganti Link: https://lore.kernel.org/r/1594300408-17658-1-git-send-email-vbadigan@codeaurora.org Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index e6275c2202b0..d3b62fc5c661 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -4383,11 +4383,6 @@ int sdhci_setup_host(struct sdhci_host *host) if (!IS_ERR(mmc->supply.vqmmc)) { if (enable_vqmmc) { ret = regulator_enable(mmc->supply.vqmmc); - if (ret) { - pr_warn("%s: Failed to enable vqmmc regulator: %d\n", - mmc_hostname(mmc), ret); - mmc->supply.vqmmc = ERR_PTR(-EINVAL); - } host->sdhci_core_to_disable_vqmmc = !ret; } @@ -4402,6 +4397,13 @@ int sdhci_setup_host(struct sdhci_host *host) if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 2700000, 3600000)) host->flags &= ~SDHCI_SIGNALING_330; + + if (ret) { + pr_warn("%s: Failed to enable vqmmc regulator: %d\n", + mmc_hostname(mmc), ret); + mmc->supply.vqmmc = ERR_PTR(-EINVAL); + } + } if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { -- cgit v1.2.3 From 16ecd8f33c6e7381abb6aa899526ff2a3bb9dcb4 Mon Sep 17 00:00:00 2001 From: Wan Ahmad Zainie Date: Wed, 1 Jul 2020 10:33:46 +0800 Subject: dt-bindings: mmc: convert arasan sdhci bindings to yaml Convert arasan,sdhci.txt file to yaml. The new file arasan,sdhci.yaml will inherit properties from mmc-controller.yaml. 'sdhci' is no longer a valid name for node and should be changed to 'mmc'. Suggested-by: Ulf Hansson Signed-off-by: Wan Ahmad Zainie Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200701023346.3873-1-wan.ahmad.zainie.wan.mohamad@intel.com Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/arasan,sdhci.txt | 192 ------------- .../devicetree/bindings/mmc/arasan,sdhci.yaml | 299 +++++++++++++++++++++ 2 files changed, 299 insertions(+), 192 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.txt create mode 100644 Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt deleted file mode 100644 index f29bf7dd2ece..000000000000 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ /dev/null @@ -1,192 +0,0 @@ -Device Tree Bindings for the Arasan SDHCI Controller - - The bindings follow the mmc[1], clock[2], interrupt[3] and phy[4] bindings. - Only deviations are documented here. - - [1] Documentation/devicetree/bindings/mmc/mmc.txt - [2] Documentation/devicetree/bindings/clock/clock-bindings.txt - [3] Documentation/devicetree/bindings/interrupt-controller/interrupts.txt - [4] Documentation/devicetree/bindings/phy/phy-bindings.txt - -Required Properties: - - compatible: Compatibility string. One of: - - "arasan,sdhci-8.9a": generic Arasan SDHCI 8.9a PHY - - "arasan,sdhci-4.9a": generic Arasan SDHCI 4.9a PHY - - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY - - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY - For this device it is strongly suggested to include arasan,soc-ctl-syscon. - - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY - For this device it is strongly suggested to include clock-output-names and - #clock-cells. - - "xlnx,versal-8.9a": Versal SDHCI 8.9a PHY - For this device it is strongly suggested to include clock-output-names and - #clock-cells. - - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY - Note: This binding has been deprecated and moved to [5]. - - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY - For this device it is strongly suggested to include arasan,soc-ctl-syscon. - - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY - For this device it is strongly suggested to include arasan,soc-ctl-syscon. - - "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC - For this device it is strongly suggested to include arasan,soc-ctl-syscon. - - "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller - For this device it is strongly suggested to include arasan,soc-ctl-syscon. - - "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller - For this device it is strongly suggested to include arasan,soc-ctl-syscon. - - [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt - - - reg: From mmc bindings: Register location and length. - - clocks: From clock bindings: Handles to clock inputs. - - clock-names: From clock bindings: Tuple including "clk_xin" and "clk_ahb" - - interrupts: Interrupt specifier - -Required Properties for "arasan,sdhci-5.1": - - phys: From PHY bindings: Phandle for the Generic PHY for arasan. - - phy-names: MUST be "phy_arasan". - -Optional Properties: - - arasan,soc-ctl-syscon: A phandle to a syscon device (see ../mfd/syscon.txt) - used to access core corecfg registers. Offsets of registers in this - syscon are determined based on the main compatible string for the device. - - clock-output-names: If specified, this will be the name of the card clock - which will be exposed by this device. Required if #clock-cells is - specified. - - #clock-cells: If specified this should be the value <0> or <1>. With this - property in place we will export one or two clocks representing the Card - Clock. These clocks are expected to be consumed by our PHY. - - xlnx,fails-without-test-cd: when present, the controller doesn't work when - the CD line is not connected properly, and the line is not connected - properly. Test mode can be used to force the controller to function. - - xlnx,int-clock-stable-broken: when present, the controller always reports - that the internal clock is stable even when it is not. - - - xlnx,mio-bank: When specified, this will indicate the MIO bank number in - which the command and data lines are configured. If not specified, driver - will assume this as 0. - -Example: - sdhci@e0100000 { - compatible = "arasan,sdhci-8.9a"; - reg = <0xe0100000 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&clkc 21>, <&clkc 32>; - interrupt-parent = <&gic>; - interrupts = <0 24 4>; - } ; - - sdhci@e2800000 { - compatible = "arasan,sdhci-5.1"; - reg = <0xe2800000 0x1000>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&cru 8>, <&cru 18>; - interrupt-parent = <&gic>; - interrupts = <0 24 4>; - phys = <&emmc_phy>; - phy-names = "phy_arasan"; - } ; - - sdhci: sdhci@fe330000 { - compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; - reg = <0x0 0xfe330000 0x0 0x10000>; - interrupts = ; - clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; - clock-names = "clk_xin", "clk_ahb"; - arasan,soc-ctl-syscon = <&grf>; - assigned-clocks = <&cru SCLK_EMMC>; - assigned-clock-rates = <200000000>; - clock-output-names = "emmc_cardclock"; - phys = <&emmc_phy>; - phy-names = "phy_arasan"; - #clock-cells = <0>; - }; - - sdhci: mmc@ff160000 { - compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; - interrupt-parent = <&gic>; - interrupts = <0 48 4>; - reg = <0x0 0xff160000 0x0 0x1000>; - clocks = <&clk200>, <&clk200>; - clock-names = "clk_xin", "clk_ahb"; - clock-output-names = "clk_out_sd0", "clk_in_sd0"; - #clock-cells = <1>; - clk-phase-sd-hs = <63>, <72>; - }; - - sdhci: mmc@f1040000 { - compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; - interrupt-parent = <&gic>; - interrupts = <0 126 4>; - reg = <0x0 0xf1040000 0x0 0x10000>; - clocks = <&clk200>, <&clk200>; - clock-names = "clk_xin", "clk_ahb"; - clock-output-names = "clk_out_sd0", "clk_in_sd0"; - #clock-cells = <1>; - clk-phase-sd-hs = <132>, <60>; - }; - - emmc: sdhci@ec700000 { - compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1"; - reg = <0xec700000 0x300>; - interrupt-parent = <&ioapic1>; - interrupts = <44 1>; - clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>, - <&cgu0 LGM_GCLK_EMMC>; - clock-names = "clk_xin", "clk_ahb", "gate"; - clock-output-names = "emmc_cardclock"; - #clock-cells = <0>; - phys = <&emmc_phy>; - phy-names = "phy_arasan"; - arasan,soc-ctl-syscon = <&sysconf>; - }; - - sdxc: sdhci@ec600000 { - compatible = "arasan,sdhci-5.1", "intel,lgm-sdhci-5.1-sdxc"; - reg = <0xec600000 0x300>; - interrupt-parent = <&ioapic1>; - interrupts = <43 1>; - clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>, - <&cgu0 LGM_GCLK_SDXC>; - clock-names = "clk_xin", "clk_ahb", "gate"; - clock-output-names = "sdxc_cardclock"; - #clock-cells = <0>; - phys = <&sdxc_phy>; - phy-names = "phy_arasan"; - arasan,soc-ctl-syscon = <&sysconf>; - }; - - mmc: mmc@33000000 { - compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1"; - interrupts = ; - reg = <0x0 0x33000000 0x0 0x300>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>, - <&scmi_clk KEEM_BAY_PSS_EMMC>; - phys = <&emmc_phy>; - phy-names = "phy_arasan"; - assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>; - assigned-clock-rates = <200000000>; - clock-output-names = "emmc_cardclock"; - #clock-cells = <0>; - arasan,soc-ctl-syscon = <&mmc_phy_syscon>; - }; - - sd0: mmc@31000000 { - compatible = "intel,keembay-sdhci-5.1-sd"; - interrupts = ; - reg = <0x0 0x31000000 0x0 0x300>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>, - <&scmi_clk KEEM_BAY_PSS_SD0>; - arasan,soc-ctl-syscon = <&sd0_phy_syscon>; - }; - - sd1: mmc@32000000 { - compatible = "intel,keembay-sdhci-5.1-sdio"; - interrupts = ; - reg = <0x0 0x32000000 0x0 0x300>; - clock-names = "clk_xin", "clk_ahb"; - clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>, - <&scmi_clk KEEM_BAY_PSS_SD1>; - arasan,soc-ctl-syscon = <&sd1_phy_syscon>; - }; diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml new file mode 100644 index 000000000000..5887c917d480 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -0,0 +1,299 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Device Tree Bindings for the Arasan SDHCI Controller + +maintainers: + - Adrian Hunter + +allOf: + - $ref: "mmc-controller.yaml#" + - if: + properties: + compatible: + contains: + const: arasan,sdhci-5.1 + then: + required: + - phys + - phy-names + - if: + properties: + compatible: + contains: + enum: + - xlnx,zynqmp-8.9a + - xlnx,versal-8.9a + then: + properties: + clock-output-names: + items: + - const: clk_out_sd0 + - const: clk_in_sd0 + +properties: + compatible: + oneOf: + - const: arasan,sdhci-8.9a # generic Arasan SDHCI 8.9a PHY + - const: arasan,sdhci-4.9a # generic Arasan SDHCI 4.9a PHY + - const: arasan,sdhci-5.1 # generic Arasan SDHCI 5.1 PHY + - items: + - const: rockchip,rk3399-sdhci-5.1 # rk3399 eMMC PHY + - const: arasan,sdhci-5.1 + description: + For this device it is strongly suggested to include + arasan,soc-ctl-syscon. + - items: + - const: xlnx,zynqmp-8.9a # ZynqMP SDHCI 8.9a PHY + - const: arasan,sdhci-8.9a + description: + For this device it is strongly suggested to include + clock-output-names and '#clock-cells'. + - items: + - const: xlnx,versal-8.9a # Versal SDHCI 8.9a PHY + - const: arasan,sdhci-8.9a + description: + For this device it is strongly suggested to include + clock-output-names and '#clock-cells'. + - items: + - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY + - const: arasan,sdhci-5.1 + description: + For this device it is strongly suggested to include + arasan,soc-ctl-syscon. + - items: + - const: intel,lgm-sdhci-5.1-sdxc # Intel LGM SDXC PHY + - const: arasan,sdhci-5.1 + description: + For this device it is strongly suggested to include + arasan,soc-ctl-syscon. + - items: + - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY + - const: arasan,sdhci-5.1 + description: + For this device it is strongly suggested to include + arasan,soc-ctl-syscon. + - const: intel,keembay-sdhci-5.1-sd # Intel Keem Bay SD controller + description: + For this device it is strongly suggested to include + arasan,soc-ctl-syscon. + - const: intel,keembay-sdhci-5.1-sdio # Intel Keem Bay SDIO controller + description: + For this device it is strongly suggested to include + arasan,soc-ctl-syscon. + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + + clock-names: + minItems: 2 + items: + - const: clk_xin + - const: clk_ahb + - const: gate + + interrupts: + maxItems: 1 + + phys: + maxItems: 1 + + phy-names: + const: phy_arasan + + arasan,soc-ctl-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: + A phandle to a syscon device (see ../mfd/syscon.txt) used to access + core corecfg registers. Offsets of registers in this syscon are + determined based on the main compatible string for the device. + + clock-output-names: + minItems: 1 + maxItems: 2 + description: + Name of the card clock which will be exposed by this device. + + '#clock-cells': + enum: [0, 1] + description: + With this property in place we will export one or two clocks + representing the Card Clock. These clocks are expected to be + consumed by our PHY. + + xlnx,fails-without-test-cd: + $ref: /schemas/types.yaml#/definitions/flag + description: + When present, the controller doesn't work when the CD line is not + connected properly, and the line is not connected properly. + Test mode can be used to force the controller to function. + + xlnx,int-clock-stable-broken: + $ref: /schemas/types.yaml#/definitions/flag + description: + When present, the controller always reports that the internal clock + is stable even when it is not. + + xlnx,mio-bank: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 2] + default: 0 + description: + The MIO bank number in which the command and data lines are configured. + +dependencies: + clock-output-names: [ '#clock-cells' ] + '#clock-cells': [ clock-output-names ] + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + mmc@e0100000 { + compatible = "arasan,sdhci-8.9a"; + reg = <0xe0100000 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&clkc 21>, <&clkc 32>; + interrupt-parent = <&gic>; + interrupts = <0 24 4>; + }; + + - | + mmc@e2800000 { + compatible = "arasan,sdhci-5.1"; + reg = <0xe2800000 0x1000>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&cru 8>, <&cru 18>; + interrupt-parent = <&gic>; + interrupts = <0 24 4>; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + }; + + - | + #include + #include + #include + mmc@fe330000 { + compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1"; + reg = <0xfe330000 0x10000>; + interrupts = ; + clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>; + clock-names = "clk_xin", "clk_ahb"; + arasan,soc-ctl-syscon = <&grf>; + assigned-clocks = <&cru SCLK_EMMC>; + assigned-clock-rates = <200000000>; + clock-output-names = "emmc_cardclock"; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + #clock-cells = <0>; + }; + + - | + mmc@ff160000 { + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + interrupt-parent = <&gic>; + interrupts = <0 48 4>; + reg = <0xff160000 0x1000>; + clocks = <&clk200>, <&clk200>; + clock-names = "clk_xin", "clk_ahb"; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; + #clock-cells = <1>; + clk-phase-sd-hs = <63>, <72>; + }; + + - | + mmc@f1040000 { + compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a"; + interrupt-parent = <&gic>; + interrupts = <0 126 4>; + reg = <0xf1040000 0x10000>; + clocks = <&clk200>, <&clk200>; + clock-names = "clk_xin", "clk_ahb"; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; + #clock-cells = <1>; + clk-phase-sd-hs = <132>, <60>; + }; + + - | + #define LGM_CLK_EMMC5 + #define LGM_CLK_NGI + #define LGM_GCLK_EMMC + mmc@ec700000 { + compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1"; + reg = <0xec700000 0x300>; + interrupt-parent = <&ioapic1>; + interrupts = <44 1>; + clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>, + <&cgu0 LGM_GCLK_EMMC>; + clock-names = "clk_xin", "clk_ahb", "gate"; + clock-output-names = "emmc_cardclock"; + #clock-cells = <0>; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + arasan,soc-ctl-syscon = <&sysconf>; + }; + + - | + #define LGM_CLK_SDIO + #define LGM_GCLK_SDXC + mmc@ec600000 { + compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1"; + reg = <0xec600000 0x300>; + interrupt-parent = <&ioapic1>; + interrupts = <43 1>; + clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>, + <&cgu0 LGM_GCLK_SDXC>; + clock-names = "clk_xin", "clk_ahb", "gate"; + clock-output-names = "sdxc_cardclock"; + #clock-cells = <0>; + phys = <&sdxc_phy>; + phy-names = "phy_arasan"; + arasan,soc-ctl-syscon = <&sysconf>; + }; + + - | + #define KEEM_BAY_PSS_AUX_EMMC + #define KEEM_BAY_PSS_EMMC + mmc@33000000 { + compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1"; + interrupts = ; + reg = <0x33000000 0x300>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>, + <&scmi_clk KEEM_BAY_PSS_EMMC>; + phys = <&emmc_phy>; + phy-names = "phy_arasan"; + assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>; + assigned-clock-rates = <200000000>; + clock-output-names = "emmc_cardclock"; + #clock-cells = <0>; + arasan,soc-ctl-syscon = <&mmc_phy_syscon>; + }; + + - | + #define KEEM_BAY_PSS_AUX_SD0 + #define KEEM_BAY_PSS_SD0 + mmc@31000000 { + compatible = "intel,keembay-sdhci-5.1-sd"; + interrupts = ; + reg = <0x31000000 0x300>; + clock-names = "clk_xin", "clk_ahb"; + clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>, + <&scmi_clk KEEM_BAY_PSS_SD0>; + arasan,soc-ctl-syscon = <&sd0_phy_syscon>; + }; -- cgit v1.2.3 From a1c76734095344fdbe43cbfe4940020e13151679 Mon Sep 17 00:00:00 2001 From: Yoshihiro Shimoda Date: Fri, 10 Jul 2020 15:51:23 +0900 Subject: dt-bindings: mmc: renesas,sdhi: convert to YAML Convert Renesas SDHI SD/MMC controller document to YAML. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/1594363883-22154-1-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Ulf Hansson --- .../devicetree/bindings/mmc/renesas,sdhi.txt | 114 ------------ .../devicetree/bindings/mmc/renesas,sdhi.yaml | 191 +++++++++++++++++++++ 2 files changed, 191 insertions(+), 114 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mmc/renesas,sdhi.txt create mode 100644 Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt b/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt deleted file mode 100644 index 0ca9a622cce0..000000000000 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.txt +++ /dev/null @@ -1,114 +0,0 @@ -* Renesas SDHI SD/MMC controller - -Required properties: -- compatible: should contain one or more of the following: - "renesas,sdhi-sh73a0" - SDHI IP on SH73A0 SoC - "renesas,sdhi-r7s72100" - SDHI IP on R7S72100 SoC - "renesas,sdhi-r7s9210" - SDHI IP on R7S9210 SoC - "renesas,sdhi-r8a73a4" - SDHI IP on R8A73A4 SoC - "renesas,sdhi-r8a7740" - SDHI IP on R8A7740 SoC - "renesas,sdhi-r8a7742" - SDHI IP on R8A7742 SoC - "renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC - "renesas,sdhi-r8a7744" - SDHI IP on R8A7744 SoC - "renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC - "renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC - "renesas,sdhi-r8a774b1" - SDHI IP on R8A774B1 SoC - "renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC - "renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC - "renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC - "renesas,sdhi-r8a7778" - SDHI IP on R8A7778 SoC - "renesas,sdhi-r8a7779" - SDHI IP on R8A7779 SoC - "renesas,sdhi-r8a7790" - SDHI IP on R8A7790 SoC - "renesas,sdhi-r8a7791" - SDHI IP on R8A7791 SoC - "renesas,sdhi-r8a7792" - SDHI IP on R8A7792 SoC - "renesas,sdhi-r8a7793" - SDHI IP on R8A7793 SoC - "renesas,sdhi-r8a7794" - SDHI IP on R8A7794 SoC - "renesas,sdhi-r8a7795" - SDHI IP on R8A7795 SoC - "renesas,sdhi-r8a7796" - SDHI IP on R8A77960 SoC - "renesas,sdhi-r8a77961" - SDHI IP on R8A77961 SoC - "renesas,sdhi-r8a77965" - SDHI IP on R8A77965 SoC - "renesas,sdhi-r8a77970" - SDHI IP on R8A77970 SoC - "renesas,sdhi-r8a77980" - SDHI IP on R8A77980 SoC - "renesas,sdhi-r8a77990" - SDHI IP on R8A77990 SoC - "renesas,sdhi-r8a77995" - SDHI IP on R8A77995 SoC - "renesas,sdhi-shmobile" - a generic sh-mobile SDHI controller - "renesas,rcar-gen1-sdhi" - a generic R-Car Gen1 SDHI controller - "renesas,rcar-gen2-sdhi" - a generic R-Car Gen2 and RZ/G1 SDHI - (not SDHI/MMC) controller - "renesas,rcar-gen3-sdhi" - a generic R-Car Gen3 or RZ/G2 - SDHI controller - - - When compatible with the generic version, nodes must list - the SoC-specific version corresponding to the platform - first followed by the generic version. - -- clocks: Most controllers only have 1 clock source per channel. However, on - some variations of this controller, the internal card detection - logic that exists in this controller is sectioned off to be run by a - separate second clock source to allow the main core clock to be turned - off to save power. - If 2 clocks are specified by the hardware, you must name them as - "core" and "cd". If the controller only has 1 clock, naming is not - required. - Devices which have more than 1 clock are listed below: - 2: R7S72100, R7S9210 - -Optional properties: -- pinctrl-names: should be "default", "state_uhs" -- pinctrl-0: should contain default/high speed pin ctrl -- pinctrl-1: should contain uhs mode pin ctrl - -Example: R8A7790 (R-Car H2) SDHI controller nodes - - sdhi0: sd@ee100000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0 0xee100000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 314>; - dmas = <&dmac0 0xcd>, <&dmac0 0xce>, - <&dmac1 0xcd>, <&dmac1 0xce>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 314>; - }; - - sdhi1: sd@ee120000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0 0xee120000 0 0x328>; - interrupts = ; - clocks = <&cpg CPG_MOD 313>; - dmas = <&dmac0 0xc9>, <&dmac0 0xca>, - <&dmac1 0xc9>, <&dmac1 0xca>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <195000000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 313>; - }; - - sdhi2: sd@ee140000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0 0xee140000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 312>; - dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, - <&dmac1 0xc1>, <&dmac1 0xc2>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 312>; - }; - - sdhi3: sd@ee160000 { - compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; - reg = <0 0xee160000 0 0x100>; - interrupts = ; - clocks = <&cpg CPG_MOD 311>; - dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, - <&dmac1 0xd3>, <&dmac1 0xd4>; - dma-names = "tx", "rx", "tx", "rx"; - max-frequency = <97500000>; - power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; - resets = <&cpg 311>; - }; diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml new file mode 100644 index 000000000000..e5dbc20456e5 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Renesas SDHI SD/MMC controller + +maintainers: + - Wolfram Sang + +allOf: + - $ref: "mmc-controller.yaml" + +properties: + compatible: + oneOf: + - items: + - const: renesas,sdhi-sh73a0 # R-Mobile APE6 + - items: + - const: renesas,sdhi-r7s72100 # RZ/A1H + - items: + - const: renesas,sdhi-r7s9210 # SH-Mobile AG5 + - items: + - const: renesas,sdhi-r8a73a4 # R-Mobile APE6 + - items: + - const: renesas,sdhi-r8a7740 # R-Mobile A1 + - items: + - enum: + - renesas,sdhi-r8a7778 # R-Car M1 + - renesas,sdhi-r8a7779 # R-Car H1 + - const: renesas,rcar-gen1-sdhi # R-Car Gen1 + - items: + - enum: + - renesas,sdhi-r8a7742 # RZ/G1H + - renesas,sdhi-r8a7743 # RZ/G1M + - renesas,sdhi-r8a7744 # RZ/G1N + - renesas,sdhi-r8a7745 # RZ/G1E + - renesas,sdhi-r8a77470 # RZ/G1C + - renesas,sdhi-r8a7790 # R-Car H2 + - renesas,sdhi-r8a7791 # R-Car M2-W + - renesas,sdhi-r8a7792 # R-Car V2H + - renesas,sdhi-r8a7793 # R-Car M2-N + - renesas,sdhi-r8a7794 # R-Car E2 + - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1 + - items: + - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP) + - items: + - enum: + - renesas,sdhi-r8a774a1 # RZ/G2M + - renesas,sdhi-r8a774b1 # RZ/G2N + - renesas,sdhi-r8a774c0 # RZ/G2E + - renesas,sdhi-r8a7795 # R-Car H3 + - renesas,sdhi-r8a7796 # R-Car M3-W + - renesas,sdhi-r8a77961 # R-Car M3-W+ + - renesas,sdhi-r8a77965 # R-Car M3-N + - renesas,sdhi-r8a77970 # R-Car V3M + - renesas,sdhi-r8a77980 # R-Car V3H + - renesas,sdhi-r8a77990 # R-Car E3 + - renesas,sdhi-r8a77995 # R-Car D3 + - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 3 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: core + - const: cd + + dmas: + minItems: 4 + maxItems: 4 + + dma-names: + minItems: 4 + maxItems: 4 + items: + enum: + - tx + - rx + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + pinctrl-0: + minItems: 1 + maxItems: 2 + + pinctrl-1: + maxItems: 1 + + pinctrl-names: + minItems: 1 + maxItems: 2 + items: + - const: default + - const: state_uhs + + max-frequency: true + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + +if: + properties: + compatible: + items: + enum: + - renesas,sdhi-r7s72100 + - renesas,sdhi-r7s9210 +then: + required: + - clock-names + description: + The internal card detection logic that exists in these controllers is + sectioned off to be run by a separate second clock source to allow + the main core clock to be turned off to save power. + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + sdhi0: mmc@ee100000 { + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; + reg = <0xee100000 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 314>; + dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 314>; + }; + + sdhi1: mmc@ee120000 { + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; + reg = <0xee120000 0x328>; + interrupts = ; + clocks = <&cpg CPG_MOD 313>; + dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <195000000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 313>; + }; + + sdhi2: mmc@ee140000 { + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; + reg = <0xee140000 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 312>; + dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 312>; + }; + + sdhi3: mmc@ee160000 { + compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi"; + reg = <0xee160000 0x100>; + interrupts = ; + clocks = <&cpg CPG_MOD 311>; + dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>; + dma-names = "tx", "rx", "tx", "rx"; + max-frequency = <97500000>; + power-domains = <&sysc R8A7790_PD_ALWAYS_ON>; + resets = <&cpg 311>; + }; -- cgit v1.2.3 From 907be2a62e4522c3dc3c298a213ccc741bd22732 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 14 Jul 2020 17:14:10 +0300 Subject: mmc: sdhci: Fix a potential uninitialized variable Smatch complains that "ret" can be used without being initialized. drivers/mmc/host/sdhci.c 4383 if (!IS_ERR(mmc->supply.vqmmc)) { 4384 if (enable_vqmmc) { ^^^^^^^^^^^^ 4385 ret = regulator_enable(mmc->supply.vqmmc); ^^^^^ 4386 host->sdhci_core_to_disable_vqmmc = !ret; 4387 } "ret" is only initialized when "enable_vqmmc" is true. Signed-off-by: Dan Carpenter Link: https://lore.kernel.org/r/20200714141410.GB314989@mwanda Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index d3b62fc5c661..3d272063d785 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -4104,7 +4104,7 @@ int sdhci_setup_host(struct sdhci_host *host) unsigned int ocr_avail; unsigned int override_timeout_clk; u32 max_clk; - int ret; + int ret = 0; bool enable_vqmmc = false; WARN_ON(host == NULL); -- cgit v1.2.3 From 88e1d0b175ec0bfa775c8629eae2a728726e2c6a Mon Sep 17 00:00:00 2001 From: Manish Narani Date: Wed, 15 Jul 2020 00:42:33 +0530 Subject: mmc: sdhci-of-arasan: fix timings allocation code The initial code that was adding delays was doing a cast over undefined memory. This meant that the delays would be all gibberish. This change, allocates all delays on the stack, and assigns them from the ZynqMP & Versal macros/phase-list. And then finally copies them over the common iclk_phase & oclk_phase variables. Signed-off-by: Manish Narani Link: https://lore.kernel.org/r/1594753953-62980-1-git-send-email-manish.narani@xilinx.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-of-arasan.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index 5a432f9bf1bb..f186fbd016b1 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -1025,7 +1025,6 @@ static void arasan_dt_read_clk_phase(struct device *dev, static void arasan_dt_parse_clk_phases(struct device *dev, struct sdhci_arasan_clk_data *clk_data) { - int *iclk_phase, *oclk_phase; u32 mio_bank = 0; int i; @@ -1037,28 +1036,32 @@ static void arasan_dt_parse_clk_phases(struct device *dev, clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { - iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_ICLK_PHASE; - oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) ZYNQMP_OCLK_PHASE; + u32 zynqmp_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = + ZYNQMP_ICLK_PHASE; + u32 zynqmp_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = + ZYNQMP_OCLK_PHASE; of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); if (mio_bank == 2) { - oclk_phase[MMC_TIMING_UHS_SDR104] = 90; - oclk_phase[MMC_TIMING_MMC_HS200] = 90; + zynqmp_oclk_phase[MMC_TIMING_UHS_SDR104] = 90; + zynqmp_oclk_phase[MMC_TIMING_MMC_HS200] = 90; } for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { - clk_data->clk_phase_in[i] = iclk_phase[i]; - clk_data->clk_phase_out[i] = oclk_phase[i]; + clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; + clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i]; } } if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) { - iclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) VERSAL_ICLK_PHASE; - oclk_phase = (int [MMC_TIMING_MMC_HS400 + 1]) VERSAL_OCLK_PHASE; + u32 versal_iclk_phase[MMC_TIMING_MMC_HS400 + 1] = + VERSAL_ICLK_PHASE; + u32 versal_oclk_phase[MMC_TIMING_MMC_HS400 + 1] = + VERSAL_OCLK_PHASE; for (i = 0; i <= MMC_TIMING_MMC_HS400; i++) { - clk_data->clk_phase_in[i] = iclk_phase[i]; - clk_data->clk_phase_out[i] = oclk_phase[i]; + clk_data->clk_phase_in[i] = versal_iclk_phase[i]; + clk_data->clk_phase_out[i] = versal_oclk_phase[i]; } } -- cgit v1.2.3 From 90508658d713c0469c056cea618c21b5610c3452 Mon Sep 17 00:00:00 2001 From: Ben Chuang Date: Wed, 15 Jul 2020 15:33:44 +0800 Subject: mmc: cqhci: Fix a print format for the task descriptor The format string of the task descriptor should be "%016llx". Signed-off-by: Ben Chuang Link: https://lore.kernel.org/r/20200715073344.8965-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/cqhci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c index 8cc277b4ffe9..cfa87dfa73d8 100644 --- a/drivers/mmc/host/cqhci.c +++ b/drivers/mmc/host/cqhci.c @@ -422,7 +422,7 @@ static void cqhci_prep_task_desc(struct mmc_request *mrq, CQHCI_BLK_COUNT(mrq->data->blocks) | CQHCI_BLK_ADDR((u64)mrq->data->blk_addr); - pr_debug("%s: cqhci: tag %d task descriptor 0x016%llx\n", + pr_debug("%s: cqhci: tag %d task descriptor 0x%016llx\n", mmc_hostname(mrq->host), mrq->tag, (unsigned long long)*data); } -- cgit v1.2.3 From 786d33c887e15061ff95942db68fe5c6ca98e5fc Mon Sep 17 00:00:00 2001 From: Ben Chuang Date: Fri, 17 Jul 2020 11:33:50 +0800 Subject: mmc: sdhci-pci-gli: Set SDR104's clock to 205MHz and enable SSC for GL975x Set SDR104's clock to 205MHz and enable SSC for GL9750 and GL9755 Signed-off-by: Ben Chuang Link: https://lore.kernel.org/r/20200717033350.13006-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-pci-gli.c | 220 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 218 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c index ca0166d9bf82..5da2b06d84ae 100644 --- a/drivers/mmc/host/sdhci-pci-gli.c +++ b/drivers/mmc/host/sdhci-pci-gli.c @@ -31,10 +31,18 @@ #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) #define SDHCI_GLI_9750_PLL 0x864 +#define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) +#define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) +#define SDHCI_GLI_9750_PLL_DIR BIT(15) #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) #define GLI_9750_PLL_TX2_INV_VALUE 0x1 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 +#define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) +#define SDHCI_GLI_9750_PLLSSC_EN BIT(31) + +#define SDHCI_GLI_9750_PLLSSC 0x86C +#define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) #define SDHCI_GLI_9750_SW_CTRL 0x874 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) @@ -76,6 +84,21 @@ #define PCIE_GLI_9763E_SCR 0x8E0 #define GLI_9763E_SCR_AXI_REQ BIT(9) +#define PCI_GLI_9755_WT 0x800 +#define PCI_GLI_9755_WT_EN BIT(0) +#define GLI_9755_WT_EN_ON 0x1 +#define GLI_9755_WT_EN_OFF 0x0 + +#define PCI_GLI_9755_PLL 0x64 +#define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) +#define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) +#define PCI_GLI_9755_PLL_DIR BIT(15) +#define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) +#define PCI_GLI_9755_PLLSSC_EN BIT(31) + +#define PCI_GLI_9755_PLLSSC 0x68 +#define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) + #define GLI_MAX_TUNING_LOOP 40 /* Genesys Logic chipset */ @@ -280,6 +303,84 @@ static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) return 0; } +static void gl9750_disable_ssc_pll(struct sdhci_host *host) +{ + u32 pll; + + gl9750_wt_on(host); + pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); + pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); + sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); + gl9750_wt_off(host); +} + +static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) +{ + u32 pll; + + gl9750_wt_on(host); + pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); + pll &= ~(SDHCI_GLI_9750_PLL_LDIV | + SDHCI_GLI_9750_PLL_PDIV | + SDHCI_GLI_9750_PLL_DIR); + pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | + FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | + FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); + sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); + gl9750_wt_off(host); + + /* wait for pll stable */ + mdelay(1); +} + +static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) +{ + u32 pll; + u32 ssc; + + gl9750_wt_on(host); + pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); + ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); + pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | + SDHCI_GLI_9750_PLLSSC_EN); + ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; + pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | + FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); + ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); + sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); + sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); + gl9750_wt_off(host); +} + +static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) +{ + /* set pll to 205MHz and enable ssc */ + gl9750_set_ssc(host, 0x1, 0x1F, 0xFFE7); + gl9750_set_pll(host, 0x1, 0x246, 0x0); +} + +static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct mmc_ios *ios = &host->mmc->ios; + u16 clk; + + host->mmc->actual_clock = 0; + + gl9750_disable_ssc_pll(host); + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (clock == 0) + return; + + clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); + if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { + host->mmc->actual_clock = 205000000; + gl9750_set_ssc_pll_205mhz(host); + } + + sdhci_enable_clk(host, clk); +} + static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) { int ret; @@ -295,6 +396,121 @@ static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); } +static inline void gl9755_wt_on(struct pci_dev *pdev) +{ + u32 wt_value; + u32 wt_enable; + + pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); + wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); + + if (wt_enable == GLI_9755_WT_EN_ON) + return; + + wt_value &= ~PCI_GLI_9755_WT_EN; + wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); + + pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); +} + +static inline void gl9755_wt_off(struct pci_dev *pdev) +{ + u32 wt_value; + u32 wt_enable; + + pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); + wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); + + if (wt_enable == GLI_9755_WT_EN_OFF) + return; + + wt_value &= ~PCI_GLI_9755_WT_EN; + wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); + + pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); +} + +static void gl9755_disable_ssc_pll(struct pci_dev *pdev) +{ + u32 pll; + + gl9755_wt_on(pdev); + pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); + pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); + pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); + gl9755_wt_off(pdev); +} + +static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) +{ + u32 pll; + + gl9755_wt_on(pdev); + pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); + pll &= ~(PCI_GLI_9755_PLL_LDIV | + PCI_GLI_9755_PLL_PDIV | + PCI_GLI_9755_PLL_DIR); + pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | + FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | + FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); + pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); + gl9755_wt_off(pdev); + + /* wait for pll stable */ + mdelay(1); +} + +static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) +{ + u32 pll; + u32 ssc; + + gl9755_wt_on(pdev); + pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); + pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); + pll &= ~(PCI_GLI_9755_PLLSSC_STEP | + PCI_GLI_9755_PLLSSC_EN); + ssc &= ~PCI_GLI_9755_PLLSSC_PPM; + pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | + FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); + ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); + pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); + pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); + gl9755_wt_off(pdev); +} + +static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) +{ + /* set pll to 205MHz and enable ssc */ + gl9755_set_ssc(pdev, 0x1, 0x1F, 0xFFE7); + gl9755_set_pll(pdev, 0x1, 0x246, 0x0); +} + +static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) +{ + struct sdhci_pci_slot *slot = sdhci_priv(host); + struct mmc_ios *ios = &host->mmc->ios; + struct pci_dev *pdev; + u16 clk; + + pdev = slot->chip->pdev; + host->mmc->actual_clock = 0; + + gl9755_disable_ssc_pll(pdev); + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); + + if (clock == 0) + return; + + clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); + if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { + host->mmc->actual_clock = 205000000; + gl9755_set_ssc_pll_205mhz(pdev); + } + + sdhci_enable_clk(host, clk); +} + static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) { struct sdhci_host *host = slot->host; @@ -440,7 +656,7 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) } static const struct sdhci_ops sdhci_gl9755_ops = { - .set_clock = sdhci_set_clock, + .set_clock = sdhci_gl9755_set_clock, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_reset, @@ -460,7 +676,7 @@ const struct sdhci_pci_fixes sdhci_gl9755 = { static const struct sdhci_ops sdhci_gl9750_ops = { .read_l = sdhci_gl9750_readl, - .set_clock = sdhci_set_clock, + .set_clock = sdhci_gl9750_set_clock, .enable_dma = sdhci_pci_enable_dma, .set_bus_width = sdhci_set_bus_width, .reset = sdhci_gl9750_reset, -- cgit v1.2.3 From adc40a5179df30421a5537bfeb4545100ab97d5e Mon Sep 17 00:00:00 2001 From: Masahiro Yamada Date: Mon, 20 Jul 2020 15:11:41 +0900 Subject: mmc: sdhci-cadence: do not use hardware tuning for SD mode As commit ef6b75671b5f ("mmc: sdhci-cadence: send tune request twice to work around errata") stated, this IP has an errata. This commit applies the second workaround for the SD mode. Due to the errata, it is not possible to use the hardware tuning provided by SDHCI_HOST_CONTROL2. Use the software-controlled tuning like the eMMC mode. Set sdhci_host_ops::platform_execute_tuning instead of overriding mmc_host_ops::execute_tuning. Signed-off-by: Masahiro Yamada Link: https://lore.kernel.org/r/20200720061141.172944-1-yamada.masahiro@socionext.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-cadence.c | 123 ++++++++++++++++++++------------------- 1 file changed, 62 insertions(+), 61 deletions(-) diff --git a/drivers/mmc/host/sdhci-cadence.c b/drivers/mmc/host/sdhci-cadence.c index 4a6c9ba82538..4d9f7681817c 100644 --- a/drivers/mmc/host/sdhci-cadence.c +++ b/drivers/mmc/host/sdhci-cadence.c @@ -202,57 +202,6 @@ static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv) return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp); } -static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, - unsigned int timing) -{ - struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); - u32 mode; - - switch (timing) { - case MMC_TIMING_MMC_HS: - mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; - break; - case MMC_TIMING_MMC_DDR52: - mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; - break; - case MMC_TIMING_MMC_HS200: - mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200; - break; - case MMC_TIMING_MMC_HS400: - if (priv->enhanced_strobe) - mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES; - else - mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400; - break; - default: - mode = SDHCI_CDNS_HRS06_MODE_SD; - break; - } - - sdhci_cdns_set_emmc_mode(priv, mode); - - /* For SD, fall back to the default handler */ - if (mode == SDHCI_CDNS_HRS06_MODE_SD) - sdhci_set_uhs_signaling(host, timing); -} - -static const struct sdhci_ops sdhci_cdns_ops = { - .set_clock = sdhci_set_clock, - .get_timeout_clock = sdhci_cdns_get_timeout_clock, - .set_bus_width = sdhci_set_bus_width, - .reset = sdhci_reset, - .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, -}; - -static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = { - .ops = &sdhci_cdns_ops, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, -}; - -static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { - .ops = &sdhci_cdns_ops, -}; - static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) { struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); @@ -286,23 +235,24 @@ static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val) return 0; } -static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode) +/* + * In SD mode, software must not use the hardware tuning and instead perform + * an almost identical procedure to eMMC. + */ +static int sdhci_cdns_execute_tuning(struct sdhci_host *host, u32 opcode) { - struct sdhci_host *host = mmc_priv(mmc); int cur_streak = 0; int max_streak = 0; int end_of_streak = 0; int i; /* - * This handler only implements the eMMC tuning that is specific to - * this controller. Fall back to the standard method for SD timing. + * Do not execute tuning for UHS_SDR50 or UHS_DDR50. + * The delay is set by probe, based on the DT properties. */ - if (host->timing != MMC_TIMING_MMC_HS200) - return sdhci_execute_tuning(mmc, opcode); - - if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200)) - return -EINVAL; + if (host->timing != MMC_TIMING_MMC_HS200 && + host->timing != MMC_TIMING_UHS_SDR104) + return 0; for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) { if (sdhci_cdns_set_tune_val(host, i) || @@ -325,6 +275,58 @@ static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode) return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2); } +static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host); + u32 mode; + + switch (timing) { + case MMC_TIMING_MMC_HS: + mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR; + break; + case MMC_TIMING_MMC_DDR52: + mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR; + break; + case MMC_TIMING_MMC_HS200: + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200; + break; + case MMC_TIMING_MMC_HS400: + if (priv->enhanced_strobe) + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES; + else + mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400; + break; + default: + mode = SDHCI_CDNS_HRS06_MODE_SD; + break; + } + + sdhci_cdns_set_emmc_mode(priv, mode); + + /* For SD, fall back to the default handler */ + if (mode == SDHCI_CDNS_HRS06_MODE_SD) + sdhci_set_uhs_signaling(host, timing); +} + +static const struct sdhci_ops sdhci_cdns_ops = { + .set_clock = sdhci_set_clock, + .get_timeout_clock = sdhci_cdns_get_timeout_clock, + .set_bus_width = sdhci_set_bus_width, + .reset = sdhci_reset, + .platform_execute_tuning = sdhci_cdns_execute_tuning, + .set_uhs_signaling = sdhci_cdns_set_uhs_signaling, +}; + +static const struct sdhci_pltfm_data sdhci_cdns_uniphier_pltfm_data = { + .ops = &sdhci_cdns_ops, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +}; + +static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = { + .ops = &sdhci_cdns_ops, +}; + static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -385,7 +387,6 @@ static int sdhci_cdns_probe(struct platform_device *pdev) priv->hrs_addr = host->ioaddr; priv->enhanced_strobe = false; host->ioaddr += SDHCI_CDNS_SRS_BASE; - host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning; host->mmc_host_ops.hs400_enhanced_strobe = sdhci_cdns_hs400_enhanced_strobe; sdhci_enable_v4_mode(host); -- cgit v1.2.3 From c4e5e22b3b4895821b7e7a9f5b2f7c820fb48ca3 Mon Sep 17 00:00:00 2001 From: Vaibhav Gupta Date: Mon, 20 Jul 2020 16:46:26 +0530 Subject: memstick: jmb38x_ms: use generic power management Drivers using legacy PM have to manage PCI states and device's PM states themselves. They also need to take care of configuration registers. With improved and powerful support of generic PM, PCI Core takes care of above mentioned, device-independent, jobs. This driver makes use of PCI helper functions like pci_save/restore_state(), pci_enable/disable_device(), pci_set_power_state() and pci_set_master() to do required operations. In generic mode, they are no longer needed. Change function parameter in both .suspend() and .resume() to "struct device*" type. Use to_pci_dev() and dev_get_drvdata() to get "struct pci_dev*" variable and drv data. Compile-tested only. Signed-off-by: Vaibhav Gupta Link: https://lore.kernel.org/r/20200720111625.306681-1-vaibhavgupta40@gmail.com Signed-off-by: Ulf Hansson --- drivers/memstick/host/jmb38x_ms.c | 38 +++++++++++--------------------------- 1 file changed, 11 insertions(+), 27 deletions(-) diff --git a/drivers/memstick/host/jmb38x_ms.c b/drivers/memstick/host/jmb38x_ms.c index 0a9c5ddf2f59..2aa9592917d9 100644 --- a/drivers/memstick/host/jmb38x_ms.c +++ b/drivers/memstick/host/jmb38x_ms.c @@ -793,11 +793,10 @@ static int jmb38x_ms_pmos(struct pci_dev *pdev, int flag) return 0; } -#ifdef CONFIG_PM - -static int jmb38x_ms_suspend(struct pci_dev *dev, pm_message_t state) +static int __maybe_unused jmb38x_ms_suspend(struct device *dev) { - struct jmb38x_ms *jm = pci_get_drvdata(dev); + struct jmb38x_ms *jm = dev_get_drvdata(dev); + int cnt; for (cnt = 0; cnt < jm->host_cnt; ++cnt) { @@ -806,26 +805,17 @@ static int jmb38x_ms_suspend(struct pci_dev *dev, pm_message_t state) memstick_suspend_host(jm->hosts[cnt]); } - pci_save_state(dev); - pci_enable_wake(dev, pci_choose_state(dev, state), 0); - pci_disable_device(dev); - pci_set_power_state(dev, pci_choose_state(dev, state)); + device_wakeup_disable(dev); + return 0; } -static int jmb38x_ms_resume(struct pci_dev *dev) +static int __maybe_unused jmb38x_ms_resume(struct device *dev) { - struct jmb38x_ms *jm = pci_get_drvdata(dev); + struct jmb38x_ms *jm = dev_get_drvdata(dev); int rc; - pci_set_power_state(dev, PCI_D0); - pci_restore_state(dev); - rc = pci_enable_device(dev); - if (rc) - return rc; - pci_set_master(dev); - - jmb38x_ms_pmos(dev, 1); + jmb38x_ms_pmos(to_pci_dev(dev), 1); for (rc = 0; rc < jm->host_cnt; ++rc) { if (!jm->hosts[rc]) @@ -837,13 +827,6 @@ static int jmb38x_ms_resume(struct pci_dev *dev) return 0; } -#else - -#define jmb38x_ms_suspend NULL -#define jmb38x_ms_resume NULL - -#endif /* CONFIG_PM */ - static int jmb38x_ms_count_slots(struct pci_dev *pdev) { int cnt, rc = 0; @@ -1030,13 +1013,14 @@ static struct pci_device_id jmb38x_ms_id_tbl [] = { { } }; +static SIMPLE_DEV_PM_OPS(jmb38x_ms_pm_ops, jmb38x_ms_suspend, jmb38x_ms_resume); + static struct pci_driver jmb38x_ms_driver = { .name = DRIVER_NAME, .id_table = jmb38x_ms_id_tbl, .probe = jmb38x_ms_probe, .remove = jmb38x_ms_remove, - .suspend = jmb38x_ms_suspend, - .resume = jmb38x_ms_resume + .driver.pm = &jmb38x_ms_pm_ops, }; module_pci_driver(jmb38x_ms_driver); -- cgit v1.2.3 From 0d776e5bede6d375c617a03262eee9d2a8a58b75 Mon Sep 17 00:00:00 2001 From: Vaibhav Gupta Date: Mon, 20 Jul 2020 19:56:04 +0530 Subject: mmc: via-sdmmc: use generic power management Drivers using legacy PM have to manage PCI states and device's PM states themselves. They also need to take care of configuration registers. With improved and powerful support of generic PM, PCI Core takes care of above mentioned, device-independent, jobs. This driver makes use of PCI helper functions like pci_save/restore_state(), pci_enable/disable_device(), pci_enable_wake() and pci_set_power_state() and to do required operations. In generic mode, they are no longer needed. Change function parameter in both .suspend() and .resume() to "struct device*" type. Use dev_get_drvdata() to get drv data. Compile-tested only. Signed-off-by: Vaibhav Gupta Link: https://lore.kernel.org/r/20200720142603.577323-1-vaibhavgupta40@gmail.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/via-sdmmc.c | 33 ++++++++------------------------- 1 file changed, 8 insertions(+), 25 deletions(-) diff --git a/drivers/mmc/host/via-sdmmc.c b/drivers/mmc/host/via-sdmmc.c index ef95bce50889..49dab9f42b6d 100644 --- a/drivers/mmc/host/via-sdmmc.c +++ b/drivers/mmc/host/via-sdmmc.c @@ -1220,9 +1220,7 @@ static void via_sd_remove(struct pci_dev *pcidev) pci_name(pcidev), (int)pcidev->vendor, (int)pcidev->device); } -#ifdef CONFIG_PM - -static void via_init_sdc_pm(struct via_crdr_mmc_host *host) +static void __maybe_unused via_init_sdc_pm(struct via_crdr_mmc_host *host) { struct sdhcreg *pm_sdhcreg; void __iomem *addrbase; @@ -1256,30 +1254,27 @@ static void via_init_sdc_pm(struct via_crdr_mmc_host *host) via_print_sdchc(host); } -static int via_sd_suspend(struct pci_dev *pcidev, pm_message_t state) +static int __maybe_unused via_sd_suspend(struct device *dev) { struct via_crdr_mmc_host *host; - host = pci_get_drvdata(pcidev); + host = dev_get_drvdata(dev); via_save_pcictrlreg(host); via_save_sdcreg(host); - pci_save_state(pcidev); - pci_enable_wake(pcidev, pci_choose_state(pcidev, state), 0); - pci_disable_device(pcidev); - pci_set_power_state(pcidev, pci_choose_state(pcidev, state)); + device_wakeup_enable(dev); return 0; } -static int via_sd_resume(struct pci_dev *pcidev) +static int __maybe_unused via_sd_resume(struct device *dev) { struct via_crdr_mmc_host *sdhost; int ret = 0; u8 gatt; - sdhost = pci_get_drvdata(pcidev); + sdhost = dev_get_drvdata(dev); gatt = VIA_CRDR_PCICLKGATT_PAD_PWRON; if (sdhost->power == MMC_VDD_165_195) @@ -1294,32 +1289,20 @@ static int via_sd_resume(struct pci_dev *pcidev) msleep(100); - pci_set_power_state(pcidev, PCI_D0); - pci_restore_state(pcidev); - ret = pci_enable_device(pcidev); - if (ret) - return ret; - via_restore_pcictrlreg(sdhost); via_init_sdc_pm(sdhost); return ret; } -#else /* CONFIG_PM */ - -#define via_sd_suspend NULL -#define via_sd_resume NULL - -#endif /* CONFIG_PM */ +static SIMPLE_DEV_PM_OPS(via_sd_pm_ops, via_sd_suspend, via_sd_resume); static struct pci_driver via_sd_driver = { .name = DRV_NAME, .id_table = via_ids, .probe = via_sd_probe, .remove = via_sd_remove, - .suspend = via_sd_suspend, - .resume = via_sd_resume, + .driver.pm = &via_sd_pm_ops, }; module_pci_driver(via_sd_driver); -- cgit v1.2.3 From cdd2b769789ae1a030e1a26f6c37c5833cabcb34 Mon Sep 17 00:00:00 2001 From: shirley her Date: Mon, 20 Jul 2020 18:17:33 -0700 Subject: mmc: sdhci-pci-o2micro: Bug fix for O2 host controller Seabird1 To fix support for the O2 host controller Seabird1, set the quirk SDHCI_QUIRK2_PRESET_VALUE_BROKEN and the capability bit MMC_CAP2_NO_SDIO. Moreover, assign the ->get_cd() callback. Signed-off-by: Shirley Her Link: https://lore.kernel.org/r/20200721011733.8416-1-shirley.her@bayhubtech.com [Ulf: Updated the commit message] Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-pci-o2micro.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c index e2a846885902..ed3c605fcf0c 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c @@ -561,6 +561,12 @@ static int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; } + if (chip->pdev->device == PCI_DEVICE_ID_O2_SEABIRD1) { + slot->host->mmc_host_ops.get_cd = sdhci_o2_get_cd; + host->mmc->caps2 |= MMC_CAP2_NO_SDIO; + host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; + } + host->mmc_host_ops.execute_tuning = sdhci_o2_execute_tuning; if (chip->pdev->device != PCI_DEVICE_ID_O2_FUJIN2) -- cgit v1.2.3 From 7b7d897e8898603ac014ba07f203b9f8c4fa7952 Mon Sep 17 00:00:00 2001 From: shirley her Date: Mon, 20 Jul 2020 18:27:00 -0700 Subject: mmc: sdhci-pci-o2micro: Add HW tuning for SDR104 mode Add HW tuning support for SD host controller in SDR104 mode Signed-off-by: Shirley Her Link: https://lore.kernel.org/r/20200721012700.8564-1-shirley.her@bayhubtech.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/sdhci-pci-o2micro.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-pci-o2micro.c b/drivers/mmc/host/sdhci-pci-o2micro.c index ed3c605fcf0c..fa76748d8929 100644 --- a/drivers/mmc/host/sdhci-pci-o2micro.c +++ b/drivers/mmc/host/sdhci-pci-o2micro.c @@ -196,7 +196,7 @@ static void __sdhci_o2_execute_tuning(struct sdhci_host *host, u32 opcode) { int i; - sdhci_send_tuning(host, MMC_SEND_TUNING_BLOCK_HS200); + sdhci_send_tuning(host, opcode); for (i = 0; i < 150; i++) { u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); @@ -305,10 +305,12 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) * This handler only implements the eMMC tuning that is specific to * this controller. Fall back to the standard method for other TIMING. */ - if (host->timing != MMC_TIMING_MMC_HS200) + if ((host->timing != MMC_TIMING_MMC_HS200) && + (host->timing != MMC_TIMING_UHS_SDR104)) return sdhci_execute_tuning(mmc, opcode); - if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200)) + if (WARN_ON((opcode != MMC_SEND_TUNING_BLOCK_HS200) && + (opcode != MMC_SEND_TUNING_BLOCK))) return -EINVAL; /* * Judge the tuning reason, whether caused by dll shift @@ -342,6 +344,9 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode) sdhci_set_bus_width(host, current_bus_width); } + sdhci_reset(host, SDHCI_RESET_CMD); + sdhci_reset(host, SDHCI_RESET_DATA); + host->flags &= ~SDHCI_HS400_TUNING; return 0; } @@ -369,7 +374,6 @@ static void o2_pci_led_enable(struct sdhci_pci_chip *chip) scratch_32 |= O2_SD_LED_ENABLE; pci_write_config_dword(chip->pdev, O2_SD_TEST_REG, scratch_32); - } static void sdhci_pci_o2_fujin2_pci_init(struct sdhci_pci_chip *chip) @@ -497,6 +501,10 @@ static void sdhci_o2_enable_clk(struct sdhci_host *host, u16 clk) static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) { u16 clk; + u8 scratch; + u32 scratch_32; + struct sdhci_pci_slot *slot = sdhci_priv(host); + struct sdhci_pci_chip *chip = slot->chip; host->mmc->actual_clock = 0; @@ -505,6 +513,23 @@ static void sdhci_pci_o2_set_clock(struct sdhci_host *host, unsigned int clock) if (clock == 0) return; + if ((host->timing == MMC_TIMING_UHS_SDR104) && (clock == 200000000)) { + pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); + + scratch &= 0x7f; + pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); + + pci_read_config_dword(chip->pdev, O2_SD_PLL_SETTING, &scratch_32); + + if ((scratch_32 & 0xFFFF0000) != 0x2c280000) + o2_pci_set_baseclk(chip, 0x2c280000); + + pci_read_config_byte(chip->pdev, O2_SD_LOCK_WP, &scratch); + + scratch |= 0x80; + pci_write_config_byte(chip->pdev, O2_SD_LOCK_WP, scratch); + } + clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); sdhci_o2_enable_clk(host, clk); } -- cgit v1.2.3 From 7d176b0ea6f0d45e32564770316df6671183136e Mon Sep 17 00:00:00 2001 From: Chun-Hung Wu Date: Mon, 20 Jul 2020 08:42:36 +0800 Subject: mmc: mediatek: add MT6779 MMC driver support Add new code to support MT6779 mmc driver. Signed-off-by: Chun-Hung Wu Link: https://lore.kernel.org/r/1595205759-5825-2-git-send-email-chun-hung.wu@mediatek.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/mtk-sd.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 49ac802ebbfe..d23f738b9cb7 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -538,6 +538,18 @@ static const struct mtk_mmc_compatible mt7620_compat = { .use_internal_cd = true, }; +static const struct mtk_mmc_compatible mt6779_compat = { + .clk_div_bits = 12, + .hs400_tune = false, + .pad_tune_reg = MSDC_PAD_TUNE0, + .async_fifo = true, + .data_tune = true, + .busy_check = true, + .stop_clk_fix = true, + .enhance_rx = true, + .support_64g = true, +}; + static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, @@ -547,6 +559,7 @@ static const struct of_device_id msdc_of_ids[] = { { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, + { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, {} }; MODULE_DEVICE_TABLE(of, msdc_of_ids); -- cgit v1.2.3 From 557011b6b8c87c10d8bd2ec4366d4b2a0614ffc8 Mon Sep 17 00:00:00 2001 From: Chun-Hung Wu Date: Mon, 20 Jul 2020 08:42:37 +0800 Subject: mmc: mediatek: refine msdc timeout api Extract msdc timeout api common part to have better code architecture and avoid redundant code. Signed-off-by: Chun-Hung Wu Reviewed-by: Matthias Brugger Link: https://lore.kernel.org/r/1595205759-5825-3-git-send-email-chun-hung.wu@mediatek.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/mtk-sd.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index d23f738b9cb7..933a09853908 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -723,21 +723,21 @@ static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) } } -/* clock control primitives */ -static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) +static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) { - u32 timeout, clk_ns; + u64 timeout, clk_ns; u32 mode = 0; - host->timeout_ns = ns; - host->timeout_clks = clks; if (host->mmc->actual_clock == 0) { timeout = 0; } else { - clk_ns = 1000000000UL / host->mmc->actual_clock; - timeout = (ns + clk_ns - 1) / clk_ns + clks; + clk_ns = 1000000000ULL; + do_div(clk_ns, host->mmc->actual_clock); + timeout = ns + clk_ns - 1; + do_div(timeout, clk_ns); + timeout += clks; /* in 1048576 sclk cycle unit */ - timeout = (timeout + (0x1 << 20) - 1) >> 20; + timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); if (host->dev_comp->clk_div_bits == 8) sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); @@ -747,9 +747,21 @@ static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) /*DDR mode will double the clk cycles for data timeout */ timeout = mode >= 2 ? timeout * 2 : timeout; timeout = timeout > 1 ? timeout - 1 : 0; - timeout = timeout > 255 ? 255 : timeout; } - sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); + return timeout; +} + +/* clock control primitives */ +static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + host->timeout_ns = ns; + host->timeout_clks = clks; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, + (u32)(timeout > 255 ? 255 : timeout)); } static void msdc_gate_clock(struct msdc_host *host) -- cgit v1.2.3 From 88bd652b3c74997bb436adf6131acf445066243e Mon Sep 17 00:00:00 2001 From: Chun-Hung Wu Date: Mon, 20 Jul 2020 08:42:38 +0800 Subject: mmc: mediatek: command queue support Support command queue for mt6779 platform. a. Add msdc_set_busy_timeout() to calculate emmc write timeout. b. Connect mtk msdc driver to cqhci driver through host->cq_host->ops = &msdc_cmdq_ops; c. msdc_cmdq_irq() will link up with cqchi_irq(). Besides, it provides more irq error messages like RSPCRCERR/CMDTO/DATACRCERR/DATTMO. d. Select kernel config MMC_CQHCI for MMC_MTK Signed-off-by: Chun-Hung Wu Acked-by: Yong Mao Link: https://lore.kernel.org/r/1595205759-5825-4-git-send-email-chun-hung.wu@mediatek.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/Kconfig | 1 + drivers/mmc/host/mtk-sd.c | 115 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 116 insertions(+) diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 3b706af35ec3..9c89a5b780e8 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -1009,6 +1009,7 @@ config MMC_MTK tristate "MediaTek SD/MMC Card Interface support" depends on HAS_DMA select REGULATOR + select MMC_CQHCI help This selects the MediaTek(R) Secure digital and Multimedia card Interface. If you have a machine with a integrated SD/MMC card reader, say Y or M here. diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 933a09853908..734e403a142e 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -31,6 +31,8 @@ #include #include +#include "cqhci.h" + #define MAX_BD_NUM 1024 /*--------------------------------------------------------------------------*/ @@ -152,6 +154,7 @@ #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ +#define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ /* MSDC_INTEN mask */ #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ @@ -182,6 +185,7 @@ /* SDC_CFG mask */ #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ +#define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ #define SDC_CFG_SDIO (0x1 << 19) /* RW */ #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ @@ -230,6 +234,7 @@ #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ +#define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ @@ -431,9 +436,11 @@ struct msdc_host { /* cmd response sample selection for HS400 */ bool hs400_mode; /* current eMMC will run at hs400 mode */ bool internal_cd; /* Use internal card-detect logic */ + bool cqhci; /* support eMMC hw cmdq */ struct msdc_save_para save_para; /* used when gate HCLK */ struct msdc_tune_para def_tune_para; /* default tune setting */ struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ + struct cqhci_host *cq_host; }; static const struct mtk_mmc_compatible mt8135_compat = { @@ -764,6 +771,15 @@ static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) (u32)(timeout > 255 ? 255 : timeout)); } +static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) +{ + u64 timeout; + + timeout = msdc_timeout_cal(host, ns, clks); + sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, + (u32)(timeout > 8191 ? 8191 : timeout)); +} + static void msdc_gate_clock(struct msdc_host *host) { clk_disable_unprepare(host->src_clk_cg); @@ -1480,6 +1496,34 @@ static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) pm_runtime_put_noidle(host->dev); } +static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) +{ + int cmd_err = 0, dat_err = 0; + + if (intsts & MSDC_INT_RSPCRCERR) { + cmd_err = -EILSEQ; + dev_err(host->dev, "%s: CMD CRC ERR", __func__); + } else if (intsts & MSDC_INT_CMDTMO) { + cmd_err = -ETIMEDOUT; + dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); + } + + if (intsts & MSDC_INT_DATCRCERR) { + dat_err = -EILSEQ; + dev_err(host->dev, "%s: DATA CRC ERR", __func__); + } else if (intsts & MSDC_INT_DATTMO) { + dat_err = -ETIMEDOUT; + dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); + } + + if (cmd_err || dat_err) { + dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", + cmd_err, dat_err, intsts); + } + + return cqhci_irq(host->mmc, 0, cmd_err, dat_err); +} + static irqreturn_t msdc_irq(int irq, void *dev_id) { struct msdc_host *host = (struct msdc_host *) dev_id; @@ -1516,6 +1560,14 @@ static irqreturn_t msdc_irq(int irq, void *dev_id) if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) break; + if ((host->mmc->caps2 & MMC_CAP2_CQE) && + (events & MSDC_INT_CMDQ)) { + msdc_cmdq_irq(host, events); + /* clear interrupts */ + writel(events, host->base + MSDC_INT); + return IRQ_HANDLED; + } + if (!mrq) { dev_err(host->dev, "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", @@ -2200,6 +2252,36 @@ static int msdc_get_cd(struct mmc_host *mmc) return !val; } +static void msdc_cqe_enable(struct mmc_host *mmc) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* enable cmdq irq */ + writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); + /* enable busy check */ + sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + /* default write data / busy timeout 20s */ + msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); + /* default read data timeout 1s */ + msdc_set_timeout(host, 1000000000ULL, 0); +} + +void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) +{ + struct msdc_host *host = mmc_priv(mmc); + + /* disable cmdq irq */ + sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); + /* disable busy check */ + sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); + + if (recovery) { + sdr_set_field(host->base + MSDC_DMA_CTRL, + MSDC_DMA_CTRL_STOP, 1); + msdc_reset_hw(host); + } +} + static const struct mmc_host_ops mt_msdc_ops = { .post_req = msdc_post_req, .pre_req = msdc_pre_req, @@ -2216,6 +2298,11 @@ static const struct mmc_host_ops mt_msdc_ops = { .hw_reset = msdc_hw_reset, }; +static const struct cqhci_host_ops msdc_cmdq_ops = { + .enable = msdc_cqe_enable, + .disable = msdc_cqe_disable, +}; + static void msdc_of_property_parse(struct platform_device *pdev, struct msdc_host *host) { @@ -2236,6 +2323,12 @@ static void msdc_of_property_parse(struct platform_device *pdev, host->hs400_cmd_resp_sel_rising = true; else host->hs400_cmd_resp_sel_rising = false; + + if (of_property_read_bool(pdev->dev.of_node, + "supports-cqe")) + host->cqhci = true; + else + host->cqhci = false; } static int msdc_drv_probe(struct platform_device *pdev) @@ -2351,6 +2444,8 @@ static int msdc_drv_probe(struct platform_device *pdev) mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; mmc->caps |= MMC_CAP_CMD23; + if (host->cqhci) + mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; /* MMC core transfer sizes tunable parameters */ mmc->max_segs = MAX_BD_NUM; if (host->dev_comp->support_64g) @@ -2366,6 +2461,26 @@ static int msdc_drv_probe(struct platform_device *pdev) host->dma_mask = DMA_BIT_MASK(32); mmc_dev(mmc)->dma_mask = &host->dma_mask; + if (mmc->caps2 & MMC_CAP2_CQE) { + host->cq_host = devm_kzalloc(host->mmc->parent, + sizeof(*host->cq_host), + GFP_KERNEL); + if (!host->cq_host) { + ret = -ENOMEM; + goto host_free; + } + host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; + host->cq_host->mmio = host->base + 0x800; + host->cq_host->ops = &msdc_cmdq_ops; + ret = cqhci_init(host->cq_host, mmc, true); + if (ret) + goto host_free; + mmc->max_segs = 128; + /* cqhci 16bit length */ + /* 0 size, means 65536 so we don't have to -1 here */ + mmc->max_seg_size = 64 * 1024; + } + host->timeout_clks = 3 * 1048576; host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2 * sizeof(struct mt_gpdma_desc), -- cgit v1.2.3 From ac42e4e906b64be68434452c3ad14cb6ef2d1774 Mon Sep 17 00:00:00 2001 From: Chun-Hung Wu Date: Mon, 20 Jul 2020 08:42:39 +0800 Subject: dt-bindings: mmc: mediatek: Add document for mt6779 Add compatible node for mt6779 mmc. Signed-off-by: Chun-Hung Wu Acked-by: Rob Herring Link: https://lore.kernel.org/r/1595205759-5825-5-git-send-email-chun-hung.wu@mediatek.com Signed-off-by: Ulf Hansson --- Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt index 8a532f4453f2..0c9cf6a8808c 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt @@ -12,6 +12,7 @@ Required properties: "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173 "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183 "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516 + "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779 "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701 "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712 "mediatek,mt7622-mmc": for MT7622 SoC -- cgit v1.2.3 From 804f178612afa1dffe0c7b84596ef97374944eb6 Mon Sep 17 00:00:00 2001 From: Ludovic Desroches Date: Thu, 9 Jul 2020 10:53:31 +0200 Subject: MAINTAINERS: mmc: sdhci-of-at91: handover maintenance to Eugen Hristev As Eugen handles the software for bootloaders and new products, handover the maintenance to him. Signed-off-by: Ludovic Desroches Acked-by: Eugen Hristev Link: https://lore.kernel.org/r/20200709085331.8145-1-ludovic.desroches@microchip.com Signed-off-by: Ulf Hansson --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index b4a43a9e7fbc..39c6ec685e2d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15297,7 +15297,7 @@ F: drivers/mmc/host/sdhci* F: include/linux/mmc/sdhci* SECURE DIGITAL HOST CONTROLLER INTERFACE (SDHCI) MICROCHIP DRIVER -M: Ludovic Desroches +M: Eugen Hristev L: linux-mmc@vger.kernel.org S: Supported F: drivers/mmc/host/sdhci-of-at91.c -- cgit v1.2.3 From 7f4bc2e8687ecea52177aac30fb153cc076f7022 Mon Sep 17 00:00:00 2001 From: Wei Yongjun Date: Tue, 28 Jul 2020 01:11:29 +0800 Subject: mmc: mediatek: make function msdc_cqe_disable() static The sparse tool complains as follows: drivers/mmc/host/mtk-sd.c:2269:6: warning: symbol 'msdc_cqe_disable' was not declared. Should it be static? This function is not used outside of mtk-sd.c, so this commit marks it static. Fixes: 88bd652b3c74 ("mmc: mediatek: command queue support") Reported-by: Hulk Robot Signed-off-by: Wei Yongjun Acked-by: Chun-Hung Wu Link: https://lore.kernel.org/r/20200727171129.2945-1-weiyongjun1@huawei.com Signed-off-by: Ulf Hansson --- drivers/mmc/host/mtk-sd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 734e403a142e..4e2583f69a63 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -2266,7 +2266,7 @@ static void msdc_cqe_enable(struct mmc_host *mmc) msdc_set_timeout(host, 1000000000ULL, 0); } -void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) +static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) { struct msdc_host *host = mmc_priv(mmc); -- cgit v1.2.3