From 870b8e3d1da957e26e6b91e9a43d5773d34ad396 Mon Sep 17 00:00:00 2001 From: Pierre-Henry Moussay Date: Mon, 30 Sep 2024 10:54:42 +0100 Subject: dt-bindings: rtc: mpfs-rtc: Add PIC64GX compatibility PIC64GX is compatible with mfps-rtc without any additional feature Signed-off-by: Pierre-Henry Moussay Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20240930095449.1813195-14-pierre-henry.moussay@microchip.com Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) (limited to 'Documentation/devicetree/bindings/rtc') diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml index 7742465b9383..ba602b1c8799 100644 --- a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml @@ -16,8 +16,11 @@ maintainers: properties: compatible: - enum: - - microchip,mpfs-rtc + oneOf: + - items: + - const: microchip,pic64gx-rtc + - const: microchip,mpfs-rtc + - const: microchip,mpfs-rtc reg: maxItems: 1 -- cgit v1.2.3 From f8560812be1d1df29291b7c3e2fc6e648dc8544a Mon Sep 17 00:00:00 2001 From: Alexandre Belloni Date: Fri, 11 Oct 2024 12:06:07 +0200 Subject: dt-bindings: rtc: mpfs-rtc: Properly name file The actual compatible string is microchip,mpfs-rtc, not microchip,mfps-rtc. Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20241011100608.862428-1-alexandre.belloni@bootlin.com Signed-off-by: Alexandre Belloni --- .../bindings/rtc/microchip,mfps-rtc.yaml | 70 ---------------------- .../bindings/rtc/microchip,mpfs-rtc.yaml | 70 ++++++++++++++++++++++ 2 files changed, 70 insertions(+), 70 deletions(-) delete mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mpfs-rtc.yaml (limited to 'Documentation/devicetree/bindings/rtc') diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml deleted file mode 100644 index ba602b1c8799..000000000000 --- a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml +++ /dev/null @@ -1,70 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# - -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Microchip PolarFire Soc (MPFS) RTC - -allOf: - - $ref: rtc.yaml# - -maintainers: - - Daire McNamara - - Lewis Hanly - -properties: - compatible: - oneOf: - - items: - - const: microchip,pic64gx-rtc - - const: microchip,mpfs-rtc - - const: microchip,mpfs-rtc - - reg: - maxItems: 1 - - interrupts: - items: - - description: | - RTC_WAKEUP interrupt - - description: | - RTC_MATCH, asserted when the content of the Alarm register is equal - to that of the RTC's count register. - - clocks: - items: - - description: | - AHB clock - - description: | - Reference clock: divided by the prescaler to create a time-based - strobe (typically 1 Hz) for the calendar counter. By default, the rtc - on the PolarFire SoC shares it's reference with MTIMER so this will - be a 1 MHz clock. - - clock-names: - items: - - const: rtc - - const: rtcref - -required: - - compatible - - reg - - interrupts - - clocks - - clock-names - -additionalProperties: false - -examples: - - | - #include "dt-bindings/clock/microchip,mpfs-clock.h" - rtc@20124000 { - compatible = "microchip,mpfs-rtc"; - reg = <0x20124000 0x1000>; - clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; - clock-names = "rtc", "rtcref"; - interrupts = <80>, <81>; - }; -... diff --git a/Documentation/devicetree/bindings/rtc/microchip,mpfs-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mpfs-rtc.yaml new file mode 100644 index 000000000000..7e58c660c0ff --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/microchip,mpfs-rtc.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/microchip,mpfs-rtc.yaml# + +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire Soc (MPFS) RTC + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Daire McNamara + - Lewis Hanly + +properties: + compatible: + oneOf: + - items: + - const: microchip,pic64gx-rtc + - const: microchip,mpfs-rtc + - const: microchip,mpfs-rtc + + reg: + maxItems: 1 + + interrupts: + items: + - description: | + RTC_WAKEUP interrupt + - description: | + RTC_MATCH, asserted when the content of the Alarm register is equal + to that of the RTC's count register. + + clocks: + items: + - description: | + AHB clock + - description: | + Reference clock: divided by the prescaler to create a time-based + strobe (typically 1 Hz) for the calendar counter. By default, the rtc + on the PolarFire SoC shares it's reference with MTIMER so this will + be a 1 MHz clock. + + clock-names: + items: + - const: rtc + - const: rtcref + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include "dt-bindings/clock/microchip,mpfs-clock.h" + rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0x20124000 0x1000>; + clocks = <&clkcfg CLK_RTC>, <&clkcfg CLK_RTCREF>; + clock-names = "rtc", "rtcref"; + interrupts = <80>, <81>; + }; +... -- cgit v1.2.3 From 71c61a45c951eca67dd2cbc4de9cdd687ece4ead Mon Sep 17 00:00:00 2001 From: Claudiu Beznea Date: Wed, 30 Oct 2024 13:01:14 +0200 Subject: dt-bindings: rtc: renesas,rzg3s-rtc: Document the Renesas RTCA-3 IP Document the RTC IP (RTCA-3) available on the Renesas RZ/G3S SoC. The RTC IP available on Renesas RZ/V2H is almost identical with the one found on Renesas RZ/G3S (it misses the time capture functionality which is not yet implemented on proposed driver). For this, added also a generic compatible that will be used at the moment as fallback for both RZ/G3S and RZ/V2H. Reviewed-by: Rob Herring (Arm) Signed-off-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20241030110120.332802-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/rtc/renesas,rz-rtca3.yaml | 84 ++++++++++++++++++++++ 1 file changed, 84 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml (limited to 'Documentation/devicetree/bindings/rtc') diff --git a/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml new file mode 100644 index 000000000000..e70eeb66aa64 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/renesas,rz-rtca3.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/renesas,rz-rtca3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RTCA-3 Real Time Clock + +maintainers: + - Claudiu Beznea + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + items: + - enum: + - renesas,r9a08g045-rtca3 # RZ/G3S + - const: renesas,rz-rtca3 + + reg: + maxItems: 1 + + interrupts: + items: + - description: Alarm interrupt + - description: Periodic interrupt + - description: Carry interrupt + + interrupt-names: + items: + - const: alarm + - const: period + - const: carry + + clocks: + items: + - description: RTC bus clock + - description: RTC counter clock + + clock-names: + items: + - const: bus + - const: counter + + power-domains: + maxItems: 1 + + resets: + items: + - description: VBATTB module reset + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + rtc@1004ec00 { + compatible = "renesas,r9a08g045-rtca3", "renesas,rz-rtca3"; + reg = <0x1004ec00 0x400>; + interrupts = , + , + ; + interrupt-names = "alarm", "period", "carry"; + clocks = <&cpg CPG_MOD R9A08G045_VBAT_BCLK>, <&vbattclk VBATTB_VBATTCLK>; + clock-names = "bus", "counter"; + power-domains = <&cpg>; + resets = <&cpg R9A08G045_VBAT_BRESETN>; + }; -- cgit v1.2.3 From d93f8ac23b505fc3971ab6e957735194de7f02bc Mon Sep 17 00:00:00 2001 From: Conor Dooley Date: Tue, 15 Oct 2024 07:52:05 +0100 Subject: dt-bindings: rtc: mpfs-rtc: remove Lewis from maintainers Lewis hasn't worked at Microchip for a while, and IIRC never actually worked on the RTC in the first place. Remove him from the maintainers list in the binding, leaving Daire. Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20241015-surcharge-caucasian-095d1fd2fa27@wendy Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/microchip,mpfs-rtc.yaml | 1 - 1 file changed, 1 deletion(-) (limited to 'Documentation/devicetree/bindings/rtc') diff --git a/Documentation/devicetree/bindings/rtc/microchip,mpfs-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mpfs-rtc.yaml index 7e58c660c0ff..a3e60d9f8399 100644 --- a/Documentation/devicetree/bindings/rtc/microchip,mpfs-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/microchip,mpfs-rtc.yaml @@ -12,7 +12,6 @@ allOf: maintainers: - Daire McNamara - - Lewis Hanly properties: compatible: -- cgit v1.2.3 From 9beeecbd63d5187a3f86be57e7d06a072777433c Mon Sep 17 00:00:00 2001 From: Andre Przywara Date: Mon, 11 Nov 2024 01:30:29 +0000 Subject: dt-bindings: rtc: sun6i: Add Allwinner A523 support The RTC in the Allwinner A523 SoC is compatible to the D1 and R329, so just add its name and use the R329 as a fallback. Signed-off-by: Andre Przywara Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20241111013033.22793-11-andre.przywara@arm.com Signed-off-by: Alexandre Belloni --- Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'Documentation/devicetree/bindings/rtc') diff --git a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml index 4531eec568a6..9df5cdb6f63f 100644 --- a/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml @@ -30,7 +30,9 @@ properties: - const: allwinner,sun50i-a64-rtc - const: allwinner,sun8i-h3-rtc - items: - - const: allwinner,sun20i-d1-rtc + - enum: + - allwinner,sun20i-d1-rtc + - allwinner,sun55i-a523-rtc - const: allwinner,sun50i-r329-rtc reg: -- cgit v1.2.3 From ce57cf7319e5315637349c02b50a51b2d2efba89 Mon Sep 17 00:00:00 2001 From: Yiting Deng Date: Tue, 12 Nov 2024 11:10:14 +0800 Subject: dt-bindings: rtc: Add Amlogic A4 and A5 RTC Add documentation describing the Amlogic A4(A113L2) and A5(A113X2) RTC. Signed-off-by: Yiting Deng Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xianwei Zhao Link: https://lore.kernel.org/r/20241112-rtc-v6-1-a71b60d2f354@amlogic.com Signed-off-by: Alexandre Belloni --- .../devicetree/bindings/rtc/amlogic,a4-rtc.yaml | 63 ++++++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/amlogic,a4-rtc.yaml (limited to 'Documentation/devicetree/bindings/rtc') diff --git a/Documentation/devicetree/bindings/rtc/amlogic,a4-rtc.yaml b/Documentation/devicetree/bindings/rtc/amlogic,a4-rtc.yaml new file mode 100644 index 000000000000..5d3ac737abcb --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/amlogic,a4-rtc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/amlogic,a4-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Amlogic A4 and A5 RTC + +maintainers: + - Yiting Deng + - Xianwei Zhao + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + enum: + - amlogic,a4-rtc + - amlogic,a5-rtc + + reg: + maxItems: 1 + + clocks: + items: + - description: RTC clock source, available 24M or 32K crystal + oscillator source. when using 24M, need to divide 24M into 32K. + - description: RTC module accesses the clock of the apb bus. + + clock-names: + items: + - const: osc + - const: sys + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + #include + apb { + #address-cells = <2>; + #size-cells = <2>; + + rtc@8e600 { + compatible = "amlogic,a4-rtc"; + reg = <0x0 0x8e600 0x0 0x38>; + clocks = <&xtal_32k>, <&clkc_periphs 1>; + clock-names = "osc", "sys"; + interrupts = ; + }; + }; -- cgit v1.2.3