From ffb8b1ee9a704229f0b6753970ae09dc4d6863d9 Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Wed, 18 Mar 2015 02:14:07 +0900 Subject: ARM: dts: add async-bridge clocks to disp1 power domain for exynos5420 FIMD and MIXER IPs in disp1 power domain have async-bridges (to GSCALER), therefore their clocks should be enabled during power domain switch. Signed-off-by: Andrzej Hajda Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Reviewed-by: Sylwester Nawrocki Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 9dc2e9773b30..ac0fc09cdb40 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -283,9 +283,11 @@ <&clock CLK_MOUT_SW_ACLK300>, <&clock CLK_MOUT_USER_ACLK300_DISP1>, <&clock CLK_MOUT_SW_ACLK400>, - <&clock CLK_MOUT_USER_ACLK400_DISP1>; + <&clock CLK_MOUT_USER_ACLK400_DISP1>, + <&clock CLK_FIMD1>, <&clock CLK_MIXER>; clock-names = "oscclk", "pclk0", "clk0", - "pclk1", "clk1", "pclk2", "clk2"; + "pclk1", "clk1", "pclk2", "clk2", + "asb0", "asb1"; }; pinctrl_0: pinctrl@13400000 { -- cgit v1.2.3 From fa87bd4360ab4244467571f4235ccb2b362fea24 Mon Sep 17 00:00:00 2001 From: Andrzej Hajda Date: Wed, 18 Mar 2015 02:14:07 +0900 Subject: ARM: dts: add async-bridge clocks to gsc power domain for exynos5420 Both GSCALER IPs in gsc power domain have async-bridges (to FIMD and MIXER), therefore their clocks should be enabled during power domain switch. Signed-off-by: Andrzej Hajda Reviewed-by: Javier Martinez Canillas Tested-by: Javier Martinez Canillas Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5420.dtsi | 2 ++ 1 file changed, 2 insertions(+) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index ac0fc09cdb40..d4d643eac6b7 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -251,6 +251,8 @@ compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; #power-domain-cells = <0>; + clocks = <&clock CLK_GSCL0>, <&clock CLK_GSCL1>; + clock-names = "asb0", "asb1"; }; isp_pd: power-domain@10044020 { -- cgit v1.2.3 From f27b907595fc586bce62b8a3dc421e89bb927250 Mon Sep 17 00:00:00 2001 From: Anand Moon Date: Fri, 27 Mar 2015 01:55:10 +0900 Subject: ARM: dts: Fixed typo interrupt-cells for exynos5420 and exynos5250 Changes fixes the misspelled of #interrups-cell. arch/arm/boot/dts/exynos5420.dtsi:224: WARNING: 'interrups' may be misspelled - perhaps 'interrupts'? Tested on OdroidXU3 board. Signed-off-by: Anand Moon [kgene@kernel.org: added fixing same typo in exynos5250] Signed-off-by: Kukjin Kim --- arch/arm/boot/dts/exynos5250.dtsi | 2 +- arch/arm/boot/dts/exynos5420.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'arch/arm/boot/dts/exynos5420.dtsi') diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 9bb1b0b738f5..c411bdf3dc0a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -134,7 +134,7 @@ compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; interrupt-controller; - #interrups-cells = <2>; + #interrupt-cells = <2>; interrupt-parent = <&mct_map>; interrupts = <0 0>, <1 0>, <2 0>, <3 0>, <4 0>, <5 0>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index d4d643eac6b7..bff96e383785 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -221,7 +221,7 @@ compatible = "samsung,exynos4210-mct"; reg = <0x101C0000 0x800>; interrupt-controller; - #interrups-cells = <1>; + #interrupt-cells = <1>; interrupt-parent = <&mct_map>; interrupts = <0>, <1>, <2>, <3>, <4>, <5>, <6>, <7>, <8>, <9>, <10>, <11>; -- cgit v1.2.3