From a08f9db4646ed3f4c046f1740568772537367f58 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 Sep 2016 20:23:23 +0200 Subject: ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h The gt90h tablet has a gsl3675 touchscreen, add a dt node describing it. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts index f27ebbbeac09..e3c7a25ca37d 100644 --- a/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts +++ b/arch/arm/boot/dts/sun8i-a23-gt90h-v4.dts @@ -53,6 +53,15 @@ status = "okay"; }; +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl3675"; + firmware-name = "gsl3675-gt90h.fw"; + touchscreen-size-x = <1792>; + touchscreen-size-y = <1024>; + status = "okay"; +}; + &lradc { button@600 { label = "Back"; -- cgit v1.2.3 From 9fae0a1cc41d0a965c03099baf12d3d19b178636 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 Sep 2016 20:23:24 +0200 Subject: ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz The inet86dz tablet has a gsl1680 touchscreen, add a dt node describing it. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-inet86dz.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23-inet86dz.dts b/arch/arm/boot/dts/sun8i-a23-inet86dz.dts index 0f9f71b14047..d4405752a414 100644 --- a/arch/arm/boot/dts/sun8i-a23-inet86dz.dts +++ b/arch/arm/boot/dts/sun8i-a23-inet86dz.dts @@ -53,6 +53,15 @@ status = "okay"; }; +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl1680"; + firmware-name = "gsl1680-inet86dz.fw"; + touchscreen-size-x = <960>; + touchscreen-size-y = <640>; + status = "okay"; +}; + &usbphy { usb1_vbus-supply = <®_dldo1>; }; -- cgit v1.2.3 From 072c3d7e007d51405729e9fc4aeb8fe46687ba86 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 Sep 2016 20:23:25 +0200 Subject: ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03 Add a node enabling the gsl1680 touchscreen controller found on sun8i-a23-polaroid-mid2407pxe03 tablets. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts index 4789aac89955..6662127c688f 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -90,3 +90,22 @@ allwinner,pull = ; }; }; + +®_ldo_io1 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-touchscreen"; + status = "okay"; +}; + +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl1680"; + firmware-name = "gsl1680-polaroid-mid2407pxe03.fw"; + touchscreen-size-x = <960>; + touchscreen-size-y = <640>; + touchscreen-inverted-x; + touchscreen-inverted-y; + vddio-supply = <®_ldo_io1>; + status = "okay"; +}; -- cgit v1.2.3 From a8da66f45467bd2bc304f12c9363df786c3dae51 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 Sep 2016 20:23:26 +0200 Subject: ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04 Add a node enabling the gsl3670 touchscreen controller found on sun8i-a23-polaroid-mid2809pxe04 tablets. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts index c9213caf7424..9955f85f9147 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2809pxe04.dts @@ -90,3 +90,12 @@ allwinner,pull = ; }; }; + +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl3670"; + firmware-name = "gsl3670-polaroid-mid2809pxe04.fw"; + touchscreen-size-x = <1660>; + touchscreen-size-y = <890>; + status = "okay"; +}; -- cgit v1.2.3 From 303146d220532a7a729ccc4da58312b80e70998f Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Sun, 11 Sep 2016 20:23:27 +0200 Subject: ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h The ga10h tablet has a gsl3675 touchscreen, add a dt node describing it. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts index de6269dcac3a..f71159987cac 100644 --- a/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts +++ b/arch/arm/boot/dts/sun8i-a33-ga10h-v1.1.dts @@ -58,6 +58,16 @@ status = "okay"; }; +&touchscreen { + reg = <0x40>; + compatible = "silead,gsl3675"; + firmware-name = "gsl3675-ga10h.fw"; + touchscreen-size-x = <1630>; + touchscreen-size-y = <990>; + touchscreen-inverted-y; + status = "okay"; +}; + &lradc { button@600 { label = "Back"; -- cgit v1.2.3 From fb455eda3f2b4e4b983b0d2f4e1166704793d4f0 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 27 Aug 2016 15:55:40 +0800 Subject: ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused The AXP809's SW (switch) regulator is unused on the A80 Optimus. Add an empty node for it so that the OS can generate constraints. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index fd874ded890e..caf0091e71ba 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -325,6 +325,10 @@ reg_rtc_ldo: rtc_ldo { regulator-name = "vcc-rtc-vdd1v8-io"; }; + + sw { + /* unused */ + }; }; }; -- cgit v1.2.3 From 296450c208ad5c2de9a0ece4f71d9754b89c0913 Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 27 Aug 2016 15:55:41 +0800 Subject: ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused The AXP809's SW (switch) regulator is unused on the Cubieboard 4. Add an empty node for it so that the OS can generate constraints. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 04b014603659..910b29f0f0b5 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -253,6 +253,10 @@ reg_rtc_ldo: rtc_ldo { regulator-name = "vcc-rtc-vdd1v8-io"; }; + + sw { + /* unused */ + }; }; }; -- cgit v1.2.3 From 17b7eef1873c782bf27920e8415610d4c80824ef Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 27 Aug 2016 15:55:42 +0800 Subject: ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators The AXP806 PMIC is the secondary PMIC. It provides various supply voltages for the SoC and other peripherals. The PMIC's interrupt line is connected to NMI pin of the SoC. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 113 ++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index caf0091e71ba..d805cb50b5c8 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -332,6 +332,118 @@ }; }; + axp806: pmic@745 { + compatible = "x-powers,axp806"; + reg = <0x745>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + bldoin-supply = <®_dcdce>; + + regulators { + reg_s_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; + }; + + aldo2 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo2"; + }; + + aldo3 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo3"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = "vcc18-efuse-adc-display-csi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = + "vdd18-drampll-vcc18-pll-cpvdd"; + }; + + bldo3 { + /* unused */ + }; + + reg_bldo4: bldo4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vcc12-hsic"; + }; + + reg_cldo1: cldo1 { + /* + * This was 3V in the original design, but + * 3.3V is the recommended supply voltage + * for the Ethernet PHY. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-gmac-phy"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "afvcc-cam"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io-wifi-codec-io2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-vpu"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-name = "vcc-bldo-codec-ldoin"; + }; + + sw { + /* + * unused, but use a different name to + * avoid name clash with axp809's sw + */ + regulator-name = "s_sw"; + }; + }; + }; + ac100: codec@e89 { compatible = "x-powers,ac100"; reg = <0xe89>; @@ -371,6 +483,7 @@ }; &usbphy2 { + phy-supply = <®_bldo4>; status = "okay"; }; -- cgit v1.2.3 From f97f02eef2b218e2d963b6f9c3e91380ab1cb0cf Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 27 Aug 2016 15:55:43 +0800 Subject: ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators The AXP806 PMIC is the secondary PMIC. It provides various supply voltages for the SoC and other peripherals. The PMIC's interrupt line is connected to NMI pin of the SoC. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-cubieboard4.dts | 112 ++++++++++++++++++++++++++++ 1 file changed, 112 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts index 910b29f0f0b5..439847acd41e 100644 --- a/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts +++ b/arch/arm/boot/dts/sun9i-a80-cubieboard4.dts @@ -260,6 +260,118 @@ }; }; + axp806: pmic@745 { + compatible = "x-powers,axp806"; + reg = <0x745>; + interrupt-parent = <&nmi_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + bldoin-supply = <®_dcdce>; + + regulators { + reg_s_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "avcc"; + }; + + aldo2 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo2"; + }; + + aldo3 { + /* + * unused, but use a different name to + * avoid name clash with axp809's aldo's + */ + regulator-name = "s_aldo3"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = "vcc18-efuse-adc-display-csi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + regulator-name = + "vdd18-drampll-vcc18-pll-cpvdd"; + }; + + bldo3 { + /* unused */ + }; + + reg_bldo4: bldo4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + regulator-name = "vcc12-hsic"; + }; + + reg_cldo1: cldo1 { + /* + * This was 3V in the original design, but + * 3.3V is the recommended supply voltage + * for the Ethernet PHY. + */ + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-gmac-phy"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-name = "afvcc-cam"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-name = "vcc-io-wifi-codec-io2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-cpub"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-name = "vdd-vpu"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <2100000>; + regulator-max-microvolt = <2100000>; + regulator-name = "vcc-bldo-codec-ldoin"; + }; + + sw { + /* + * unused, but use a different name to + * avoid name clash with axp809's sw + */ + regulator-name = "s_sw"; + }; + }; + }; + ac100: codec@e89 { compatible = "x-powers,ac100"; reg = <0xe89>; -- cgit v1.2.3 From 013ace36f89b38c59a0adb5ffe215dab6eeabb2f Mon Sep 17 00:00:00 2001 From: Chen-Yu Tsai Date: Sat, 27 Aug 2016 15:55:44 +0800 Subject: ARM: dts: sun9i: a80-optimus: Disable EHCI1 EHCI1 provides an HSIC interface. This interface is exposed on the board through two pins among the GPIO header. With the PHY now powered up and responding, enabling the interface when nothing is connected results in a lot of error messages: usb 2-1: device descriptor read/64, error -71 usb 2-1: device descriptor read/64, error -71 usb 2-1: new high-speed USB device number 3 using ehci-platform usb 2-1: device descriptor read/64, error -71 usb 2-1: device descriptor read/64, error -71 usb 2-1: new high-speed USB device number 4 using ehci-platform usb 2-1: device not accepting address 4, error -71 usb 2-1: new high-speed USB device number 5 using ehci-platform usb 2-1: device not accepting address 5, error -71 usb usb2-port1: unable to enumerate USB device Disable it by default, but leave the entries in the board DTS. Signed-off-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun9i-a80-optimus.dts | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun9i-a80-optimus.dts b/arch/arm/boot/dts/sun9i-a80-optimus.dts index d805cb50b5c8..ceb6ef15d669 100644 --- a/arch/arm/boot/dts/sun9i-a80-optimus.dts +++ b/arch/arm/boot/dts/sun9i-a80-optimus.dts @@ -112,7 +112,8 @@ }; &ehci1 { - status = "okay"; + /* Enable if HSIC peripheral is connected */ + status = "disabled"; }; &ehci2 { @@ -484,7 +485,8 @@ &usbphy2 { phy-supply = <®_bldo4>; - status = "okay"; + /* Enable if HSIC peripheral is connected */ + status = "disabled"; }; &usbphy3 { -- cgit v1.2.3 From e3d11d3c45c5ef6dac68b49f68ce2bc6d6ddefce Mon Sep 17 00:00:00 2001 From: Jorik Jonker Date: Mon, 12 Sep 2016 20:12:43 +0200 Subject: dts: sun8i-h3: add pinmux definitions for UART2-3 These are the pinmux definitions for UART2-3 on H3. These UARTs can only be muxed to these pins, so _a and @0 do not really make sense. I have left out RTS/CTS, since these are rarely used. These can easily be enabled using an additional pinmux set. Signed-off-by: Jorik Jonker Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 6d83b8674201..9571512fdd77 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -373,6 +373,20 @@ allwinner,drive = ; allwinner,pull = ; }; + + uart2_pins: uart2 { + allwinner,pins = "PA0", "PA1"; + allwinner,function = "uart2"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart3_pins: uart3 { + allwinner,pins = "PG13", "PG14"; + allwinner,function = "uart3"; + allwinner,drive = ; + allwinner,pull = ; + }; }; timer@01c20c00 { -- cgit v1.2.3 From ae0fc941527cc74e7aeef700e5dbe07848a00bfb Mon Sep 17 00:00:00 2001 From: Jorik Jonker Date: Mon, 12 Sep 2016 20:12:44 +0200 Subject: dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux This was done to make UART1-3 on H3 consistent, and less complicated to enable UART1-3 on the breakout header on the several H3 board (notably Orange Pi's). This patch adds a bit of complexity for the existing Banana Pi, which already had the RTS/CTS associated on UART1. The RTS/CTS for UART2-3 could be defined in the same way, but since there is no actual use case for them at the moment, they are left out. Signed-off-by: Jorik Jonker Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts | 2 +- arch/arm/boot/dts/sun8i-h3.dtsi | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts index f3b1d5f6dbd2..06fddaae8edd 100644 --- a/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts @@ -185,7 +185,7 @@ &uart1 { pinctrl-names = "default"; - pinctrl-0 = <&uart1_pins_a>; + pinctrl-0 = <&uart1_pins>, <&uart1_rts_cts_pins>; status = "okay"; }; diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 9571512fdd77..83fcb6a2e618 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -367,8 +367,15 @@ allwinner,pull = ; }; - uart1_pins_a: uart1@0 { - allwinner,pins = "PG6", "PG7", "PG8", "PG9"; + uart1_pins: uart1 { + allwinner,pins = "PG6", "PG7"; + allwinner,function = "uart1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + uart1_rts_cts_pins: uart1_rts_cts { + allwinner,pins = "PG8", "PG9"; allwinner,function = "uart1"; allwinner,drive = ; allwinner,pull = ; -- cgit v1.2.3 From 33d9fc06cae240f1ba769caa40d5b023c0c38cee Mon Sep 17 00:00:00 2001 From: Jorik Jonker Date: Mon, 12 Sep 2016 20:12:45 +0200 Subject: dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards These H3 boards all expose UART1-3 on their expansion header. Since other functions can be muxed to these pins, they are explicitly disabled. To enable them, one could use DT overlays or U-boot commands: => fdt set /soc/serial@01c28c00 status okay Signed-off-by: Jorik Jonker Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3-orangepi-2.dts | 18 ++++++++++++++++++ arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 18 ++++++++++++++++++ arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 18 ++++++++++++++++++ 3 files changed, 54 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts index f89fe00ddec5..e5bcaba3e87f 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-2.dts @@ -186,6 +186,24 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + &usb1_vbus_pin_a { allwinner,pins = "PG13"; }; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts index 0adf932fd923..5c9b5bfa5c21 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts @@ -139,6 +139,24 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + &usbphy { /* USB VBUS is always on */ status = "okay"; diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts index daf50b9a6657..3ec971285aa3 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts @@ -161,6 +161,24 @@ status = "okay"; }; +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "disabled"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "disabled"; +}; + &usbphy { /* USB VBUS is always on */ status = "okay"; -- cgit v1.2.3 From 85e6f7ff7d01b31c654295aaa09b9ed0fe914e98 Mon Sep 17 00:00:00 2001 From: Jorik Jonker Date: Mon, 12 Sep 2016 20:12:46 +0200 Subject: dts: sun8i-h3: add pinmux definitions for I2C0-2 These are the only possible pins for these peripherals according to the datasheet. Signed-off-by: Jorik Jonker Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 83fcb6a2e618..2c958c40bd92 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -327,6 +327,27 @@ interrupt-controller; #interrupt-cells = <3>; + i2c0_pins: i2c0 { + allwinner,pins = "PA11", "PA12"; + allwinner,function = "i2c0"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c1_pins: i2c1 { + allwinner,pins = "PA18", "PA19"; + allwinner,function = "i2c1"; + allwinner,drive = ; + allwinner,pull = ; + }; + + i2c2_pins: i2c2 { + allwinner,pins = "PE12", "PE13"; + allwinner,function = "i2c2"; + allwinner,drive = ; + allwinner,pull = ; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; -- cgit v1.2.3 From d8a507e6d9316b1023ba3cc9a7e696067200b495 Mon Sep 17 00:00:00 2001 From: Jorik Jonker Date: Mon, 12 Sep 2016 20:12:47 +0200 Subject: dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC These peripherals can only be muxed to these pins, so they are associated in the DTSI instead of the board files. This makes it very easy to enable them using overlays or u-boot commands: => fdt set /soc/i2c@01c2ac00 status okay Signed-off-by: Jorik Jonker Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-h3.dtsi | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 2c958c40bd92..99e66404d3b8 100644 --- a/arch/arm/boot/dts/sun8i-h3.dtsi +++ b/arch/arm/boot/dts/sun8i-h3.dtsi @@ -491,6 +491,45 @@ status = "disabled"; }; + i2c0: i2c@01c2ac00 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2ac00 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C0>; + resets = <&ccu RST_BUS_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c1: i2c@01c2b000 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C1>; + resets = <&ccu RST_BUS_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c2: i2c@01c2b400 { + compatible = "allwinner,sun6i-a31-i2c"; + reg = <0x01c2b000 0x400>; + interrupts = ; + clocks = <&ccu CLK_BUS_I2C2>; + resets = <&ccu RST_BUS_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gic: interrupt-controller@01c81000 { compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; reg = <0x01c81000 0x1000>, -- cgit v1.2.3 From 82eec384249fb4a58ad9b8946dc7623393311593 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 16 Sep 2016 23:16:41 +0800 Subject: ARM: dts: sun8i: add pinmux for UART1 at PG The UART1 at PG (PG6, PG7, PG8, PG9) is, in the Allwinner's reference tablet design of A23/33, used to connect to UART Bluetooth cards. Add the pinmux for it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-a33.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23-a33.dtsi b/arch/arm/boot/dts/sun8i-a23-a33.dtsi index 01d8bbf08749..ea4082cd111b 100644 --- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi @@ -279,6 +279,16 @@ allwinner,pull = ; }; + uart1_pins_a: uart1@0 { + allwinner,pins = "PG6", "PG7"; + allwinner,function = "uart1"; + }; + + uart1_pins_cts_rts_a: uart1-cts-rts@0 { + allwinner,pins = "PG8", "PG9"; + allwinner,function = "uart1"; + }; + mmc0_pins_a: mmc0@0 { allwinner,pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5"; -- cgit v1.2.3 From fef377702efc6c6ecab0c323dd72ede4a32fcb02 Mon Sep 17 00:00:00 2001 From: Icenowy Zheng Date: Fri, 16 Sep 2016 23:16:42 +0800 Subject: ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board UART1 is connected to the bluetooth part of RTL8723BS WiFi/BT combo card on iNet D978 Rev2 board. Enable the UART1 to make it possible to use the modified hciattach by Realtek to drive the BT part of RTL8723BS. On the board no r_uart pins are found now (the onboard RX/TX pins are wired to PF2/PF4, which is muxed with mmc0), so also disabled it. Signed-off-by: Icenowy Zheng Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts index 0f52cd9dfa41..fb4665576dff 100644 --- a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts +++ b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts @@ -49,6 +49,15 @@ model = "INet-D978 Rev 02"; compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33"; + aliases { + serial0 = &uart1; + }; + + chosen { + /* Delete debug UART as serial0 is the UART for bluetooth */ + /delete-property/stdout-path; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -86,3 +95,14 @@ allwinner,pull = ; }; }; + +&r_uart { + status = "disabled"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins_a>, + <&uart1_pins_cts_rts_a>; + status = "okay"; +}; -- cgit v1.2.3 From 90cb4b8c7e3af989c78227954e01455fc7c1e767 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Mon, 19 Sep 2016 12:39:25 +0200 Subject: ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03 Add a dt node describing the mma7660 accelerometer on the polaroid-mid2407pxe03 tablet. Signed-off-by: Hans de Goede Signed-off-by: Maxime Ripard --- arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'arch/arm') diff --git a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts index 6662127c688f..a86cbedda34c 100644 --- a/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts +++ b/arch/arm/boot/dts/sun8i-a23-polaroid-mid2407pxe03.dts @@ -62,6 +62,13 @@ }; }; +&i2c1 { + mma7660: accelerometer@4c { + reg = <0x4c>; + compatible = "fsl,mma7660"; + }; +}; + &mmc1 { pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins_a>; -- cgit v1.2.3