From 2b66f02e2de174c2a9bdf60160a1d9963dc7ca2c Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Tue, 30 Aug 2022 11:31:33 +0800 Subject: clk: imx: clk-composite-93: check white_list The CCM ROOT AUTHEN register WHITE_LIST indicate: Each bit in this field represent for one domain. Bit16~Bit31 represent for DOMAIN0~DOMAIN15 respectively. Only corresponding bit of the domains is set to 1 can change the registers of this Clock Root. i.MX93 DID is 3, so if BIT(3 + WHITE_LIST_SHIFT) is 0, the clk should be set to read only. To make the imx93_clk_composite_flags be reusable, add a new parameter named did(domain id); Signed-off-by: Peng Fan Reviewed-by: Ye Li Reviewed-by: Jacky Bai Reviewed-by: Abel Vesa Signed-off-by: Abel Vesa Link: https://lore.kernel.org/r/20220830033137.4149542-5-peng.fan@oss.nxp.com --- drivers/clk/imx/clk.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'drivers/clk/imx/clk.h') diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 5061a06468df..396a5ea75083 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -445,9 +445,10 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names, int num_parents, void __iomem *reg, + u32 domain_id, unsigned long flags); -#define imx93_clk_composite(name, parent_names, num_parents, reg) \ - imx93_clk_composite_flags(name, parent_names, num_parents, reg, \ +#define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \ + imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \ CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE) struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name, -- cgit v1.2.3