From 5b73721b60360163169a8eccd3c4285f4a605d07 Mon Sep 17 00:00:00 2001 From: Naveen Krishna Chatradhi Date: Mon, 17 Feb 2014 15:14:31 +0530 Subject: clk: samsung: exynos5250/5420: Add gate clock for SSS module This patch adds gating clock for SSS(Security SubSystem) module on Exynos5250/5420. Signed-off-by: Naveen Krishna Chatradhi [t.figa: Fixed sort order and group name.] Signed-off-by: Tomasz Figa --- drivers/clk/samsung/clk-exynos5250.c | 1 + 1 file changed, 1 insertion(+) (limited to 'drivers/clk/samsung/clk-exynos5250.c') diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c index e549e862524a..d1d53ca45e20 100644 --- a/drivers/clk/samsung/clk-exynos5250.c +++ b/drivers/clk/samsung/clk-exynos5250.c @@ -428,6 +428,7 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { * CMU_ACP */ GATE(CLK_MDMA0, "mdma0", "div_aclk266", GATE_IP_ACP, 1, 0, 0), + GATE(CLK_SSS, "sss", "div_aclk266", GATE_IP_ACP, 2, 0, 0), GATE(CLK_G2D, "g2d", "div_aclk200", GATE_IP_ACP, 3, 0, 0), GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "div_aclk266", GATE_IP_ACP, 5, 0, 0), -- cgit v1.2.3