From f16a3f6335e84c07de4b5dd263f0c26e3a3fa5a4 Mon Sep 17 00:00:00 2001 From: Matt Roper Date: Fri, 24 Mar 2023 14:04:14 -0700 Subject: drm/xe/mtl: Fix PAT table coherency settings Re-sync our MTL PAT table with the bspec. 1-way coherency should only be set on table entry 3. We do not want an incorrect setting here to accidentally paper over other bugs elsewhere in the driver. Bspec: 45101 Reviewed-by: Nirmoy Das Link: https://lore.kernel.org/r/20230324210415.2434992-6-matthew.d.roper@intel.com Signed-off-by: Matt Roper Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/xe/xe_pat.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'drivers/gpu/drm/xe/xe_pat.c') diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c index d2935ef0e274..e83f7895b853 100644 --- a/drivers/gpu/drm/xe/xe_pat.c +++ b/drivers/gpu/drm/xe/xe_pat.c @@ -54,8 +54,8 @@ const u32 pvc_pat_table[] = { const u32 mtl_pat_table[] = { [0] = MTL_PAT_0_WB, - [1] = MTL_PAT_1_WT | MTL_2_COH_1W, - [2] = MTL_PAT_3_UC | MTL_2_COH_1W, + [1] = MTL_PAT_1_WT, + [2] = MTL_PAT_3_UC, [3] = MTL_PAT_0_WB | MTL_2_COH_1W, [4] = MTL_PAT_0_WB | MTL_3_COH_2W, }; -- cgit v1.2.3