From 0bb337c97c2cdc9c0215205a81406f968c1dcae0 Mon Sep 17 00:00:00 2001 From: Suganath Prabu Subramani Date: Wed, 26 Oct 2016 13:34:38 +0530 Subject: scsi: mpt3sas: Increased/Additional MSIX support for SAS35 devices. For SAS35 devices MSIX vectors are inceased to 128 from 96. To support this Reply post host index register count is increased to 16. Also variable msix96_vector is replaced with combined_reply_queue and variable combined_reply_index_count is added to set different values for SAS3 and SAS35 devices. Signed-off-by: Chaitra P B Signed-off-by: Sathya Prakash Signed-off-by: Suganath Prabu S Reviewed-by: Hannes Reinecke Reviewed-by: Tomas Henzl Signed-off-by: Martin K. Petersen --- drivers/scsi/mpt3sas/mpt3sas_base.h | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'drivers/scsi/mpt3sas/mpt3sas_base.h') diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h index 3d75c57215b3..acb410628671 100644 --- a/drivers/scsi/mpt3sas/mpt3sas_base.h +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h @@ -300,8 +300,9 @@ * There are twelve Supplemental Reply Post Host Index Registers * and each register is at offset 0x10 bytes from the previous one. */ -#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT 12 -#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET (0x10) +#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G3 12 +#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_COUNT_G35 16 +#define MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET (0x10) /* OEM Identifiers */ #define MFG10_OEM_ID_INVALID (0x00000000) @@ -1158,7 +1159,8 @@ struct MPT3SAS_ADAPTER { u8 reply_queue_count; struct list_head reply_queue_list; - u8 msix96_vector; + u8 combined_reply_queue; + u8 combined_reply_index_count; /* reply post register index */ resource_size_t **replyPostRegisterIndex; -- cgit v1.2.3