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authorJane Jian <jane.jian@amd.com>2019-10-17 17:30:20 +0200
committerAlex Deucher <alexander.deucher@amd.com>2019-10-25 22:50:09 +0200
commit6aec5bb4892a2c4881261532e99eef86e5f1c734 (patch)
tree071e243fe09298d35e0db1663b45f7e0e99b0874
parentdrm/amd/display: Apply vactive dram clock change workaround to dcn2 DMLv2 (diff)
downloadlinux-6aec5bb4892a2c4881261532e99eef86e5f1c734.tar.xz
linux-6aec5bb4892a2c4881261532e99eef86e5f1c734.zip
drm/amdgpu: add VCN0 and VCN1 needed headers
Add mmsch part registers Signed-off-by: Jane Jian <jane.jian@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h12
1 files changed, 12 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
index cf2149cc12ee..90350f46a0c4 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/vcn/vcn_2_5_offset.h
@@ -24,6 +24,18 @@
// addressBlock: uvd0_mmsch_dec
// base address: 0x1e000
+#define mmMMSCH_VF_VMID 0x000b
+#define mmMMSCH_VF_VMID_BASE_IDX 0
+#define mmMMSCH_VF_CTX_ADDR_LO 0x000c
+#define mmMMSCH_VF_CTX_ADDR_LO_BASE_IDX 0
+#define mmMMSCH_VF_CTX_ADDR_HI 0x000d
+#define mmMMSCH_VF_CTX_ADDR_HI_BASE_IDX 0
+#define mmMMSCH_VF_CTX_SIZE 0x000e
+#define mmMMSCH_VF_CTX_SIZE_BASE_IDX 0
+#define mmMMSCH_VF_MAILBOX_HOST 0x0012
+#define mmMMSCH_VF_MAILBOX_HOST_BASE_IDX 0
+#define mmMMSCH_VF_MAILBOX_RESP 0x0013
+#define mmMMSCH_VF_MAILBOX_RESP_BASE_IDX 0
// addressBlock: uvd0_jpegnpdec