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authorJordan Crouse <jcrouse@codeaurora.org>2019-05-07 20:02:06 +0200
committerRob Clark <robdclark@chromium.org>2019-06-18 22:46:35 +0200
commitbdad5c53e10b91adf1c30cde708411da2331ee11 (patch)
tree0d63f938f06da8d8948f6f022d5cb8f94e65a7d3
parentdrm/msm/adreno: Enable 64 bit mode by default on a5xx and a6xx targets (diff)
downloadlinux-bdad5c53e10b91adf1c30cde708411da2331ee11.tar.xz
linux-bdad5c53e10b91adf1c30cde708411da2331ee11.zip
drm/msm: Print all 64 bits of the faulting IOMMU address
When we move to 64 bit addressing for a5xx and a6xx targets we will start seeing pagefaults at larger addresses so format them appropriately in the log message for easier debugging. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Signed-off-by: Rob Clark <robdclark@chromium.org>
-rw-r--r--drivers/gpu/drm/msm/msm_iommu.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c
index 12bb54cefd46..19263290b9b7 100644
--- a/drivers/gpu/drm/msm/msm_iommu.c
+++ b/drivers/gpu/drm/msm/msm_iommu.c
@@ -30,7 +30,7 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev,
struct msm_iommu *iommu = arg;
if (iommu->base.handler)
return iommu->base.handler(iommu->base.arg, iova, flags);
- pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, flags);
+ pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags);
return 0;
}