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authorAkhil R <akhilrajeev@nvidia.com>2024-04-03 12:00:36 +0200
committerHerbert Xu <herbert@gondor.apana.org.au>2024-04-12 09:07:51 +0200
commitcc370ff85bae5373330518e4ebb2d36c0ca8a470 (patch)
tree15662828d14e4a230eabcd21e2ab01898158d7a6
parentdt-bindings: crypto: Add Tegra Security Engine (diff)
downloadlinux-cc370ff85bae5373330518e4ebb2d36c0ca8a470.tar.xz
linux-cc370ff85bae5373330518e4ebb2d36c0ca8a470.zip
gpu: host1x: Add Tegra SE to SID table
Add Tegra Security Engine details to the SID table in host1x driver. These entries are required to be in place to configure the stream ID for SE. Register writes to stream ID registers fail otherwise. Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Acked-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
-rw-r--r--drivers/gpu/host1x/dev.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 89983d7d73ca..3a0aaa68ac8d 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -216,6 +216,30 @@ static const struct host1x_info host1x07_info = {
*/
static const struct host1x_sid_entry tegra234_sid_table[] = {
{
+ /* SE2 MMIO */
+ .base = 0x1658,
+ .offset = 0x90,
+ .limit = 0x90
+ },
+ {
+ /* SE4 MMIO */
+ .base = 0x1660,
+ .offset = 0x90,
+ .limit = 0x90
+ },
+ {
+ /* SE2 channel */
+ .base = 0x1738,
+ .offset = 0x90,
+ .limit = 0x90
+ },
+ {
+ /* SE4 channel */
+ .base = 0x1740,
+ .offset = 0x90,
+ .limit = 0x90
+ },
+ {
/* VIC channel */
.base = 0x17b8,
.offset = 0x30,