diff options
| author | Cédric Le Goater <clg@kaod.org> | 2022-06-03 09:37:05 +0200 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2022-09-28 05:01:40 +0200 |
| commit | da41645f11bb58eae3dda87dc459495a094f1935 (patch) | |
| tree | 32a28da805220e0bfca6ece771e7ffdd23ac6807 | |
| parent | ARM: dts: aspeed-g6: Enable more UART controllers (diff) | |
| download | linux-da41645f11bb58eae3dda87dc459495a094f1935.tar.xz linux-da41645f11bb58eae3dda87dc459495a094f1935.zip | |
ARM: dts: aspeed: ast2600-evb: Enable Quad SPI RX tranfers
Now that the pinctrl definitions of the ast2600 SoC have been fixed,
see commit 925fbe1f7eb6 ("dt-bindings: pinctrl: aspeed-g6: add FWQSPI
function/group"), it is safe to activate QSPI on the ast2600 evb.
Cc: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
Tested-by: Jae Hyun Yoo <quic_jaehyoo@quicinc.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Link: https://lore.kernel.org/r/20220603073705.1624351-1-clg@kaod.org
Signed-off-by: Joel Stanley <joel@jms.id.au>
| -rw-r--r-- | arch/arm/boot/dts/aspeed-ast2600-evb.dts | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 14dbeaee7ee3..5c6eacb43c03 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -182,6 +182,7 @@ status = "okay"; m25p,fast-read; label = "bmc"; + spi-rx-bus-width = <4>; spi-max-frequency = <50000000>; #include "openbmc-flash-layout-64.dtsi" }; @@ -196,6 +197,7 @@ status = "okay"; m25p,fast-read; label = "pnor"; + spi-rx-bus-width = <4>; spi-max-frequency = <100000000>; }; }; |