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authorIlpo Järvinen <ilpo.jarvinen@linux.intel.com>2024-10-18 16:47:47 +0200
committerBjorn Helgaas <bhelgaas@google.com>2024-10-23 23:49:46 +0200
commitfad610b987132868e3410c530871086552ce6155 (patch)
treebec9babe636c3389fcaaea7154ad03966c354bdd
parentLinux 6.12-rc1 (diff)
downloadlinux-fad610b987132868e3410c530871086552ce6155.tar.xz
linux-fad610b987132868e3410c530871086552ce6155.zip
Documentation PCI: Reformat RMW ops documentation
Extract the list of RMW protected PCIe Capability registers into a bullet list to make them easier to pick up on a glance. An upcoming change is going to add one more register among them so it will be much cleaner to have them as bullets. Link: https://lore.kernel.org/r/20241018144755.7875-2-ilpo.jarvinen@linux.intel.com Signed-off-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Lukas Wunner <lukas@wunner.de> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
-rw-r--r--Documentation/PCI/pciebus-howto.rst13
1 files changed, 8 insertions, 5 deletions
diff --git a/Documentation/PCI/pciebus-howto.rst b/Documentation/PCI/pciebus-howto.rst
index f344452651e1..e48d01422efc 100644
--- a/Documentation/PCI/pciebus-howto.rst
+++ b/Documentation/PCI/pciebus-howto.rst
@@ -217,8 +217,11 @@ capability structure except the PCI Express capability structure,
that is shared between many drivers including the service drivers.
RMW Capability accessors (pcie_capability_clear_and_set_word(),
pcie_capability_set_word(), and pcie_capability_clear_word()) protect
-a selected set of PCI Express Capability Registers (Link Control
-Register and Root Control Register). Any change to those registers
-should be performed using RMW accessors to avoid problems due to
-concurrent updates. For the up-to-date list of protected registers,
-see pcie_capability_clear_and_set_word().
+a selected set of PCI Express Capability Registers:
+
+* Link Control Register
+* Root Control Register
+
+Any change to those registers should be performed using RMW accessors to
+avoid problems due to concurrent updates. For the up-to-date list of
+protected registers, see pcie_capability_clear_and_set_word().