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author | Andrew Davis <afd@ti.com> | 2023-11-13 15:43:59 +0100 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2023-12-22 15:23:30 +0100 |
commit | 671c08ec007b2f859d9075fc9bc0c06320c90cd4 (patch) | |
tree | a550b0610f2ea2c06701f94a5e52efbaf6c4ab22 /arch/arm/mach-nspire/Kconfig | |
parent | ARM: mach-sunplus: Rework support and directory structure (diff) | |
download | linux-671c08ec007b2f859d9075fc9bc0c06320c90cd4.tar.xz linux-671c08ec007b2f859d9075fc9bc0c06320c90cd4.zip |
ARM: mach-nspire: Rework support and directory structure
Having a platform need a mach-* directory should be seen as a negative,
it means the platform needs special non-standard handling. ARM64 support
does not allow mach-* directories at all. While we may not get to that
given all the non-standard architectures we support, we should still try
to get as close as we can and reduce the number of mach directories.
The mach-nspire/ directory and files, provides just one "feature":
having the kernel print the machine name if the DTB does not also contain
a "model" string (which they always do). To reduce the number of mach-*
directories let's do without that feature and remove this directory.
NOTE: The default l2c_aux_mask is now ~0 but these devices never have
this type of cache controller so this is safe.
Signed-off-by: Andrew Davis <afd@ti.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-nspire/Kconfig')
-rw-r--r-- | arch/arm/mach-nspire/Kconfig | 15 |
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/arm/mach-nspire/Kconfig b/arch/arm/mach-nspire/Kconfig deleted file mode 100644 index 0ffdcaca1e6b..000000000000 --- a/arch/arm/mach-nspire/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only -config ARCH_NSPIRE - bool "TI-NSPIRE based" - depends on ARCH_MULTI_V4T - depends on CPU_LITTLE_ENDIAN - select CPU_ARM926T - select GENERIC_IRQ_CHIP - select ARM_AMBA - select ARM_VIC - select ARM_TIMER_SP804 - select NSPIRE_TIMER - select POWER_RESET - select POWER_RESET_SYSCON - help - This enables support for systems using the TI-NSPIRE CPU |