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| author | Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> | 2021-12-23 08:56:40 +0100 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-02-01 01:20:29 +0100 |
| commit | ffd6cc92ab9cb426896481fa8372d38cbe53f76b (patch) | |
| tree | 62753be36227fe9ab2ed3fa6ca9fe960eae561d0 /arch/arm64/boot/dts/qcom/sm8250.dtsi | |
| parent | arm64: dts: qcom: sdm845: add missing power-controller compatible (diff) | |
| download | linux-ffd6cc92ab9cb426896481fa8372d38cbe53f76b.tar.xz linux-ffd6cc92ab9cb426896481fa8372d38cbe53f76b.zip | |
arm64: dts: qcom: sm8250: add description of dcvsh interrupts
The change adds SM8250 cpufreq-epss controller interrupts for each
CPU core cluster.
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Cc: Thara Gopinath <thara.gopinath@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211223075640.2924569-1-vladimir.zapolskiy@linaro.org
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sm8250.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sm8250.dtsi | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index db57c115d262..88cd82ed75b7 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -4571,7 +4571,10 @@ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; clock-names = "xo", "alternate"; - + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; }; }; |