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| author | Marek Vasut <marex@denx.de> | 2024-10-17 21:09:18 +0200 |
|---|---|---|
| committer | Alexandre Torgue <alexandre.torgue@foss.st.com> | 2024-10-29 16:20:39 +0100 |
| commit | 3f2e7d167307527f49bf4a03d99bd4d3867f7adb (patch) | |
| tree | d14c8a17881c11321d947e935de1180a47543c4d /arch/arm | |
| parent | ARM: dts: stm32: Add IWDG2 EXTI interrupt mapping and mark as wakeup source (diff) | |
| download | linux-3f2e7d167307527f49bf4a03d99bd4d3867f7adb.tar.xz linux-3f2e7d167307527f49bf4a03d99bd4d3867f7adb.zip | |
ARM: dts: stm32: Describe M24256E write-lockable page in DH STM32MP13xx DHCOR SoM DT
The STM32MP13xx DHCOR SoM is populated with M24256E EEPROM which has
Additional Write lockable page at separate I2C address. Describe the
page in DT to make it available.
Note that the WLP page on this device is hardware write-protected by
R37 which pulls the nWC signal high to VDD_3V3_1V8 power rail.
Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi index ddad6497775b..5edbc790d1d2 100644 --- a/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/st/stm32mp13xx-dhcor-som.dtsi @@ -201,6 +201,12 @@ pagesize = <64>; }; + eeprom0wl: eeprom@58 { + compatible = "st,24256e-wl"; /* ST M24256E WL page of 0x50 */ + pagesize = <64>; + reg = <0x58>; + }; + rv3032: rtc@51 { compatible = "microcrystal,rv3032"; reg = <0x51>; |