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authorAndrew Jones <ajones@ventanamicro.com>2022-10-02 06:48:59 +0200
committerAnup Patel <anup@brainfault.org>2022-10-02 06:48:59 +0200
commitafd5dde9a186b8fc5742fff707f184760c4af1a9 (patch)
treec904eeb853e64c2e09c234412c0a0fe5105fff6a /arch/riscv/mm
parentRISC-V: KVM: Make ISA ext mappings explicit (diff)
downloadlinux-afd5dde9a186b8fc5742fff707f184760c4af1a9.tar.xz
linux-afd5dde9a186b8fc5742fff707f184760c4af1a9.zip
RISC-V: KVM: Provide UAPI for Zicbom block size
We're about to allow guests to use the Zicbom extension. KVM userspace needs to know the cache block size in order to properly advertise it to the guest. Provide a virtual config register for userspace to get it with the GET_ONE_REG API, but setting it cannot be supported, so disallow SET_ONE_REG. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Signed-off-by: Anup Patel <anup@brainfault.org>
Diffstat (limited to 'arch/riscv/mm')
-rw-r--r--arch/riscv/mm/dma-noncoherent.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
index e3f9bdf47c5f..b0add983530a 100644
--- a/arch/riscv/mm/dma-noncoherent.c
+++ b/arch/riscv/mm/dma-noncoherent.c
@@ -13,6 +13,8 @@
#include <asm/cacheflush.h>
unsigned int riscv_cbom_block_size;
+EXPORT_SYMBOL_GPL(riscv_cbom_block_size);
+
static bool noncoherent_supported;
void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,