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| author | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2014-04-15 12:55:07 +0200 |
|---|---|---|
| committer | Martin Schwidefsky <schwidefsky@de.ibm.com> | 2014-05-20 08:58:47 +0200 |
| commit | d3a73acbc26a4a81a01a35fd162973e53d0386f5 (patch) | |
| tree | 5b8fd3880f3b38575b1a043f3f4f07623a633bd1 /arch/s390/include/asm/mmu_context.h | |
| parent | s390/uaccess: simplify control register updates (diff) | |
| download | linux-d3a73acbc26a4a81a01a35fd162973e53d0386f5.tar.xz linux-d3a73acbc26a4a81a01a35fd162973e53d0386f5.zip | |
s390: split TIF bits into CIF, PIF and TIF bits
The oi and ni instructions used in entry[64].S to set and clear bits
in the thread-flags are not guaranteed to be atomic in regard to other
CPUs. Split the TIF bits into CPU, pt_regs and thread-info specific
bits. Updates on the TIF bits are done with atomic instructions,
updates on CPU and pt_regs bits are done with non-atomic instructions.
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Diffstat (limited to 'arch/s390/include/asm/mmu_context.h')
| -rw-r--r-- | arch/s390/include/asm/mmu_context.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h index 93ec0c8e4c83..056d7eff2a16 100644 --- a/arch/s390/include/asm/mmu_context.h +++ b/arch/s390/include/asm/mmu_context.h @@ -36,7 +36,7 @@ static inline void set_user_asce(struct mm_struct *mm) S390_lowcore.user_asce = mm->context.asce_bits | __pa(pgd); set_fs(current->thread.mm_segment); - set_thread_flag(TIF_ASCE); + set_cpu_flag(CIF_ASCE); } static inline void clear_user_asce(void) @@ -54,7 +54,7 @@ static inline void load_kernel_asce(void) __ctl_store(asce, 1, 1); if (asce != S390_lowcore.kernel_asce) __ctl_load(S390_lowcore.kernel_asce, 1, 1); - set_thread_flag(TIF_ASCE); + set_cpu_flag(CIF_ASCE); } static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, @@ -70,7 +70,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, __ctl_load(S390_lowcore.kernel_asce, 1, 1); __ctl_load(S390_lowcore.kernel_asce, 7, 7); /* Delay loading of the new ASCE to control registers CR1 & CR7 */ - set_thread_flag(TIF_ASCE); + set_cpu_flag(CIF_ASCE); atomic_inc(&next->context.attach_count); atomic_dec(&prev->context.attach_count); if (MACHINE_HAS_TLB_LC) |