diff options
| author | Nicholas Piggin <npiggin@gmail.com> | 2022-05-20 14:36:49 +0200 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2022-07-27 13:36:04 +0200 |
| commit | 28f07fab26319dacc5675ae01dfc84d82122c59b (patch) | |
| tree | 39715eb682c3033d17f267329ef03cf7704ac4b9 /arch | |
| parent | powerpc/pci: Add config option for using all 256 PCI buses (diff) | |
| download | linux-28f07fab26319dacc5675ae01dfc84d82122c59b.tar.xz linux-28f07fab26319dacc5675ae01dfc84d82122c59b.zip | |
powerpc/vdso: Fix __kernel_sync_dicache sequence with coherent icache
Processors with coherent icache require the sequence sync ; icbi ; isync
to entire store->execute coherency. icbi (to any address) must be
executed to ensure isync flushes the pipeline. See "POWER9 Processor
User's Manual, 4.6.2.2 Instruction Cache Block Invalidate (icbi)" for
details.
__kernel_sync_dicache is missing icbi for the coherent icache path.
Add it.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220520123649.258440-1-npiggin@gmail.com
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/powerpc/kernel/vdso/cacheflush.S | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/powerpc/kernel/vdso/cacheflush.S b/arch/powerpc/kernel/vdso/cacheflush.S index d4e43ab2d5df..0085ae464dac 100644 --- a/arch/powerpc/kernel/vdso/cacheflush.S +++ b/arch/powerpc/kernel/vdso/cacheflush.S @@ -91,6 +91,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_COHERENT_ICACHE) 3: crclr cr0*4+so sync + icbi 0,r1 isync li r3,0 blr |