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| author | Zichen Xie <zichenxie0106@gmail.com> | 2024-10-23 16:51:47 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-10-29 00:47:22 +0100 |
| commit | 00f8f70a0e8c6601861628be26270a0b6f4bbb34 (patch) | |
| tree | 47baf214f140a2abc78179a4527d66d057c6d1a4 /drivers/clk/sophgo | |
| parent | clk: tegra: use clamp() in tegra_bpmp_clk_determine_rate() (diff) | |
| download | linux-00f8f70a0e8c6601861628be26270a0b6f4bbb34.tar.xz linux-00f8f70a0e8c6601861628be26270a0b6f4bbb34.zip | |
clk: sophgo: avoid integer overflow in sg2042_pll_recalc_rate()
This was found by a static analyzer.
There may be a potential integer overflow issue in
sg2042_pll_recalc_rate(). numerator is defined as u64 while
parent_rate is defined as unsigned long and ctrl_table.fbdiv
is defined as unsigned int. On 32-bit machine, the result of
the calculation will be limited to "u32" without correct casting.
Integer overflow may occur on high-performance systems.
Fixes: 48cf7e01386e ("clk: sophgo: Add SG2042 clock driver")
Signed-off-by: Zichen Xie <zichenxie0106@gmail.com>
Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/20241023145146.13130-1-zichenxie0106@gmail.com
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Diffstat (limited to 'drivers/clk/sophgo')
| -rw-r--r-- | drivers/clk/sophgo/clk-sg2042-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/sophgo/clk-sg2042-pll.c b/drivers/clk/sophgo/clk-sg2042-pll.c index ff9deeef509b..1537f4f05860 100644 --- a/drivers/clk/sophgo/clk-sg2042-pll.c +++ b/drivers/clk/sophgo/clk-sg2042-pll.c @@ -153,7 +153,7 @@ static unsigned long sg2042_pll_recalc_rate(unsigned int reg_value, sg2042_pll_ctrl_decode(reg_value, &ctrl_table); - numerator = parent_rate * ctrl_table.fbdiv; + numerator = (u64)parent_rate * ctrl_table.fbdiv; denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2; do_div(numerator, denominator); return numerator; |