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| author | Anup Patel <apatel@ventanamicro.com> | 2023-07-10 15:19:01 +0200 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2023-11-01 03:15:48 +0100 |
| commit | 5d98446f03c622cb917e15a5561601587c64aab2 (patch) | |
| tree | 2fe485cdec9a3858c756d7fa704749342a993b64 /drivers/clocksource/timer-tegra.c | |
| parent | Merge patch series "RISC-V: Enable cbo.zero in usermode" (diff) | |
| download | linux-5d98446f03c622cb917e15a5561601587c64aab2.tar.xz linux-5d98446f03c622cb917e15a5561601587c64aab2.zip | |
clocksource: timer-riscv: Don't enable/disable timer interrupt
Currently, we enable/disable timer interrupt at runtime to start/stop
timer events. This makes timer interrupt state go out-of-sync with
the Linux interrupt subsystem.
To address the above issue, we can stop a per-HART timer interrupt
by setting U64_MAX in timecmp CSR (or sbi_set_timer()) at the time
of handling timer interrupt.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Link: https://lore.kernel.org/r/20230710131902.1459180-2-apatel@ventanamicro.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
Diffstat (limited to 'drivers/clocksource/timer-tegra.c')
0 files changed, 0 insertions, 0 deletions