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authorShen Lichuan <shenlichuan@vivo.com>2024-09-30 04:33:44 +0200
committerTakashi Sakamoto <o-takashi@sakamocchi.jp>2024-10-01 12:02:57 +0200
commit8f04019d71cb870ca40960777b1b4720483cabac (patch)
tree272ace2afa8e8936762190beed584d7b31ba05b0 /drivers/firewire/ohci.c
parentLinux 6.12-rc1 (diff)
downloadlinux-8f04019d71cb870ca40960777b1b4720483cabac.tar.xz
linux-8f04019d71cb870ca40960777b1b4720483cabac.zip
firewire: Correct some typos
Fixed some confusing typos that were currently identified with codespell, the details are as follows: drivers/firewire/core-topology.c:59: containted ==> contained drivers/firewire/core.h:83: reenable ==> re-enable drivers/firewire/ohci.c:1387: apppends ==> appends drivers/firewire/ohci.c:2216: superceded ==> superseded drivers/firewire/ohci.c:2617: litte ==> little Signed-off-by: Shen Lichuan <shenlichuan@vivo.com> Link: https://lore.kernel.org/r/20240930023344.7535-1-shenlichuan@vivo.com Signed-off-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Diffstat (limited to 'drivers/firewire/ohci.c')
-rw-r--r--drivers/firewire/ohci.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/firewire/ohci.c b/drivers/firewire/ohci.c
index 7ee55c2804de..4dbd20360223 100644
--- a/drivers/firewire/ohci.c
+++ b/drivers/firewire/ohci.c
@@ -1384,7 +1384,7 @@ struct driver_data {
};
/*
- * This function apppends a packet to the DMA queue for transmission.
+ * This function appends a packet to the DMA queue for transmission.
* Must always be called with the ochi->lock held to ensure proper
* generation handling and locking around packet queue manipulation.
*/
@@ -2213,7 +2213,7 @@ static irqreturn_t irq_handler(int irq, void *data)
if (unlikely(param_debug > 0)) {
dev_notice_ratelimited(ohci->card.device,
- "The debug parameter is superceded by tracepoints events, and deprecated.");
+ "The debug parameter is superseded by tracepoints events, and deprecated.");
}
/*
@@ -2614,7 +2614,7 @@ static int ohci_set_config_rom(struct fw_card *card,
* ConfigRomHeader and BusOptions doesn't honor the
* noByteSwapData bit, so with a be32 config rom, the
* controller will load be32 values in to these registers
- * during the atomic update, even on litte endian
+ * during the atomic update, even on little endian
* architectures. The workaround we use is to put a 0 in the
* header quadlet; 0 is endian agnostic and means that the
* config rom isn't ready yet. In the bus reset tasklet we