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| author | Christian König <christian.koenig@amd.com> | 2017-11-03 15:59:25 +0100 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-12-06 18:47:21 +0100 |
| commit | c47b41a79ab5e8faec9aea6c4a06c4d1e4d1132f (patch) | |
| tree | 97820364b390c2b55ace5d1d27faf14c1f8193fb /drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | |
| parent | drm/amdgpu: use dep_sync for CS dependency/syncobj (diff) | |
| download | linux-c47b41a79ab5e8faec9aea6c4a06c4d1e4d1132f.tar.xz linux-c47b41a79ab5e8faec9aea6c4a06c4d1e4d1132f.zip | |
drm/amdgpu: remove nonsense const u32 cast on ARRAY_SIZE result
Not sure what that should originally been good for, but it doesn't seem
to make any sense any more.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/dce_v11_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index be25706e5f07..67e670989e81 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -156,26 +156,26 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, - (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); + ARRAY_SIZE(cz_mgcg_cgcg_init)); amdgpu_program_register_sequence(adev, cz_golden_settings_a11, - (const u32)ARRAY_SIZE(cz_golden_settings_a11)); + ARRAY_SIZE(cz_golden_settings_a11)); break; case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, - (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); + ARRAY_SIZE(stoney_golden_settings_a11)); break; case CHIP_POLARIS11: case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, polaris11_golden_settings_a11, - (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); + ARRAY_SIZE(polaris11_golden_settings_a11)); break; case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, polaris10_golden_settings_a11, - (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); + ARRAY_SIZE(polaris10_golden_settings_a11)); break; default: break; |